Datasheet

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STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics
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5.3.15 MIPI D-PHY regulator characteristics
The parameters given in Table 55 are derived from tests performed under temperature and
V
DD
supply voltage conditions summarized in Table 18.
I
DD(PLL)
PLL power consumption on V
DD12
f
VCO_OUT
= 500 MHz - 0.55 0.70
mAf
VCO_OUT
= 600 MHz - 0.65 0.80
f
VCO_OUT
= 1000 MHz - 0.95 1.20
1. Based on test during characterization.
Table 54. DSI-PLL characteristics
(1)
(continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 55. DSI regulator characteristics
(1)
Symbol Parameter Conditions Min Typ Max Unit
V
DD12DSI
1.2 V internal voltage on V
DD12DSI
- 1.15 1.20 1.30 V
C
EXT
External capacitor on V
CAPDSI
- 1.1 2.2 3.3 F
ESR External Serial Resistor - 0 25 600 m
I
DDDSIREG
Regulator power consumption - 100 120 125 µA
I
DDDSI
DSI system (regulator, PLL and
D-PHY) current consumption on V
DDDSI
Ultra Low Power Mode
(Reg. ON + PLL OFF)
-290600
µA
Stop State
(Reg. ON + PLL OFF)
-290600
I
DDDSILP
DSI system current consumption on
V
DDDSI
in LP mode communication
(2)
10 MHz escape clock
(Reg. ON + PLL OFF)
-4.35.0
mA
20 MHz escape clock
(Reg. ON + PLL OFF)
-4.35.0
I
DDDSIHS
DSI system (regulator, PLL and
D-PHY) current consumption on V
DDDSI
in HS mode communication
(3)
300 Mbps - 1 data lane
(Reg. ON + PLL ON)
-8.08.8
mA
300 Mbps - 2data lane
(Reg. ON + PLL ON)
- 11.4 12.5
500 Mbps - 1 data lane
(Reg. ON + PLL ON)
-13.514.7
500 Mbps - 2data lane
(Reg. ON + PLL ON)
-18.019.6
DSI system (regulator, PLL and
D-PHY) current consumption on V
DDDSI
in HS mode with CLK like payload
500 Mbps - 2data lane
(Reg. ON + PLL ON)
-21.423.3
t
WAKEUP
Startup delay
C
EXT
= 2.2 µF - 110 -
µs
C
EXT
= 3.3 µF - - 160
I
INRUSH
Inrush current on V
DDDSI
External capacitor load at start - 60 200 mA
1. Based on test during characterization.
2. Values based on an average traffic in LP Command Mode.
3. Values based on an average traffic (3/4 HS traffic & 1/4 LP) in Video Mode.
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