Datasheet

Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
148/255 DocID029041 Rev 6
V
IL
Output low level voltage - 1.1 1.2 1.2 V
V
IL-ULPS
Output high level voltage - -50 - 50 mV
V
IH
Output impedance of LP
transmitter
-110--
V
hys
15%-85% rise and fall time - - - 25 ns
LP Contention Detector Characteristics
V
ILCD
Logic 0 contention threshold - - - 200
mV
V
IHCD
Logic 0 contention threshold - 450 - -
1. Guaranteed based on test during characterization.
Table 53. MIPI D-PHY AC characteristics LP mode and HS/LP
transitions
(1)
Symbol Parameter Conditions Min Typ Max Unit
T
LPX
Transmitted length of any Low-
Power state period
-50--
ns
T
CLK-PREPARE
Time that the transmitter drives
the Clock Lane LP-00 Line
state immediately before the
HS-0 Line state starting the HS
transmission.
-38-95
T
CLK-PREPARE
+
T
CLK-ZERO
Time that the transmitter drives
the HS-0 state prior to starting
the clock.
- 300 - -
T
CLK-PRE
Time that the HS clock shall be
driven by the transmitter prior to
any associated Data Lane
beginning the transition from
LP to HS mode.
-8--UI
Table 52. MIPI D-PHY characteristics
(1)
(continued)
Symbol Parameter Conditions Min Typ Max Unit
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