Datasheet

Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
114/255 DocID029041 Rev 6
5.3.2 VCAP1/VCAP2 external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor C
EXT
to
the VCAP1/VCAP2 pins. C
EXT
is specified in Table 20.
Figure 28. External capacitor C
EXT
1. Legend: ESR is the equivalent series resistance.
6. It is recommended to power V
DD
and V
DDA
from the same source. A maximum difference of 300 mV between V
DD
and
V
DDA
can be tolerated during power-up and power-down operation.
7. The over-drive mode is not supported when the internal regulator is OFF.
8. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
9. If T
A
is lower, higher P
D
values are allowed as long as T
J
does not exceed T
Jmax
.
10. In low power dissipation state, T
A
can be extended to this range as long as T
J
does not exceed T
Jmax
.
Table 19. Limitations depending on the operating power supply range
Operating
power supply
range
ADC operation
Maximum Flash
memory access
frequency with
no wait states
(f
Flashmax
)
Maximum HCLK
frequency vs Flash
memory wait states
(1)(2)
I/O operation
Possible Flash
memory
operations
V
DD
=1.7 to
2.1 V
(3)
Conversion time
up to 1.2 Msps
20 MHz
180 MHz with 8 wait
states and over-drive
OFF
No I/O
compensation
8-bit erase and
program
operations only
V
DD
= 2.1 to
2.4 V
Conversion time
up to 1.2 Msps
22 MHz
216 MHz with 9 wait
states and over-drive
ON
No I/O
compensation
16-bit erase and
program
operations
V
DD
= 2.4 to
2.7 V
Conversion time
up to 2.4 Msps
24 MHz
216 MHz with 8 wait
states and over-drive
ON
I/O compensation
works
16-bit erase and
program
operations
V
DD
= 2.7 to
3.6 V
(4)
Conversion time
up to 2.4 Msps
30 MHz
216 MHz with 6 wait
states and over-drive
ON
I/O compensation
works
32-bit erase and
program
operations
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states given here
does not impact the execution speed from Flash memory since the ART accelerator or L1-cache allows to achieve a
performance equivalent to 0-wait state program execution.
3. V
DD
/V
DDA
minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.18.2:
Internal reset OFF).
4. The voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+
pins will be degraded between 2.7 and 3 V.
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