Datasheet

Functional overview STM32F413xG/H
28/208 DocID029162 Rev 6
3.18.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
• MR is used in the nominal regulation mode (With different voltage scaling in Run mode)
In Main regulator mode (MR mode), different voltage scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
• LPR is used in the Stop mode
The LP regulator mode is configured by software when entering Stop mode.
• Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Depending on the package, one or two external ceramic capacitors should be connected on
the V
CAP_1 and VCAP_2 pins. The VCAP_2 pin is only available on 100- and 144-pin
packages.
All packages have the regulator ON feature.
3.18.2 Regulator OFF
This feature is available only on UFBGA100 and UFBGA144 packages, which feature the
BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator
OFF mode allows to supply externally a V
12
voltage source through V
CAP_1
and V
CAP_2
pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency.
The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling
capacitors.
When the regulator is OFF, there is no more internal monitoring on V
12
. An external power
supply supervisor should be used to monitor the V
12
of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V
12
power domain.
In regulator OFF mode, the following features are no more supported:
• PA0 cannot be used as a GPIO pin since it allows to reset a part of the V
12
logic power
domain which is not reset by the NRST pin.
• As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
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