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This is information on a product in full production.

September 2017 DocID029162 Rev 6 1/208

STM32F413xG STM32F413xH

Arm

-Cortex

-M4 32b MCU+FPU, 125 DMIPS, up to 1.5MB Flash,

320KB RAM, USB OTG FS, 1 ADC, 2 DACs, 2 DFSDMs

Datasheet - production data

Features

• Dynamic Efficiency Line with eBAM (enhanced

Batch Acquisition Mode)

– 1.7 V to 3.6 V power supply

– -40 °C to 85/105/125 °C temperature range

• Core: Arm

32-bit Cortex

-M4 CPU with FPU,

Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait state execution

from Flash memory, frequency up to 100 MHz,

memory protection unit, 125 DMIPS/

1.25 DMIPS/MHz (Dhrystone 2.1), and DSP

instructions

• Memories

– Up to 1.5 Mbytes of Flash memory

– 320 Kbytes of SRAM

– Flexible external static memory controller

with up to 16-bit data bus: SRAM, PSRAM,

NOR Flash memory

– Dual mode Quad-SPI interface

• LCD parallel interface, 8080/6800 modes

• Clock, reset and supply management

– 1.7 to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– 4-to-26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

• Power consumption

– Run: 112 µA/MHz (peripheral off)

– Stop (Flash in Stop mode, fast wakeup

time): 42 µA Typ.; 80 µA max @25 °C

– Stop (Flash in Deep power down mode,

slow wakeup time): 15 µA Typ.;

46 µA max @25 °C

– Standby without RTC: 1.1 µA Typ.;

14.7 µA max at @85 °C

– V

BAT

supply for RTC: 1 µA @25 °C

• 2x12-bit D/A converters

• 1×12-bit, 2.4 MSPS ADC: up to 16 channels

• 6x digital filters for sigma delta modulator,

12x PDM interfaces, with stereo microphone

and sound source localization support

• General-purpose DMA: 16-stream DMA

• Up to 18 timers: up to twelve 16-bit timers, two

32-bit timers up to 100 MHz each with up to

four IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input, two

watchdog timers (independent and window),

one SysTick timer, and a low-power timer

• Debug mode

– Serial wire debug (SWD) & JTAG

–Cortex

-M4 Embedded Trace Macrocell™

• Up to 114 I/O ports with interrupt capability

– Up to 109 fast I/Os up to 100 MHz

– Up to 114 five V-tolerant I/Os

• Up to 24 communication interfaces

– Up to 4x I

C interfaces (SMBus/PMBus)

– Up to 10 UARTS: 4 USARTs / 6 UARTs

(2 x 12.5 Mbit/s, 2 x 6.25 Mbit/s), ISO 7816

interface, LIN, IrDA, modem control)

– Up to 5 SPI/I2Ss (up to 50 Mbit/s, SPI or

I2S audio protocol), out of which 2 muxed

full-duplex I2S interfaces

– SDIO interface (SD/MMC/eMMC)

– Advanced connectivity: USB 2.0 full-speed

device/host/OTG controller with PHY

– 3x CAN (2.0B Active)

– 1xSAI

• True random number generator

• CRC calculation unit

• 96-bit unique ID

• RTC: subsecond accuracy, hardware calendar

• All packages are ECOPACK

Table 1. Device summary

Reference Part number

STM32F413xH

STM32F413CH STM32F413MH STM32F413RH

STM32F413VH STM32F413ZH

STM32F413xG

STM32F413CG STM32F413MG STM32F413RG

STM32F413VG STM32F413ZG

)%*$

UFQFPN48

(7x7 mm)

UFBGA100

(7x7mm)

UFBGA144

(10x10mm)

LQFP100 (14x14mm)

LQFP144 (20x20mm)

LQFP64 (10x10mm)

WLCSP81

(4.039x3.951 mm)

www.st.com

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Summary of content (208 pages)

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STM32F413xG STM32F413xH Arm®-Cortex®-M4 32b MCU+FPU, 125 DMIPS, up to 1.5MB Flash, 320KB RAM, USB OTG FS, 1 ADC, 2 DACs, 2 DFSDMs Datasheet - production data Features )%*$ • Dynamic Efficiency Line with eBAM (enhanced Batch Acquisition Mode) – 1.7 V to 3.
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Contents STM32F413xG/H Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 Arm® Cortex®-M4 with FPU core with embedded Flash and SRAM . . . . 19 3.2 Adaptive real-time memory accelerator (ART Accelerator™) .
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STM32F413xG/H Contents 3.22 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4 3.22.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.22.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.22.3 Basic timer (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.22.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . .
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Contents STM32F413xG/H 4.7 UFBGA144 pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.8 Pins definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.9 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6 Electrical characteristics . . . . . . . .
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STM32F413xG/H 7 Contents 6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 6.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 6.3.24 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 6.3.25 DFSDM characteristics . . . . . . . . . . . . . . . . . . .
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List of tables STM32F413xG/H List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. 6/208 Downloaded from Arrow.com. Device summary . . . . . . . . . . . .
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STM32F413xG/H Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89.
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List of tables Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. 8/208 Downloaded from Arrow.com. STM32F413xG/H Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F413xG/H List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
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List of figures Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87.
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STM32F413xG/H Figure 88. Figure 89. List of figures for VBUS sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 USB peripheral-only Full speed mode, VBUS detection using GPIO . . . . . . . . . . . . . . . . 205 USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 205 DocID029162 Rev 6 11/208 11 Downloaded from Arrow.com.
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Introduction 1 STM32F413xG/H Introduction This datasheet provides the description of the STM32F413xG/H microcontrollers. For information on the Cortex®-M4 core, please refer to the Cortex®-M4 programming manual (PM0214) available from www.st.com. 12/208 Downloaded from Arrow.com.
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STM32F413xG/H 2 Description Description The STM32F413XG/H devices are based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 100 MHz. Their Cortex®-M4 core features a Floating point unit (FPU) single precision which supports all Arm single-precision dataprocessing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
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Description STM32F413xG/H These features make the STM32F413xG/H microcontrollers suitable for a wide range of applications: 14/208 Downloaded from Arrow.com.
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STM32F413xG/H Description Table 2.
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Description 2.1 STM32F413xG/H Compatibility with STM32F4 series The STM32F413xG/H are fully software and feature compatible with the STM32F4 series (STM32F42x, STM32F401, STM32F43x, STM32F41x, STM32F405 and STM32F407) The STM32F413xG/H can be used as drop-in replacement of the other STM32F4 products but some slight changes have to be done on the PCB board. Figure 1.
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STM32F413xG/H Description Figure 2. Compatible board design for LQFP64 package 670 ) [[ 670 ) [[ 670 ) [[ 670 ) [[ 670 ) [[ 670 ) [[ 670 ) [[ 9'' 9&$3B 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 9'' 966 3% QRW DYDLODEOH DQ\PRUH 5HSODFHG E\ 9&$3B 9'' 966 3$ 3$ 3$ 3$ 3$ 966 3$ 3& 3& 3& 3& 3% 3% 3% 3% 9'' 3% 3% 9&$3B 966 9'' 3% 3% 3% 9&$3B 9''
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Description STM32F413xG/H Figure 4. STM32F413xG/H block diagram 038 )38 (70 )60& 125 )ODVK 65$0 365$0 $+% -7$* 6: .% 65$0 , %86 ' %86 .% 65$0 6 %86 $&&(/ &$&+( $50 &RUWH[ 0 &RUWH[ 0 0+] &/. 1(> @ $> @ '> @ 12(1 1:(1 1%/> @ 1:$,7 &/. &6$ &6% '> @ 4XDG 63, 19,& $+% EXV PDWUL[ 6 0 -7567 -7', -7&. 6:&/. -7'2 6:' -7'2 75$&(&/. 75$&('> @ 8S WR 0% )ODVK PHPRU\ 51* ),)2 *3,2 3257 $ 3%> @ *3,2 3257 % $+% 0+] 6WUHDPV '0$ 3$>
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STM32F413xG/H Functional overview 3 Functional overview 3.1 Arm® Cortex®-M4 with FPU core with embedded Flash and SRAM The Arm® Cortex®-M4 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
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Functional overview STM32F413xG/H A dedicated application note (AN4515) describes how to implement the STM32F413xG/H BAM to allow the best power efficiency. 3.4 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas.
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STM32F413xG/H 3.7 Functional overview Embedded SRAM All devices embed 320 Kbytes of system SRAM which can be accessed (read/write) at CPU clock speed with 0 wait states. 3.8 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves (Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. Figure 5.
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Functional overview 3.9 STM32F413xG/H DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB).
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STM32F413xG/H 3.11 Functional overview Quad-SPI memory interface (QUAD-SPI) All devices embed a Quad-SPI memory interface, which is a specialized communication interface targeting single, dual or quad-SPI Flash memories. It can work in direct mode through registers, external Flash status register polling mode and memory mapped mode. Up to 256 Mbyte of external Flash memory are mapped. They can be accessed in 8, 16 or 32-bit mode. Code execution is also supported.
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Functional overview STM32F413xG/H buses and high-speed APB domains is 100 MHz. The maximum allowed frequency of the low-speed APB domain is 50 MHz. The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 3.
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STM32F413xG/H 3.16 Note: Functional overview Power supply schemes • VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor (POR/PDR) disabled, provided externally through VDD pins. Requires the use of an external power supply supervisor connected to the VDD and NRST pins. • VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively, with decoupling technique.
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Functional overview STM32F413xG/H Figure 6. VDDUSB connected to an external independent power supply 9''86%B0$; 86% IXQFWLRQDO DUHD 9''86% 9''86%B0,1 86% QRQ IXQFWLRQDO DUHD 9'' 9''$ 86% QRQ IXQFWLRQDO DUHD 9''B0,1 2SHUDWLQJ PRGH 3RZHU RQ 3RZHU GRZQ WLPH 06 9 3.17 Power supply supervisor 3.17.1 Internal reset ON This feature is available for VDD operating voltage range 1.8 V to 3.6 V. On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high.
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STM32F413xG/H 3.17.2 Functional overview Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to low. An external power supply supervisor should monitor VDD and should set the device in reset mode when VDD is below 1.7 V. NRST should be connected to this external power supply supervisor.
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Functional overview 3.18.1 STM32F413xG/H Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled.
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STM32F413xG/H Functional overview Figure 8. Regulator OFF 9 ([WHUQDO 9&$3B SRZHU $SSOLFDWLRQ UHVHW VXSSO\ VXSHUYLVRU ([W UHVHW FRQWUROOHU DFWLYH VLJQDO RSWLRQDO ZKHQ 9&$3B 0LQ 9 9'' 3$ 9'' 1567 %<3$66B5(* 9 9&$3B 9&$3B DL 9 The following conditions must be respected: Note: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains.
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Functional overview STM32F413xG/H Figure 9. Startup in regulator OFF: slow VDD slope power-down reset risen after VCAP_1/VCAP_2 stabilization 9'' 3'5 9 9 0LQ 9 9&$3B 9&$3B WLPH 1567 3$ WLPH 06Y 9 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 10. Startup in regulator OFF mode: fast VDD slope power-down reset risen before VCAP_1/VCAP_2 stabilization 9'' 3'5 9 9&$3B 9&$3B 9 0LQ 9 1567 WLPH 3$ DVVHUWHG H[WHUQDOO\ WLPH 1.
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STM32F413xG/H 3.18.3 Functional overview Regulator ON/OFF and internal reset ON/OFF availability Table 4.
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Functional overview STM32F413xG/H Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. The RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 3.
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STM32F413xG/H 3.22 Functional overview Timers and watchdogs The devices embed two advanced-control timer, ten general-purpose timers, two basic timers, one low-power timer, two watchdog timers and a SysTick timer. All timer counters can be frozen in debug mode. Table 5 compares the features of the advanced-control and general-purpose timers. Table 5. Timer feature comparison Timer type Advance d-control Max. Max.
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Functional overview STM32F413xG/H Table 5. Timer feature comparison (continued) Timer type Max. Max. DMA Capture/ Complemen- interface timer request compare tary output clock clock generation channels (MHz) (MHz) Timer Counter Counter Prescaler resolution type factor Basic timers TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 50 100 Lowpower timer LPTIM1 16-bit Up Between 1 and 128 No 2 No 50 100 3.22.
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STM32F413xG/H Functional overview independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 15 input capture/output compare/PWMs TIM2. TIM3, TIM4 and TIM5 general-purpose timers can operate together or in conjunction with the other general-purpose timers and TIM1 advanced-control timer via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM output. TIM2.
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Functional overview 3.22.6 STM32F413xG/H Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.22.7 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 3.
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STM32F413xG/H Functional overview USART1, USART2, USART3 and USART6 provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. Table 7. USART feature comparison Max. baud Max. baud USART Standard Modem SPI Smartcard rate in Mbit/s rate in Mbit/s APB LIN irDA name features (RTS/CTS) master (ISO 7816) (oversampling (oversampling mapping by 16) by 8) USART1 X X X X X X 6.25 12.
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Functional overview 3.25 STM32F413xG/H Serial peripheral interface (SPI) The devices feature five SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4 and SPI5 can communicate at up to 50 Mbit/s, SPI2 and SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller.
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STM32F413xG/H Functional overview Different sources can also be selected for the SAI. The different possible sources are the main PLL, the PLLI2S, HSE or HSI clocks or an external clock provided through a pin (external PLL or CODEC output). The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz.
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Functional overview STM32F413xG/H The strong benefits of such mechanism coupled with DFSDM are: • Possibility to place the digital microphones close to each other • No need for external delay lines • The delay tuning is done in hardware, preventing the use of MIPs crunching algorithms • Possibility to change the delay tuning on the fly • The low power consumption and CPU time released due to the DFSDM hardware PDM to PCM conversion The impacted audio application are beam forming and sound source
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STM32F413xG/H Functional overview The main USB OTG FS features are: 3.
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Functional overview STM32F413xG/H • 8-bit or 12-bit output mode • Left or right data alignment in 12-bit mode • Synchronized update capability • Noise-wave generation • Triangular-wave generation • Dual DAC channel independent or simultaneous conversions • DMA capability for each channel • External triggers for conversion • Input voltage reference (VREF+) Eight DAC trigger inputs are used in the device.
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STM32F413xG/H Pinouts and pin description 4 Pinouts and pin description 4.1 WLCSP81 pinout description Figure 11.
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Pinouts and pin description 4.2 STM32F413xG/H UFQFPN48 pinout description 966 3& 26& B,1 3$ 3& 26& B287 3% 3% 9'' 3% 3% 3% 3$ 3& 3$ 3% %227 966 9%$7 3% 9'' Figure 12.
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STM32F413xG/H 4.
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Pinouts and pin description 4.4 STM32F413xG/H LQFP100 pinout description 6$$ 633 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 14.
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STM32F413xG/H 4.5 Pinouts and pin description LQFP144 pinout description 9'' 3'5B21 3( 3( 3% 3% %227 3% 3% 3% 3% 3% 3* 9'' 966 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ Figure 15.
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Pinouts and pin description 4.6 STM32F413xG/H UFBGA100 pinout description Figure 16. STM32F413xG/H UFBGA100 pinout $ 3( 3( 3% % 3( 3( & 3& 3' 3% 3% 3$ 3$ 3$ 3$ 3' 3' 3' 3' 3& 3& 3$ 3' 3' 3& 9&$3 B 3$ 966 3$ 3$ 3& %<3$66 B5(* 3& 3& 3& 966 966 966 3+ 26&B 287 9'' 9'' 9'' + 3& 1567 3'5 B21 3' 3' 3' - 966$ 3& 3& 3' 3' 3' .
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STM32F413xG/H 4.7 Pinouts and pin description UFBGA144 pinout description Figure 17.
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Pinouts and pin description STM32F413xG/H Table 9. Legend/abbreviations used in the pinout table (continued) Name Abbreviation Definition Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Table 10.
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STM32F413xG/H Pinouts and pin description Table 10.
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Pinouts and pin description STM32F413xG/H Table 10.
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STM32F413xG/H Pinouts and pin description Table 10.
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Pinouts and pin description STM32F413xG/H Table 10.
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STM32F413xG/H Pinouts and pin description Table 10.
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Pinouts and pin description STM32F413xG/H Table 10.
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STM32F413xG/H Pinouts and pin description Table 10.
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Pinouts and pin description STM32F413xG/H Table 10.
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STM32F413xG/H Pinouts and pin description Table 10.
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Pinouts and pin description STM32F413xG/H Table 10.
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STM32F413xG/H Pinouts and pin description Table 10.
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Pinouts and pin description STM32F413xG/H Table 10.
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STM32F413xG/H Pinouts and pin description Table 10.
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Pinouts and pin description STM32F413xG/H Table 10.
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STM32F413xG/H Pinouts and pin description Table 11.
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Pinouts and pin description STM32F413xG/H Table 11. FSMC pin definition (continued) FSMC Pins 66/208 Downloaded from Arrow.com.
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Memory mapping 5 STM32F413xG/H Memory mapping The memory map is shown in Figure 18. Figure 18. Memory map 5HVHUYHG &RUWH[ą 0 LQWHUQDO SHULSKHUDOV 5HVHUYHG [( [)))) )))) [( [( ) )))) [$ ± '))) ))) $ ))) $+% [ [ ))) )))) $+% [)))) )))) 0E\WH EORFN 5HVHUYHG [ [ [ ))) )))) [ )) LQWHUQDO SHULSKHUDOV [( ['))) )))) 0E\WH EORFN 1RW XVHG [& [%))) )))) $+% 5HVHUYHG [$ [$
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STM32F413xG/H Memory mapping Table 13.
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Memory mapping STM32F413xG/H Table 13. STM32F413xG/H register boundary addresses (continued) Bus APB2 76/208 Downloaded from Arrow.com.
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STM32F413xG/H Memory mapping Table 13.
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Electrical characteristics STM32F413xG/H 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM32F413xG/H 6.1.6 Electrical characteristics Power supply scheme Figure 21. Power supply scheme 9%$7 9%$7 WR 9 *3,2V î ) 9''B86% 9&$3B 9&$3B 9'' 966 î Q) î ) ,2 /RJLF .HUQHO ORJLF &38 GLJLWDO 5$0 9ROWDJH UHJXODWRU %<3$66B5(* 9''86% Q) ) 3'5B21 9'' )ODVK PHPRU\ 27* )6 3+< 5HVHW FRQWUROOHU 9''$ 95() Q) ) ,1 /HYHO VKLIWHU 287 9'' %DFNXS FLUFXLWU\ 26& .
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Electrical characteristics 6.1.7 STM32F413xG/H Current consumption measurement Figure 22. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ DL 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics, Table 15: Current characteristics, and Table 16: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied.
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STM32F413xG/H Electrical characteristics Table 15. Current characteristics Symbol Ratings Max.
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Electrical characteristics STM32F413xG/H 6.3 Operating conditions 6.3.1 General operating conditions Table 17.
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STM32F413xG/H Electrical characteristics Table 17. General operating conditions (continued) Symbol Parameter Input voltage on RST, FT and TC pins(7) VIN Typ Max 2 V ≤ VDD ≤ 3.6 V –0.3 - 5.5 VDD ≤ 2 V –0.3 - 5.2 - - 0.3 - VDDA + 0.
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Electrical characteristics STM32F413xG/H 8. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. 9. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax. Table 18. Features depending on the operating power supply range Operating power supply range ADC operation VDD =1.7 to 2.1 V(4) Conversion time up to 1.2 Msps VDD = 2.1 to 2.4 V Conversion time up to 1.2 Msps VDD = 2.4 to 2.7 V Conversion time up to 2.4 Msps VDD = 2.
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STM32F413xG/H 6.3.2 Electrical characteristics VCAP_1/VCAP_2 external capacitors Stabilization for the main regulator is achieved by connecting the external capacitor CEXT to the VCAP_1 and VCAP_2 pins. For packages supporting only 1 VCAP pin, the 2 CEXT capacitors are replaced by a single capacitor. CEXT is specified in Table 19. Figure 23. External capacitor CEXT & (65 5 /HDN 06 9 1. Legend: ESR is the equivalent series resistance. Table 19.
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Electrical characteristics 6.3.4 STM32F413xG/H Operating conditions at power-up / power-down (regulator OFF) Subject to general operating conditions for TA. Table 21. Operating conditions at power-up / power-down (regulator OFF)(1) Symbol tVDD tVCAP Parameter Conditions Min Max VDD rise time rate Power-up 20 ∞ VDD fall time rate Power-down 20 ∞ VCAP_1 and VCAP_2 rise time rate Power-up 20 ∞ VCAP_1 and VCAP_2 fall time rate Power-down 20 ∞ Unit µs/V 1.
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STM32F413xG/H Electrical characteristics Table 22. Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit - - 40 - mV Falling edge 2.13 2.19 2.24 Rising edge 2.23 2.29 2.33 Brownout level 2 threshold Falling edge 2.44 2.50 2.56 Rising edge 2.53 2.59 2.63 Brownout level 3 threshold Falling edge 2.75 2.83 2.88 Rising edge 2.85 2.92 2.
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Electrical characteristics STM32F413xG/H Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in input mode with a static value at VDD or VSS (no load). • All peripherals are disabled except if it is explicitly mentioned. • The Flash memory access time is adjusted to both fHCLK frequency and VDD ranges (refer to Table 18: Features depending on the operating power supply range).
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STM32F413xG/H Electrical characteristics 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the analog part. Table 24. Typical and maximum current consumption, code with data processing (ART accelerator disabled) running from SRAM - VDD = 3.
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Electrical characteristics STM32F413xG/H Table 25. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.
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STM32F413xG/H Electrical characteristics Table 26. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.
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Electrical characteristics STM32F413xG/H Table 27. Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 3.
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STM32F413xG/H Electrical characteristics Table 28. Typical and maximum current consumption in run mode, code with data processing (ART accelerator disabled) running from Flash memory - VDD = 1.
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Electrical characteristics STM32F413xG/H Table 29. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled with prefetch) running from Flash memory - VDD = 3.
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STM32F413xG/H Electrical characteristics Table 30. Typical and maximum current consumption in run mode, code with data processing (ART accelerator enabled with prefetch) running from Flash memory - VDD = 1.
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Electrical characteristics STM32F413xG/H Table 31. Typical and maximum current consumption in Sleep mode - VDD = 3.
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STM32F413xG/H Electrical characteristics Table 32. Typical and maximum current consumption in Sleep mode - VDD = 1.
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Electrical characteristics STM32F413xG/H 2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register). Table 33. Typical and maximum current consumptions in Stop mode - VDD = 1.
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STM32F413xG/H Electrical characteristics Table 36. Typical and maximum current consumption in Standby mode - VDD= 3.6 V Typ(1) Symbol Parameter Conditions TA = TA = TA = TA = TA = Unit 25 °C 25 °C 85 °C 105 °C 125 °C Low-speed oscillator (LSE in low drive mode) and RTC ON IDD_STBY Max(2) Supply current in Low-speed oscillator (LSE in high drive Standby mode mode) and RTC ON RTC and LSE OFF 3.7 5.2 20.6 40.5 82.7 4.5 6.0 21.4 41.3 83.5 2.5 4.0 19.4 39.3 81.5(3) µA 1.
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Electrical characteristics STM32F413xG/H Figure 24. Typical VBAT current consumption (LSE and RTC ON/LSE oscillator “low power” mode selection) 06Y 9 Figure 25. Typical VBAT current consumption (LSE and RTC ON/LSE oscillator “high drive” mode selection) 06Y 9 100/208 Downloaded from Arrow.com.
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STM32F413xG/H Electrical characteristics I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 59: I/O static characteristics.
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Electrical characteristics STM32F413xG/H Table 38. Switching output I/O current consumption Symbol Parameter Conditions(1) VDD = 3.3 V C = CINT VDD = 3.3 V CEXT = 0 pF C = CINT + CEXT + CS IDDIO I/O switching current VDD = 3.3 V CEXT =10 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT + CS VDD = 3.3 V CEXT = 33 pF C = CINT + CEXT + CS I/O toggling Typ frequency (fSW) 2 MHz 0.05 8 MHz 0.15 25 MHz 0.45 50 MHz 0.85 60 MHz 1.00 84 MHz 1.40 90 MHz 1.67 2 MHz 0.
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STM32F413xG/H Electrical characteristics On-chip peripheral current consumption The MCU is placed under the following conditions: • At startup, all I/O pins are in analog input configuration. • All peripherals are disabled unless otherwise mentioned. • The ART accelerator is ON. • Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V. • HCLK is the system clock at 100 MHz. fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK.
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Electrical characteristics STM32F413xG/H Table 39. Peripheral current consumption (continued) IDD (Typ) Peripheral APB1 104/208 Downloaded from Arrow.com. Unit Scale 1 Scale 2 Scale 3 AHB-APB1 bridge 0.90 0.88 0.81 TIM2 13.08 12.48 11.16 TIM3 9.98 9.50 8.50 TIM4 9.88 9.43 8.44 TIM5 13.14 12.52 11.19 TIM6 1.94 1.86 1.66 TIM7 1.86 1.79 1.56 TIM12 5.56 5.29 4.72 TIM13 3.44 3.29 2.94 TIM14 3.66 3.48 3.09 LPTIM1 7.34 7.00 6.25 WWDG 0.64 0.62 0.
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STM32F413xG/H Electrical characteristics Table 39. Peripheral current consumption (continued) IDD (Typ) Peripheral Unit Scale 1 Scale 2 Scale 3 AHB-APB2 bridge 0.10 0.11 0.09 TIM1 6.78 6.46 5.80 TIM8 6.94 6.62 5.94 USART1 3.14 3.00 2.69 USART6 3.12 2.98 2.67 UART9 2.89 1.98 1.75 UART10 2.91 2.00 1.77 ADC1 3.45 3.29 2.95 SDIO 3.54 3.37 3.03 SPI1 1.52 1.46 1.31 SPI4 1.50 1.43 1.28 SYSCFG 0.58 0.55 0.50 EXT1 0.91 0.86 0.78 TIM9 2.95 2.81 2.
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Electrical characteristics STM32F413xG/H Figure 26. Low-power mode wakeup :DNHXS IURP 6WRS PRGH PDLQ UHJXODWRU 2SWLRQ E\WHV DUH QRW UHORDGHG &38 UHVWDUW 5HJXODWRU +6, UHVWDUW )ODVK VWRS H[LW UDPS XS :DNHXS IURP 6WRS PRGH PDLQ UHJXODWRU IODVK LQ 'HHS SRZHU GRZQ PRGH 2SWLRQ E\WHV DUH QRW UHORDGHG &38 UHVWDUW 5HJXODWRU +6, UHVWDUW )ODVK 'HHS 3G UHFRYHU\ UDPS XS :DNHXS IURP 6WRS UHJXODWRU LQ ORZ SRZHU PRGH 2SWLRQ E\WHV DUH QRW UHORDGHG 5HJXODWRU UDPS XS &38 UHVWDUW +6, UHVWDUW )ODVK VWRS H[L
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STM32F413xG/H Electrical characteristics Table 40. Low-power mode wakeup timings(1) Symbol Parameter tWUSLEEP Wakeup from Sleep mode tWUSLEEPFDSM tWUSTOP tWUSTOP Wakeup from STOP mode Code execution on Flash Wakeup from STOP mode code execution on RAM(3) tWUSTDBY Wakeup from Standby mode tWUFLASH Wakeup of Flash Conditions Min(1) Typ(1) Max(1) Unit - - 4 6 clk cycles Flash memory in Deep power down mode - - 50.0 Main regulator - 12.7 15.
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Electrical characteristics STM32F413xG/H summarized in Table 17. Table 41. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 - 50 MHz fHSE_ext External user clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.
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STM32F413xG/H Electrical characteristics Figure 27. High-speed external clock source AC timing diagram 6(3%( 6(3%, TR (3% TF (3% T7 (3% /3#?). ), T7 (3% T 4(3% %XTERNAL CLOCK SOURCE F(3%?EXT 34- & AI Figure 28.
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Electrical characteristics STM32F413xG/H Table 43. HSE 4-26 MHz oscillator characteristics(1) Symbol fOSC_IN RF IDD Parameter Conditions Min Typ Max Unit Oscillator frequency 4 - 26 MHz Feedback resistor - 200 - kΩ VDD=3.3 V, ESR= 30 Ω, CL=5 pF @25 MHz - 450 - VDD=3.
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STM32F413xG/H Electrical characteristics possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). The LSE high-power mode allows to cover a wider range of possible crystals but with a cost of higher power consumption. Table 44. LSE oscillator characteristics (fLSE = 32.
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Electrical characteristics 6.3.9 STM32F413xG/H Internal clock source characteristics The parameters given in Table 45 and Table 46 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 17. High-speed internal (HSI) RC oscillator Table 45. HSI oscillator characteristics (1) L Symbol fHSI Parameter Conditions Min Typ Max Unit Frequency - - 16 - MHz HSI user trimming step(2) - - - 1 % (3) –8 - 6.75 % °C(3) –8 - 4.
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STM32F413xG/H Electrical characteristics Low-speed internal (LSI) RC oscillator Table 46. LSI oscillator characteristics (1) Symbol Parameter fLSI(2) tsu(LSI) Min Typ Max Unit 16.1 32.0 47.0 kHz LSI oscillator startup time - 15.0 40.0 µs LSI oscillator power consumption - 0.4 0.6 µA Frequency (3) IDD(LSI)(3) 1. VDD = 3 V, TA = –40 to 125 °C unless otherwise specified. 2. Guaranteed by characterization results. 3. Guaranteed by design. Figure 32.
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Electrical characteristics 6.3.10 STM32F413xG/H PLL characteristics The parameters given in Table 47 and Table 48 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 17. Table 47. Main PLL characteristics Symbol Parameter Conditions Min Typ Max fPLL_IN PLL input clock(1) - 0.95(2) 1 2.
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STM32F413xG/H Electrical characteristics Table 48. PLLI2S (audio PLL) characteristics Symbol Parameter Conditions Min Typ Max fPLL_IN PLL input clock(1) - 0.95(2) 1 2.
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Electrical characteristics 6.3.11 STM32F413xG/H PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 55: EMI characteristics for LQFP144). It is available only on the main PLL. Table 49. SSCG parameter constraints Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 kHz md Peak modulation depth 0.
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STM32F413xG/H Electrical characteristics Figure 33 and Figure 34 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 33. PLL output clock waveforms in center spread mode &REQUENCY 0,,?/54 MD & MD TMODE 4IME XTMODE AI Figure 34. PLL output clock waveforms in down spread mode )UHTXHQF\ 3//B287 ) [PG WPRGH 7LPH [WPRGH DL E 6.3.
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Electrical characteristics STM32F413xG/H Table 51.
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STM32F413xG/H Electrical characteristics Table 52. Flash memory programming with VPP voltage Symbol Parameter Conditions tprog Double word programming tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Min(1) Typ Max(1) Unit - 16 100(2) µs - 230 - - 490 - - 875 - - 9.8 - s TA = 0 to +40 °C VDD = 3.3 V VPP = 8.5 V Mass erase time ms Vprog Programming voltage - 2.7 - 3.
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Electrical characteristics 6.3.13 STM32F413xG/H EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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STM32F413xG/H Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
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Electrical characteristics STM32F413xG/H Table 56. ESD absolute maximum ratings Symbol VESD(HBM) VESD(CDM) Class Maximum value(1) TA = +25 °C conforming to JESD22-A114 2 2000 TA = +25 °C conforming to ANSI/ESD STM5.3.1, UFBGA144, UFBGA100, LQFP144, LQFP100, WLCSP81, LQFP64 3 250 4 500 Ratings Electrostatic discharge voltage (human body model) Conditions Electrostatic discharge voltage (charge device model) T = +25 °C conforming to ANSI/ESD STM5.3.1, A UFQFPN48 Unit V 1.
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STM32F413xG/H Electrical characteristics Table 58. I/O current injection susceptibility(1) Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on BOOT0, PDR_ON, BYPASS_REG -0 0 Injected current on NRST -0 NA Injected current on PE6, PC13, PC14, PC15, PF0, PF1, PF2, PC0, PC1, PC2, PC3 -0 NA Injected current on any other FT and FTf pins -5 NA Injected current on any other pins -5 +5 Unit mA 1. NA = not applicable.
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Electrical characteristics STM32F413xG/H Table 59.
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STM32F413xG/H Electrical characteristics Figure 35.
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Electrical characteristics STM32F413xG/H Table 60.
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STM32F413xG/H Electrical characteristics Table 61. I/O AC characteristics(1)(2) OSPEEDRy Symbol [1:0] bit value(1) Parameter fmax(IO)out Maximum frequency(3) 00 tf(IO)out/ tr(IO)out 01 Output high to low level fall time and output low to high level rise time fmax(IO)out Maximum frequency(3) 10 tf(IO)out/ tr(IO)out Fmax(IO)ou t 11 tf(IO)out/ tr(IO)out Fmax FM+ - Min Typ Max CL = 50 pF, VDD ≥ 2.70 V - - 4 CL = 50 pF, VDD≥ 1.7 V - - 2 CL = 10 pF, VDD ≥ 2.
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Electrical characteristics STM32F413xG/H 1. Guaranteed by characterization results. 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 3. The maximum frequency is defined in Figure 36. 4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used. Figure 36.
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STM32F413xG/H Electrical characteristics Figure 37. Recommended NRST pin protection 9'' ([WHUQDO UHVHW FLUFXLW 1567 538 ,QWHUQDO 5HVHW )LOWHU ) 670 ) DL F 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 62. Otherwise the reset is not taken into account by the device. 6.3.18 TIM timer characteristics The parameters given in Table 63 are guaranteed by design.
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Electrical characteristics 6.3.19 STM32F413xG/H Communications interfaces I2C interface characteristics The I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 64. Refer also to Section 6.3.
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STM32F413xG/H Electrical characteristics Figure 38. I2C bus AC waveforms and measurement circuit 9''B, & 53 9''B, & 53 670 )[[ 56 6'$ , & EXV 56 6&/ 67$57 5(3($7(' 67$57 67$57 WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ WVX 6'$ WZ 672 67$ 6723 WK 6'$ WZ 6&/+ 6&/ WU 6&/ WZ 6&// WI 6&/ WVX 672 06Y 9 1. RS = series protection resistor. 2. RP = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. Table 65. SCL frequency (fPCLK1= 50 MHz, VDD = VDD_I2C = 3.
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Electrical characteristics STM32F413xG/H FMPI2C characteristics The following table presents FMPI2C characteristics. Refer also to Section 6.3.16: I/O port characteristics for more details on the input/output function characteristics (SDA and SCL). Table 66. FMPI2C characteristics(1) Standard mode Fast mode Fast+ mode Parameter Unit Min Max Min Max Min Max 2 - 8 - 18 - fFMPI2CC FMPI2CCLK frequency tw(SCLL) SCL clock low time 4.7 - 1.3 - 0.5 - tw(SCLH) SCL clock high time 4.
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STM32F413xG/H Electrical characteristics Figure 39. FMPI2C timing diagram and measurement circuit 9''B, & 53 9''B, & 53 670 )[[ 56 6'$ , & EXV 56 6&/ 67$57 5(3($7(' 67$57 67$57 WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ WVX 6'$ WZ 6&/+ WZ 672 67$ 6723 WK 6'$ 6&/ WZ 6&// WU 6&/ WI 6&/ WVX 672 06Y 9 DocID029162 Rev 6 133/208 174 Downloaded from Arrow.com.
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Electrical characteristics STM32F413xG/H SPI interface characteristics Unless otherwise specified, the parameters given in Table 67 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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STM32F413xG/H Electrical characteristics Table 67. SPI dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit ta(SO) Data output access time Slave mode 7 - 21 ns tdis(SO) Data output disable time Slave mode 5 - 12 ns Slave mode (after enable edge), 2.7 V < VDD < 3.6 V - 7 12.5 Slave mode (after enable edge), 1.71 V < VDD < 3.6 V - 7 19 tv(MO) Master mode - 2 3 th(SO) Slave mode 1.71 V < VDD < 3.6 V 6 - - 1.
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Electrical characteristics STM32F413xG/H Figure 41. SPI timing diagram - slave mode and CPHA = 1 166 LQSXW 6&. LQSXW W68 166 &3+$ &32/ &3+$ &32/ WK 166 WF 6&. WZ 6&.+ WZ 6&./ 0,62 287387 06% 287 %,7 287 WU 6&. WI 6&. WGLV 62 /6% 287 WK 6, WVX 6, 026, ,1387 WK 62 WY 62 WD 62 06% ,1 %,7 ,1 /6% ,1 DL E Figure 42. SPI timing diagram - master mode +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&. 2XWSXW WF 6&.
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STM32F413xG/H Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 68 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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Electrical characteristics STM32F413xG/H Figure 43. I2S slave timing diagram (Philips protocol) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 44. I2S master timing diagram (Philips protocol) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 138/208 Downloaded from Arrow.com.
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STM32F413xG/H Electrical characteristics SAI characteristics Unless otherwise specified, the parameters given in Table 69 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C=30 pF • Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 6.3.
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Electrical characteristics STM32F413xG/H Figure 45. SAI master timing waveforms F3#+ 3!)?3#+?8 TH &3 3!)?&3?8 OUTPUT TV &3 TH 3$?-4 TV 3$?-4 3!)?3$?8 TRANSMIT 3LOT N 3LOT N TSU 3$?-2 TH 3$?-2 3!)?3$?8 RECEIVE 3LOT N -3 6 Figure 46. SAI slave timing waveforms F3#+ 3!)?3#+?8 TW #+(?8 3!)?&3?8 INPUT TW #+,?8 TH &3 TSU &3 TH 3$?34 TV 3$?34 3!)?3$?8 TRANSMIT 3LOT N TSU 3$?32 3!)?3$?8 RECEIVE 3LOT N TH 3$?32 3LOT N -3 6 140/208 Downloaded from Arrow.com.
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STM32F413xG/H Electrical characteristics QSPI interface characteristics Unless otherwise specified, the parameters given in the following tables for QSPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C=20pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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Electrical characteristics STM32F413xG/H Table 71. QSPI dynamic characteristics in DDR mode(1) (continued) Symbol tw(CKH) tw(CKL) Parameter Conditions QSPI clock high and low time - tsr(IN), tsf(IN) Data input setup time thr(IN), thf(IN) Data input hold time tvr(OUT), tvf(OUT) Data output valid time thr(OUT), thf(OUT) Data output hold time Min Typ Max Unit t(CK) / 2 - 1 - t(CK) / 2 t(CK) / 2 - t(CK) / 2 + 1 2.7 V < VDD < 3.6 V 0.5 - - 1.71 V < VDD < 3.6 V 0.5 - - 2.
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STM32F413xG/H Electrical characteristics 2. The USB OTG FS functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 3. Guaranteed by design. 4. RL is the load connected on the USB OTG FS drivers. Note: When VBUS sensing feature is enabled, PA9 should be left at their default state (floating input), not as alternate function.
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Electrical characteristics 6.3.20 STM32F413xG/H 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 75 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 17. Table 75. ADC characteristics Symbol Parameter VDDA Power supply VREF+ Positive reference voltage VREF- Negative reference voltage Conditions Typ Max (1) 1.7 - 3.6 1.7(1) - VDDA - 0 - 0.6 15 18 MHz VDDA = 2.
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STM32F413xG/H Electrical characteristics Table 75. ADC characteristics (continued) Symbol Parameter Sampling rate fS(2) (fADC = 30 MHz, and tS = 3 ADC cycles) Conditions Min Typ Max Unit 12-bit resolution Single ADC - - 2 Msps IVREF+(2) ADC VREF DC current consumption in conversion mode - - 300 500 µA IVDDA(2) ADC VDDA DC current consumption in conversion mode - - 1.6 1.8 mA 1. VDDA minimum value of 1.
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Electrical characteristics STM32F413xG/H Table 77. ADC accuracy at fADC = 30 MHz(1) Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V, VDDA −VREF < 1.2 V Typ Max(2) ±2 ±5 ±1.5 ±2.5 ±1.5 ±4 ±1 ±2 ±1.5 ±3 Unit LSB 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. 2.
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STM32F413xG/H Note: Electrical characteristics ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.
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Electrical characteristics STM32F413xG/H Figure 49. Typical connection diagram using the ADC 9'' 6DPSOH DQG KROG $'& FRQYHUWHU 97 9 5$,1 9$,1 5$'& $,1[ &SDUDVLWLF 97 9 ELW FRQYHUWHU ,/ $ &$'& 06 9 1. Refer to Table 75 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy.
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STM32F413xG/H Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 50 or Figure 51, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 50. Power supply and reference decoupling (VREF+ not connected to VDDA) 670 ) 95() ) Q) 9''$ ) Q) 966$ 95() DL E 1.
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Electrical characteristics STM32F413xG/H Figure 51. Power supply and reference decoupling (VREF+ connected to VDDA) 670 ) 95() 9''$ ) Q) 95() 966$ DL F 1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA. 6.3.21 Temperature sensor characteristics Table 81.
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STM32F413xG/H 6.3.22 Electrical characteristics VBAT monitoring characteristics Table 83. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit KΩ R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 4 - Error on Q –1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - µs (1) Er TS_vbat(2)(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.
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Electrical characteristics 6.3.24 STM32F413xG/H DAC electrical characteristics Table 86. DAC characteristics Symbol Parameter Conditions Min Typ Max Unit Comments VDDA Analog supply voltage - 1.7(1) - 3.6 V VREF+ Reference supply voltage - 1.7(1) - 3.
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STM32F413xG/H Electrical characteristics Table 86.
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Electrical characteristics STM32F413xG/H 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.17.2: Internal reset OFF). 2. Guaranteed by design. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization results. Figure 52.
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STM32F413xG/H 6.3.25 Electrical characteristics DFSDM characteristics Unless otherwise specified, the parameters given in Table 87 for DFSDM are derived from tests performed under the ambient temperature, fAPB2 frequency and VDD supply voltage conditions summarized in Table 17: General operating conditions. • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 * VDD Refer to Section 6.3.
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Electrical characteristics STM32F413xG/H Table 87. DFSDM characteristics(1) (continued) Symbol twh(CKIN) twl(CKIN) tsu th Parameter Conditions Min Typ Max Input clock high and low time SPI mode (SITP[1:0] = 01), External clock mode (SPICKSEL[1:0] = 0) 1.71 < VDD < 3.6 V tCKIN / 2 - 0.5 tCKIN / 2 - Data input setup time SPI mode (SITP[1:0]=01), External clock mode (SPICKSEL[1:0] = 0) 1.71 < VDD < 3.6 V 3.
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STM32F413xG/H Electrical characteristics ')6'0B &.,1\ ')6'0B'$7,1\ 63, WLPLQJ 63,&.6(/ Figure 16: DFSDM timing diagram WZO WZK WU WI 63,&.6(/ WVX WK 6,73 WVX WK 6,73 ')6'0B&.287 63,&.6(/ WZO WU WZK WI 63,&.6(/ ')6'0B'$7,1\ WVX ')6'0B'$7,1\ 0DQFKHVWHU WLPLQJ 63, WLPLQJ 63,&.6(/ 63,&.
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Electrical characteristics 6.3.26 STM32F413xG/H FSMC characteristics Unless otherwise specified, the parameters given in Table 88 to Table 95 for the FSMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitance load C = 30 pF • Measurement points are done at CMOS levels: 0.5.VDD Refer to Section 6.3.
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STM32F413xG/H Electrical characteristics Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms WZ 1( )60&B1( WY 12(B1( WZ 12( WK 1(B12( )60&B12( )60&B1:( WK $B12( TV !?.% )60&B$> @ $GGUHVV TV ",?.% WK %/B12( )60&B1%/> @ WK 'DWDB1( WVX 'DWDB12( WK 'DWDB12( WVX 'DWDB1( 'DWD )60&B'> @ WY 1$'9B1( WZ 1$'9 )60&B1$'9 )60&B1:$,7 WK 1(B1:$,7 WVX 1:$,7B1( 06Y 9 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
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Electrical characteristics STM32F413xG/H Table 88. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Min Max 2 * tHCLK - 1 2 * tHCLK + 1 0 0.5 2 * tHCLK - 1 2 * tHCLK + 1 FSMC_NOE high to FSMC_NE high hold time 0 - FSMC_NEx low to FSMC_A valid - 0.5 th(A_NOE) Address hold time after FSMC_NOE high 0 - tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.
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STM32F413xG/H Electrical characteristics Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms WZ 1( )60&B1([ )60&B12( WY 1:(B1( WK 1(B1:( WZ 1:( )60&B1:( WK $B1:( TV !?.% )60&B$> @ $GGUHVV TV ",?.% )60&B1%/> @ WK %/B1:( 1%/ WY 'DWDB1( WK 'DWDB1:( 'DWD )60&B'> @ WY 1$'9B1( )60&B1$'9 WZ 1$'9 )60&B1:$,7 WK 1(B1:$,7 WVX 1:$,7B1( 06Y 9 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 90.
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Electrical characteristics STM32F413xG/H 1. CL = 30 pF. 2. Based on characterization. Table 91. Asynchronous non-multiplexed SRAM/PSRAM/NOR write NWAIT timings(1)(2) Symbol Parameter FSMC_NE low time tw(NE) tw(NWE) FSMC_NWE low time Min Max Unit 8 * tHCLK - 1 8 * tHCLK + 1 6 * tHCLK - 1.5 6 * tHCLK + 0.5 tsu(NWAIT_NE) FSMC_NWAIT valid before FSMC_NEx high 6 * tHCLK - 1 - th(NE_NWAIT) FSMC_NEx hold time after FSMC_NWAIT invalid 4 * tHCLK + 2 - ns 1. CL = 30 pF. 2.
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STM32F413xG/H Electrical characteristics Table 92. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol Min Max 3 * tHCLK - 1 3 * tHCLK + 1 FSMC_NEx low to FSMC_NOE low 2 * tHCLK 2 * tHCLK + 0.5 FSMC_NOE low time tHCLK - 1 tHCLK + 1 FSMC_NOE high to FSMC_NE high hold time 0 - FSMC_NEx low to FSMC_A valid - 0.5 FSMC_NEx low to FSMC_NADV low 0 0.5 FSMC_NADV low time tHCLK - 0.5 tHCLK + 1 th(AD_NADV) FSMC_AD(address) valid hold time after FSMC_NADV high) tHCLK + 0.
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Electrical characteristics STM32F413xG/H Figure 56. Asynchronous multiplexed PSRAM/NOR write waveforms WZ 1( )60&B1([ )60&B12( WK 1(B1:( WZ 1:( WY 1:(B1( )60&B1:( WK $B1:( TV !?.% )60&B$> @ $GGUHVV WK %/B1:( TV ",?.% )60&B1%/> @ 1%/ WY $B1( )60&B$'> @ WY 'DWDB1$'9 $GGUHVV W Y 1$'9B1( WK 'DWDB1:( 'DWD TH !$?.!$6 WZ 1$'9 )60&B1$'9 )60&B1:$,7 WK 1(B1:$,7 WVX 1:$,7B1( 164/208 Downloaded from Arrow.com.
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STM32F413xG/H Electrical characteristics Table 94. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Parameter tw(NE) FSMC_NE low time FSMC_NEx low to FSMC_NWE low tv(NWE_NE) tw(NWE) FSMC_NWE low time th(NE_NWE) Min Max 4 * THCLK - 1 4 * THCLK + 1 THCLK - 1 THCLK + 0.5 2 * THCLK - 0.5 2 * THCLK - 0.5 FSMC_NWE high to FSMC_NE high hold time THCLK - 0.5 - FSMC_NEx low to FSMC_A valid - 0 FSMC_NEx low to FSMC_NADV low 0 0.
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Electrical characteristics STM32F413xG/H In all timing tables, the THCLK is the HCLK clock period (with maximum FSMC_CLK = 90 MHz). Figure 57. Synchronous multiplexed NOR/PSRAM read timings WZ &/. %867851 WZ &/. )60&B&/. 'DWD ODWHQF\ WG &/./ 1([/ )60&B1([ WG &/./ 1$'9/ WG &/.+ 1([+ WG &/./ 1$'9+ )60&B1$'9 WG &/.+ $,9 WG &/./ $9 )60&B$> @ WG &/./ 12(/ WG &/.+ 12(+ )60&B12( WG &/./ $',9 WG &/./ $'9 )60&B$'> @ WK &/.+ $'9 WVX $'9 &/.+ WVX $'9 &/.+ $'> @ ' WVX 1:$,79 &/.
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STM32F413xG/H Electrical characteristics Table 96. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol tw(CLK) Parameter FSMC_CLK period Min Max 2 * THCLK - 0.5 - - 2 THCLK + 0.5 - td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) td(CLKH_NExH) FSMC_CLK high to FSMC_NEx high (x= 0…2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0 - td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 2.
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Electrical characteristics STM32F413xG/H Figure 58. Synchronous multiplexed PSRAM write timings WZ &/. %867851 WZ &/. )60&B&/. 'DWD ODWHQF\ WG &/./ 1([/ WG &/.+ 1([+ )60&B1([ WG &/./ 1$'9/ WG &/./ 1$'9+ )60&B1$'9 WG &/.+ $,9 WG &/./ $9 )60&B$> @ WG &/.+ 1:(+ WG &/./ 1:(/ )60&B1:( WG &/./ $',9 WG &/./ $'9 )60&B$'> @ WG &/./ 'DWD WG &/./ 'DWD $'> @ ' ' )60&B1:$,7 :$,7&)* E :$,732/ E WVX 1:$,79 &/.+ WK &/.+ 1:$,79 WG &/.
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STM32F413xG/H Electrical characteristics Table 97. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Min Max tw(CLK) FSMC_CLK period, VDD range= 2.7 to 3.6 V 2 * THCLK - 0.5 - td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x= 0...2) - 2 td(CLKH-NExH) FSMC_CLK high to FSMC_NEx high (x= 0…2) THCLK + 0.5 - td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0 - td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 2.
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Electrical characteristics STM32F413xG/H Figure 59. Synchronous non-multiplexed NOR/PSRAM read timings WZ &/. WZ &/. )60&B&/. WG &/./ 1([/ WG &/.+ 1([+ 'DWD ODWHQF\ )60&B1([ WG &/./ 1$'9/ WG &/./ 1$'9+ )60&B1$'9 WG &/./ $9 WG &/.+ $,9 )60&B$> @ WG &/.+ 12(+ WG &/./ 12(/ )60&B12( WVX '9 &/.+ WK &/.+ '9 WVX '9 &/.+ WK &/.+ '9 ' )60&B'> @ WVX 1:$,79 &/.+ )60&B1:$,7 :$,7&)* E :$,732/ E ' WK &/.+ 1:$,79 WVX 1:$,79 &/.+ )60&B1:$,7 :$,7&)* E :$,732/ E WVX 1:$,79 &/.
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STM32F413xG/H Electrical characteristics Figure 60. Synchronous non-multiplexed PSRAM write timings WZ &/. WZ &/. )60&B&/. WG &/./ 1([/ WG &/.+ 1([+ 'DWD ODWHQF\ )60&B1([ WG &/./ 1$'9/ WG &/./ 1$'9+ )60&B1$'9 WG &/./ $9 WG &/.+ $,9 )60&B$> @ WG &/./ 1:(/ WG &/.+ 1:(+ )60&B1:( WG &/./ 'DWD ' )60&B'> @ )60&B1:$,7 :$,7&)* E :$,732/ E WG &/./ 'DWD WVX 1:$,79 &/.+ ' WG &/.+ 1%/+ WK &/.+ 1:$,79 )60&B1%/ 06Y 9 Table 99.
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Electrical characteristics 6.3.27 STM32F413xG/H SD/SDIO MMC/eMMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 100 for the SDIO are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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STM32F413xG/H Electrical characteristics Table 100. SD / MMC characteristics(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 50 MHz - SDIO_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp =50MHz 9.5 10.5 - tW(CKH) Clock high time fpp =50MHz 8.5 9.
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Electrical characteristics 6.3.28 STM32F413xG/H RTC characteristics Table 102. RTC characteristics 174/208 Downloaded from Arrow.com.
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STM32F413xG/H 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 WLCSP81 package information Figure 63. WLCSP81 - 81-ball, 4.039 x 3.951 mm, 0.
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Package information STM32F413xG/H Table 103. WLCSP81 - 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - - 0.025 - - 0.0010 - Ø b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 4.004 4.039 4.074 0.1576 0.1590 0.1604 E 3.916 3.951 3.986 0.1542 0.1556 0.1569 e - 0.400 - - 0.
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STM32F413xG/H Package information Figure 64. WLCSP81- 81-ball, 4.039 x 3.951 mm, 0.4 mm pitch wafer level chip scale package recommended footprint 'SDG 'VP :/&63 B$ %B)3B9 Table 104. WLCSP81 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 mm Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm DocID029162 Rev 6 177/208 205 Downloaded from Arrow.com.
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Package information STM32F413xG/H Device marking for WLCSP81 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 65. WLCSP81 marking example (package top view) 3LQ LGHQWLILHU 3URGXFW LGHQWLILFDWLRQ ) * 'DWH FRGH < :: $ $GGLWLRQDO LQIRUPDWLRQ 06Y 9 1.
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STM32F413xG/H 7.2 Package information UFQFPN48 package information Figure 66. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline 3LQ LGHQWLILHU ODVHU PDUNLQJ DUHD ' $ ( ( 7 GGG $ 6HDWLQJ SODQH E H 'HWDLO < ' ([SRVHG SDG DUHD < ' / & [ SLQ FRUQHU ( 5 W\S 'HWDLO = = $ % B0(B9 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3.
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Package information STM32F413xG/H Table 105. UFQFPN48 - 48-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.
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STM32F413xG/H Package information Device marking for UFQFPN48 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 68. UFQFPN48 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670 ) &+8 'DWH FRGH < :: 3LQ LQGHQWLILHU 5HYLVLRQ FRGH $ 06Y 9 1.
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Package information 7.3 STM32F413xG/H LQFP64 package information Figure 69. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( ( E H :B0(B9 1. Drawing is not to scale. 182/208 Downloaded from Arrow.com.
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STM32F413xG/H Package information Table 106. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.
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Package information STM32F413xG/H Figure 70. LQFP64 recommended footprint AI C 1. Dimensions are in millimeters. 184/208 Downloaded from Arrow.com.
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STM32F413xG/H Package information Device marking for LQFP64 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 71. LQFP64 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ $ 670 ) 5+7 'DWH FRGH < :: 3LQ LQGHQWLILHU 06Y 9 1.
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Package information 7.4 STM32F413xG/H LQFP100 package information Figure 72. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ ! + CCC # , $ , $ 0). )$%.4)&)#!4)/. % % % B E ,?-%?6 1. Drawing is not to scale. Dimensions are in millimeters. Table 107.
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STM32F413xG/H Package information Table 107. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0° ccc - - 0.080 - - 0.0031 1.
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Package information STM32F413xG/H Device marking for LQFP100 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 74. LQFP100 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670 ) 9+7 $ 5HYLVLRQ FRGH 'DWH FRGH < :: 3LQ LQGHQWLILHU 06Y 9 1.
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STM32F413xG/H 7.5 Package information LQFP144 package information Figure 75. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM CCC # $ , $ + ! '!5'% 0,!.% , $ % % % B 0). )$%.4)&)#!4)/. E !?-%?6 1. Drawing is not to scale. DocID029162 Rev 6 189/208 205 Downloaded from Arrow.com.
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Package information STM32F413xG/H Table 108. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.
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STM32F413xG/H Package information Figure 76. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint DL H 1. Dimensions are expressed in millimeters. DocID029162 Rev 6 191/208 205 Downloaded from Arrow.com.
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Package information STM32F413xG/H Device marking for LQFP144 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 77. LQFP144 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ $ 670 ) =+7 'DWH FRGH < :: 3LQ LGHQWLILHU 06Y 9 1.
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STM32F413xG/H 7.6 Package information UFBGA100 package information Figure 78. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ $ $ ( $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD = H ; ( $ = ' ' H < 0 %27720 9,(: E EDOOV HHH 0 = < ; III 0 = 723 9,(: $ & B0(B9 1. Drawing is not to scale. Table 109. UFBGA100 - 100-ball, 7 x 7 mm, 0.
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Package information STM32F413xG/H Table 109. UFBGA100 - 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 79. UFBGA100 - 100-pin, 7 x 7 mm, 0.
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STM32F413xG/H Package information Device marking for UFBGA100 The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 80. UFBGA100 marking example (package top view) WƌŽĚƵĐƚ ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ;ϭͿ 670 ) 9++ ĂƚĞ ĐŽĚĞ с ǇĞĂƌ н ǁĞĞŬ < :: Ăůů ϭ ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ĚĚŝƚŝŽŶĂů ŝŶĨŽƌŵĂƚŝŽŶ $ 06Y 9 1.
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Package information 7.7 STM32F413xG/H UFBGA144 package information Figure 81. UFBGA144 - 144-pin, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package outline & 6HDWLQJ SODQH GGG = $ $ $ $ $ ( H $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) $ ( $ ) ' ' H % 0 %27720 9,(: E EDOOV HHH 0 & $ % III 0 & 723 9,(: $
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STM32F413xG/H Package information Table 111. UFBGA144 - 144-ball, 10 x 10 mm, 0.80 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. F 0.550 0.600 0.650 0.0177 0.0197 0.0217 ddd - - 0.080 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 82. UFBGA144 - 144-pin, 10 x 10 mm, 0.
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Package information STM32F413xG/H Device marking for UFBGA144 The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 83. UFBGA144 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670 ) =+- $GGLWLRQDO LQIRUPDWLRQ $ 'DWH FRGH < :: %DOO $ LQGHQWLILHU 06Y 9 1.
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STM32F413xG/H 7.8 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 17: General operating conditions. The maximum chip-junction temperature, TJ max.
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Ordering information 8 STM32F413xG/H Ordering information Table 114.
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STM32F413xG/H Recommendations when using the internal reset OFF Appendix A Recommendations when using the internal reset OFF When the internal reset is OFF, the following integrated features are no longer supported: • The integrated power-on-reset (POR)/power-down reset (PDR) circuitry is disabled. • The brownout reset (BOR) circuitry must be disabled. By default BOR is OFF. • The embedded programmable voltage detector (PVD) is disabled.
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Application block diagrams Appendix B B.1 STM32F413xG/H Application block diagrams Sensor Hub application example Figure 84. Sensor Hub application example $FFHOHURPHWHU *\URVFRSH 0DJQHWRPHWHU 670 ) [[ 3% 3% 3$ SLQ SDFNDJH 6&/ , & 3UHVVXUH 3% 3% 3% 6'$ [ *3,2 . 3% 6/. *3,2 $PELHQW OLJKW , 6 3% '$7$ 3UR[LPLW\ %227 3$ 7; 8$57 0LFUR 3$ 5; -7$* 6:',2 3& 6:&/. 3$ 6:2 3% 1567 26& N 3$ 166 3$ 6&.
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STM32F413xG/H B.2 Application block diagrams Display application example Figure 85. Display application example 670 ) [[ SLQ SDFNDJH 7,0 BFK N %227 1:( $ 1( 12( )60& -7$* 6:',2 6:&/. 6:2 3$ 3$ 3% ' ' ' ' ' ' ' ' *3,2 %DFNOLJKW FRQWURO 7( 7HDULQJ 3& 3& 3& 3& :5 '& &6 5' 3& 3% 3& 3& 3& 3$ 3$ 3$ 3$ 'LVSOD\ 0RGXOH >' ' @ *3,2 ,QWHUUXSW 3% 3% 6&/ , & 6'$ 7RXFK 6FUHHQ &RQWUROOHU 06Y 9 Note: 16 bit displays interfaces can be address
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Application block diagrams B.3 STM32F413xG/H USB OTG full speed (FS) interface solutions Figure 86. USB controller configured as peripheral-only and used in Full speed mode 9''86% 9'' 9 WR 9''86% 9ROWDJH UHJXODWRU 9%86 '0 3$ 26&B,1 '3 3$ 26&B287 966 86% 6WG % FRQQHFWRU 670 ) [[ 670 ) [[ SLQV SDFNDJHV SLQV SDFNDJHV 06Y 9 06Y 9 1. External voltage regulator only needed when building a VBUS powered device. Figure 87.
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STM32F413xG/H Application block diagrams Figure 88. USB peripheral-only Full speed mode, VBUS detection using GPIO 9 9'' 9 9''86% *3,2 9%86 '0 3$ 26&B,1 '3 3$ 26&B287 966 86% 6WG % FRQQHFWRU 670 ) [[ SLQV SDFNDJHV 06Y 9 1. External voltage regulator only needed when building a VBUS powered device. Figure 89.
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Revision history STM32F413xG/H Revision history Table 115. Document revision history Date Revision 29-Aug-2016 1 Initial release.
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STM32F413xG/H Revision history Table 115. Document revision history Date 14-Jun-2017 19-Sep-2017 Revision Changes 5 Added: – Section 4.1: WLCSP81 pinout description – Section 4.2: UFQFPN48 pinout description – Section 4.3: LQFP64 pinout description – Section 4.4: LQFP100 pinout description – Section 4.5: LQFP144 pinout description – Section 4.6: UFBGA100 pinout description – Section 4.7: UFBGA144 pinout description – Section 4.8: Pins definition – Section 4.
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