Datasheet

DocID022265 Rev 6 85/121
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics
90
6.3.22 Communication interfaces
I
2
C interface characteristics
The I
2
C interface meets the timings requirements of the I
2
C-bus specification and user
manual rev. 03 for:
• S
tandard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I
2
C timings requirements are guaranteed by design when the I2Cx peripheral is
properly configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with th
e following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V
DDIOx
is disabled, but is still present. Only FTf I/O pins
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I
2
C I/Os characteristics.
All I
2
C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 60. IWDG min/max timeout period at 40 kHz (LSI)
(1)
1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Prescaler divider PR[2:0] bits
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
Unit
/4 0 0.1 409.6
ms
/8 1 0.2 819.2
/16 2 0.4 1638.4
/32 3 0.8 3276.8
/64 4 1.6 6553.6
/128 5 3.2 13107.2
/256 6 or 7 6.4 26214.4
Table 61. WWDG min/max timeout value at 48 MHz (PCLK)
Prescaler WDGTB Min timeout value Max timeout value Unit
1 0 0.0853 5.4613
ms
2 1 0.1706 10.9226
4 2 0.3413 21.8453
8 3 0.6826 43.6906
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