Datasheet

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STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics
90
Figure 27. 12-bit buffered / non-buffered DAC
1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
t
SETTLING
(3)
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±1LSB
-3 4 µsC
LOAD
≤ 50 pF, R
LOAD
≥ 5 kΩ
Update
rate
(3)
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
-- 1 MS/sC
LOAD
≤ 50 pF, R
LOAD
≥ 5 kΩ
t
WAKEUP
(3)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
-6.5 10 µs
C
LOAD
≤ 50 pF, R
LOAD
≥ 5 kΩ
input code between lowest and
highest possible ones.
PSRR+
(1)
Power supply rejection ratio
(to V
DDA
) (static DC
measurement
- –67 –40 dB No R
LOAD
, C
LOAD
= 50 pF
1. Guaranteed by design, not tested in production.
2. The DAC is in “quiescent mode” when it keeps the value steady on the output so no dynamic consumption is involved.
3. Data based on characterization results, not tested in production.
Table 55. DAC characteristics (continued)
Symbol Parameter Min Typ Max Unit Comments
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'$&B287[
%XIIHU
ELWGLJLWDO
WRDQDORJ
FRQYHUWHU

5/
&/
069
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