Datasheet

ST6200C/ST6201C/ST6203C
81/100
10.9 CONTROL PIN CHARACTERISTICS
10.9.1 Asynchronous RESET
Pin
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Notes:
1. Unless otherwise specified, typical data are based on T
A
=25°C and V
DD
=5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The R
ON
pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results,
not tested in production.
5. All short pulse applied on RESET
pin with a duration below t
h(RSTL)in
can be ignored.
6. The reset network protects the device against parasitic resets, especially in a noisy environment.
7. The output of the external reset circuit must have an open-drain output to drive the ST6 reset pad. Otherwise the device
can be damaged when the ST6 generates an internal reset (LVD or watchdog).
Figure 63. Typical R
ON
vs V
DD
with V
IN
=V
SS
Symbol Parameter Conditions Min Typ
1)
Max Unit
V
IL
Input low level voltage
2)
0.3xV
DD
V
V
IH
Input high level voltage
2)
0.7xV
DD
V
hys
Schmitt trigger voltage hysteresis
3)
200 400 mV
R
ON
Weak pull-up equivalent resistor
4)
V
IN
=V
SS
V
DD
=5V 150 350 900
k
Ω
V
DD
=3.3V 300 730 1900
R
ESD
ESD resistor protection V
IN
=V
SS
V
DD
=5V 2.8
k
Ω
V
DD
=3.3V
t
w(RSTL)out
Generated reset pulse duration
External pin or
internal reset sources
t
CPU
µ
s
t
h(RSTL)in
External reset pulse hold time
5)
µ
s
t
g(RSTL)in
Filtered glitch duration
6)
ns
3456
VDD [V]
100
200
300
400
500
600
700
800
900
1000
Ron [Kohm]
Ta=-40°C
Ta=25°C
Ta=95°C
Ta=125°C
1