Datasheet

DocID028475 Rev 7 37/114
LSM6DSL Digital interfaces
114
6 Digital interfaces
6.1 I
2
C/SPI interface
The registers embedded inside the LSM6DSL may be accessed through both the I
2
C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode. The device is compatible with SPI modes 0 and 3.
The serial interfaces are mapped onto the same pins. To select/exploit the I
2
C interface, the
CS line must be tied high (i.e connected to Vdd_IO).
6.2 Master I
2
C
If the LSM6DSL is configured in Mode2, a master I
2
C line is available. The master serial
interface is mapped in the following dedicated pins.
Table 10. Serial interface pin description
Pin name Pin description
CS
SPI enable
I
2
C/SPI mode selection (1: SPI idle mode / I
2
C communication enabled;
0: SPI communication mode / I
2
C disabled)
SCL/SPC
I
2
C Serial Clock (SCL)
SPI Serial Port Clock (SPC)
SDA/SDI/SDO
I
2
C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SDO/SA0
SPI Serial Data Output (SDO)
I
2
C less significant bit of the device address
Table 11. Master I
2
C pin details
Pin name Pin description
MSCL I
2
C serial clock master
MSDA I
2
C serial data master
MDRDY I
2
C master external synchronization signal