Datasheet

DocID17530 Rev 2 25/54
LIS3DH Digital interfaces
54
6.1.1 I
2
C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH-to-LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the Master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the Master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the Master.
The Slave ADdress (SAD) associated to the LIS3DH is 001100xb. The SDO/SA0 pad can
be used to modify the less significant bit of the device address. If the SA0 pad is connected
to the voltage supply, LSb is ‘1’ (address 0011001b) else if SA0 pad is connected to ground,
the LSb value is ‘0’ (address 0011000b). This solution permits to connect and address two
different accelerometers to the same I
2
C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver
which has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I
2
C embedded inside the LIS3DH behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the
7 LSb represent the actual register address while the MSB enables address auto increment.
If the MSb of the SUB field is ‘1’, the SUB (register address) is automatically increased to
allow multiple data read/writes.
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)
the Master transmit to the slave with direction unchanged. Table 16 explains how the
SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Table 16. SAD+Read/Write patterns
Command SAD[6:1] SAD[0] = SA0 R/W SAD+R/W
Read 001100 0 1 00110001 (31h)
Write 001100 0 0 00110000 (30h)
Read 001100 1 1 00110011 (33h)
Write 001100 1 0 00110010 (32h)
Table 17. Transfer when master is writing one byte to slave
Master ST SAD + W SUB DATA SP
Slave SAK SAK SAK
Table 18. Transfer when master is writing multiple bytes to slave
Master ST SAD + W SUB DATA DATA SP
Slave SAK SAK SAK SAK