User`s guide

LZ87010 Advance User’s Guide Table of Contents
1/15/03 v
Chapter 11 – External Memory
11.1 Theory of Operation .....................................................................................11-1
11.1.1 Writing to External Memory ................................................................... 11-1
11.1.2 Reading from External Memory............................................................. 11-1
11.2 Signals.......................................................................................................... 11-3
11.3 Registers ...................................................................................................... 11-4
11.4 External Memory Timing .............................................................................. 11-5
Chapter 12 – Interrupts
12.1 Theory of Operation .....................................................................................12-1
12.1.1 Interrupt-Related Registers ................................................................... 12-1
12.1.2 Interrupt Vectors .................................................................................... 12-2
12.1.2.1 Vectors and Status Bits .................................................................. 12-3
12.1.3 Interrupt Sources ................................................................................... 12-4
12.1.4 Interrupt Priority ..................................................................................... 12-5
12.1.5 External Interrupts ................................................................................. 12-5
12.1.5.1 INT[0] and INT[1]............................................................................12-5
12.1.5.2 INT[7:2]........................................................................................... 12-6
12.2 Signals.......................................................................................................... 12-7
12.3 Registers ...................................................................................................... 12-7
12.3.1 ALTFEN1 (Alternate Function Enable) Register ................................... 12-7
12.3.2 IE (Interrupt Enable) Register................................................................ 12-8
12.3.3 IE1 (Interrupt Enable 1) Register........................................................... 12-9
12.3.4 IP and IPH (Interrupt Priority) Registers .............................................. 12-10
12.3.5 IP1 and IPH1 (Interrupt Priority) Registers .......................................... 12-11
Chapter 13 – Analog Inputs (ADC)
13.1 Theory of Operation .....................................................................................13-1
13.2 Signals.......................................................................................................... 13-2
13.3 Registers ...................................................................................................... 13-3
13.3.1 ADCC (ADC Control) Register .............................................................. 13-3
13.3.2 ADCDH (ADC Data High) Register ....................................................... 13-4
13.3.3 ADCDL (ADC Data Low) Register......................................................... 13-5
Chapter 14 – Analog Outputs (DAC)
14.1 Theory of Operation .....................................................................................14-1
14.1.1 Digital-to-Analog Converter (DAC) ........................................................ 14-1
14.1.2 Waveform Generator............................................................................. 14-3
14.2 Signals.......................................................................................................... 14-4
14.3 Registers ...................................................................................................... 14-4
14.3.1 DACC (DAC Control) Register .............................................................. 14-4
14.3.2 WGCTL0 and WGCTL1 (Control) Registers ......................................... 14-5
14.3.3 WGCFG0 and WGCFG1 (Configuration) Registers .............................. 14-6
14.3.4 WGINX0 and WGINX1 (Index) Registers.............................................. 14-7
14.3.5 WGMA0 and WGMA1 (Memory Address) Registers............................. 14-7
14.3.6 WGMD0 and WGMD1 (Memory Data) Registers.................................. 14-8