User`s guide

8051-Compatible Core LZ87010 Advance User’s Guide
3-2 1/15/03
3.2.1 ACC (Accumulator) Register
The ACC (Accumulator) register provides an 8-bit value as one of the operands for many
processor instructions.
3.2.2 B Register
The B register provides the second operand for a multiply or divide instruction, and can
also be used as a read/write scratchpad register.
3.2.3 DPH, DPL, DPH1, and DPL1 (Data Pointer) Registers
The DPL, DPH, DPL1, and DPH1 registers make up the two Data Pointer (DPTR) regis-
ters, of which only one is active at a time. DPTR uses a pair of registers, either DPL and
DPH, or DPL1 and DPH1. Which register pair is used depends on the state of the DPS
(Data Pointer Select) register. The DPTR register is used in instructions requiring 16-bit
addressing. The lower 8 bits come from the DPL or DPL1 register, while the upper 8 bits
come from the DPH or DPH1 register.
Table 3-2. ACC (Accumulator) Register
BIT 7 6 5 4 3 2 1 0
FIELD ACC[7] ACC[6] ACC[5] ACC[4] ACC[3] ACC[2] ACC[1] ACC[0]
RESET 000 0 0 000
RW RW RW RW RW RW RW RW RW
ADDR 0xE0
Table 3-3. B Register
BIT 7 6 5 4 3 2 1 0
FIELD B[7] B[6] B[5] B[4] B[3] B[2] B[1] B[0]
RESET 000 0 0 000
RW RW RW RW RW RW RW RW RW
ADDR 0xF0
Table 3-4. DPH and DPH1 Registers
BIT 7 6 5 4 3 2 1 0
FIELD DPTR[15] DPTR[14] DPTR[13] DPTR[12] DPTR[11] DPTR[10] DPTR[9] DPTR[8]
RESET 000 0 0 000
RW RW RW RW RW RW RW RW RW
ADDR
DPH: 0x83
DPH1: 0x85
Table 3-5. DPL and DPL1 Registers
BIT 7 6 5 4 3 2 1 0
FIELD DPTR[7] DPTR[6] DPTR[5] DPTR[4] DPTR[3] DPTR[2] DPTR[1] DPTR[0]
RESET 000 0 0 000
RW RW RW RW RW RW RW RW RW
ADDR
DPL: 0x82
DPL1: 0x84