Service manual

2-10. ISP2032
This IC has been developed specially for UP-3300 to achieve VGA
CHIP and PSRAM interfaces.
Pin descriotion
Pin
No.
Name I/O Function
1 /VMEM In
VIDEO MEMORY DECODE
C00000H ∼ C1FFFFH
16bit/8bit access, 8 bit read from the
CPU is treated as 16-bit on the VGA.
2 /VMEM2 In
VIDEO MEMORY DECODE (ONLY FOR
GRAPHICS MODE; 8BIT)
C80000H ∼ C9FFFFH 8-bit access only.
/VMEM and /VMEM2 differ in their
apparent address to each other, but the
contents of memory to be accessed are
the same.
They differ in access method
(WORD/BYTE).
3 /HWR In HIGH BYTE WRITE FROM CPU
4 /LWR In LOW BYTE WRITE FROM CPU
5 PHAI In CLOCK FROM CPU
6VCC
7 /ISPEN In for ISP (In System Program)
8 /VWAITI In WAIT FROM VGA CHIP (IOCHRDY)
9 /VWAIT Out
WAIT TO MPCA
There are following 2 ORs.
IOCHRDY from VGA CHIP
1 WAIT is generated when VRAM.
VGA I/O is accessed. (Because
IOCHRDY is slow, 1 WAIT is generated
prior to it.)
10 /DWRI In
DELAYED WRITE (FOR VGA CHIP
TIMING)
11 /DWRO Out WRITE FOR /DWRI
12 /DRDI In
DELAYED READ (FOR VGA CHIP
TIMING)
13 /DRD Out READ FOR /PRDI
14 RES Out
RESET OUTPUT
RESET
NOT (/RESET)
15 /RES In /RESET INPUT
16 A0 In A0
17 GND
18 A20 In A20
19 PCE21E Out
EXTENDED PSRAM1 DECODE (EVEN)
800000H ∼ 8FFFFFH
20 PCE210 Out
EXTENDED PSRAM1 DECODE (ODD)
800000H ∼ 8FFFFFH
21 PCE220 Out
EXTENDED PSRAM2 DECODE (ODD)
900000H ∼ 9FFFFFH
22 PCE22E Out
EXTENDED PSRAM2 DECODE (EVEN)
900000H ∼ 9FFFFFH
23 /IPLON0 In IPL SIGNAL
24 /PSRF0 Out PSRAM REFRESH
25 /OWR Out PSRAM WRITE (ODD SIDE)
26 /M3SWP Out
MODE3 BUS SWAP (FOR PSRAM
ACCESS WHEN IPL)
27 Y2/SCLK ISP
28 VCC
29 Y1/RESET ISP
30 MODE ISP
31 RASPN2E In
EXTENDED PSRAM2 DECODE
(FROM MPCA)
800000H ∼ 9FFFFFH
Pin
No.
Name I/O Function
32 RASPN2 In
EXTENDED PSRAM2 DECODE
(FROM MPCA)
800000H ∼ 9FFFFFH
33 /RASPN12 In
PSRAM DECODE (FROM MPCA)
600000H ∼ 9FFFFFH
34 /AS In /AS FROM CPU
35 /RD In /RD FROM CPU
36 /RFSH In /RFSH FROM CPU
37 /SMEMR Out VIDEO MEMORY READ (TO VGA CHIP)
38 /SMEMW Out
VIDEO MEMORY WRITE (TO VGA
CHIP)
39 GND
40 /COE0 Not used
41 /IORD Out VGA IO READ (TO VGA CHIP)
42 /IOWR Out VGA IO WRITE (TO VGA CHIP)
43 /SBHE Out BUS HIGH ENABLE (TO VGA CHIP)
44 /VIO2 Out VGA IO CHIP SELECT
3. Address map
3-1. Total memory space
The address map of the total memory space is shown below. As you
can see, the memory space is divided into the following 5 blocks:
0page area (including the I/O area)
• VRAM
• RAM
• ROM
• Extended I/O area
000000h
0 page area
(64KB)
00FFFFh
200000h
600000h
C00000h
F00000h
FFFFFFh
Extended I/O area
(1MB)
(6MB)
(2MB)
Flash
RAM
(4MB)
VRAM
(1MB)
EP-ROM
D00000h
* The expanded I/O area means
the space for the I/O device
addressed in the area excluding
the 0 page one.
MPCA8 uses FFFF00h to
FFFFFFh for the addressed
register (BAR) of SSP.
The I/O register for VGAC is
included.
* In the 0 page area, lower 64KB
or less of the flash area is
mapped.
By mapping the ROM area, the
reset start and other vectors
become addressable.
Fig. 2