User Manual

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1. Tracking offset adjustment
When the servo and laser are both off, the DSP of the ASIC
(IC402) samples the TE (tracking error) signal in order to con-
trol the offset cancel of SSI33P3721 (IC831) in order to can-
cel the electrical offset.
2. Tracking gain adjustment
When the focus servo is on, the DSP of the ASIC (IC402)
measures the amplitude of the TE signal and uses it to set
the CGA amp gain of the SSI (IC831).
3. Balance adjustment of main PP and sub PP
This measures the DC offset when shifting to the inside and
to the outside occurs, with respect to the center of the TE
signal when the actuator is shifted 0.83 V to the outside, when
it is shifted 0.83 V to the inside and when it is at the standard
position.
4. Servo ON (disc rotation offset tracking)
The DSP of the ASIC (IC402) moves the tracking actuator to
the left or right to control the TE signal so that its AC compo-
nent is “0”.
2-3-2. FCM/ADDR AMPLIFIER
1. FCM AMPLIFIER
FCM is an abbreviation for Fine Clock Mark. This is used as
the external clock reference to generate the signal which be-
comes the syncronizing standard for the drive circuit board.
Fig. 6
2. FCLKPP/FCLKNP/FCLKZ
These are generated from the FCM signal by the comparator
(IC852) according to the timing shown in Fig. 7.
1. When LAND is on, the lead channel macro of the ASIC
judges that a FCM has been detected after the FCLKPP
signal has been detected and the FCLKZ signal is rising.
2. When GROOVE is on, the lead channel macro of the ASIC
judges that a FCM has been detected after the FCLKNP
signal has been detected and the FCLKZ singal is falling.
1. Fine clock mark (FCM)
A computation ((A+B)–(C+D)) is carried out on the signals
from the photosensor, after which they pass through the VCA
circuit (IC853) and LPF circuit, and then the FCM signal am-
plitudes pass through the peak hold and bottom hold circuits
and are input to the DSP of the ASIC (IC402), where A/D
conversion is carried out. At the DSP of the ASIC (IC402), the
D/A value of the signal (FCLKGC) which has had the control
voltage adjusted by the VCA (IC853) is changed so that the
FCM level is set to the level which is necessary for the
FCLKNP and FCLKPP signals to be generated. Furthermore,
DSP of the ASIC (IC402) and the above circuits set the slice
level to 50 % - 70 % of the +/– side FCM marks so that the
comparator (IC852) (FCLKPP and FCLKNP) singals do not
delay the transfer of the address signals. The above circuits
adjust the signals so that the FCM amplitude is at about the
same level when at the default recording and playback power.
Furthermore, a ratio of 60 % or more between the + side and
the – side of the FCM signal is necessary when LAND is on
and when GROOVE is on. The DSP controls the control po-
tential of the VCA (IC853) so that the Vpp of the FCM signal
is about TYP 1.7 Vp-p. Furthermore, the signal interval for
the FCM signals is 532 x 50 ns = 26.6 µs.
LAND
FCLKPP
FCLKZ
FCLKNP
GROOVE
Fig. 7
C
D
B
A
outside
inside
Land
Land
Land
Groove
Groove
TPP Matrix
[(A+B)-(C+D)]
IC814
(AD8054)
IC854
(AD8054)
IC855
(ADG701)
IC857
(AD8534)
LC
Filter
A, B, C, D
FCLKGC
VCA variable
range (± 4dB)
Ctrl
IC853
(BA7655)
LC
Filter
IC854
(AD8054)
Gain-Amp
x2
FCMK signal
obwervation
termanal
(TP808)
comparator
input allowable
value (0.8~3.6V)
gain fixing
play: x 6.356
rec: x 3.33
Attenuator
WG
"0" REC
"1" PLAY
Amp
PEAK HOLD
circuit
BOTTOM
HOLD
circuit
FCLKAMPL
FCLKAMPBTM
DSP process
ASIC
IC851
(AD8534)
IC857
(AD8534)
primary
function
circuit
primary
function
circuit
Comparator
IC852
(LT1721)
FCM-PP
160
AS-MO ASIC
FCLKPP
Comparator
IC852
(LT1721)
FCM-NP
161
FCLKNP
Comparator
IC852
(LT1721)
FCM-Z
162
FCLKSLS
FCLKSLSBTM
VC25
FCLKNP
FCLKPP
2.5V
lower slice level
upper slice level
LAND
FCM
LAND
FCM
GROOVE
2.5V
2.5V
FCLKZ
26.6[µs]
A/D
A/D
D/A
D/A
The OA amplifiers, analog switch
and the power supply of the
comparator IC are all 5V.