User Manual

CompactFlash Memory Card Interface Description
3-18 CompactFlash
®
Memory Card Product Manual, Rev. 10.0 © 2002 SANDISK CORPORATION
Table 3-13. PIO Data Transfer To/From Device
PIO Timing Parameters Mode 0 ns Mode 1 ns Mode 2 ns Mode 3 ns Mode 4 ns Note
t
0
Cycle time (min) 600 383 240 180 120 1
t
1
Address valid to IORD-/IOWR- setup (min) 70 50 30 30 25
t
2
IORD-/IOWR- pulse width 16-bit (min) 165 125 100 80 70 1
t
2i
IORD-/IOWR- recovery time (min) - - - 70 25 1
t
3
IOWR- data setup (min) 60 45 30 30 20
t
4
IOWR- data hold (min) 30 20 15 10 10
t
5
IORD- data setup (min) 50 35 20 20 20
t
6
IORD- data hold (min) 5 5 5 5 5
t
6z
IORD- data tri-state (max) 30 30 30 30 30 2
t
9
IORD-/IOWR- to address valid hold (min) 20 15 10 10 10
1. t
0
is the minimum total cycle time, t
2
is the minimum command active time, and t
2i
is the minimum command
recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time
and the actual command inactive time. The three timing requirements of t
0,
t
2
, and t
2i
shall be met. The minimum total
cycle time requirements are greater than the sum of t
2
and t
2i.
This means a host implementation may lengthen either
or both t
2
or t
2i
to ensure that t
0
is equal to or greater than the value reported in the devices IDENTIFY DEVICE data.
A device implementation shall support any legal host implementation.
2. This parameter specifies the time from the negation edge of /IORD to the time that the data bus is no longer
driven by the device (tri-state).
3. SanDisk CompactFlash Memory Cards do not assert an -IORDY signal.
3.4. Card Configuration
The CompactFlash Memory Cards are identified by appropriate information in the Card Information Structure (CIS).
The following configuration registers are used to coordinate the I/O spaces and the Interrupt level of cards that are
located in the system. In addition, these registers provide a method for accessing status information about the
CompactFlash Card that may be used to arbitrate between multiple interrupt sources on the same interrupt level or to
replace status information that appears on dedicated pins in memory cards that have alternate use in I/O cards.