S3C8275X/F8275X/C8278X /F8278X/C8274X/F8274X 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1.
Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.
NOTIFICATION OF REVISIONS ORIGINATOR: Samsung Electronics, LSI Development Group, Gi-Heung, South Korea PRODUCT NAME: S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 8-bit CMOS Microcontroller DOCUMENT NAME: S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X User's Manual, Revision1.4 DOCUMENT NUMBER: 21.
REVISION HISTORY Revision Date Remark 0 February, 2005 1 April, 2005 First edition. Reviewed by Finechips. 1.1 July, 2005 Second edition. Reviewed by Finechips. 1.2 August, 2005 Third edition. Reviewed by Finechips. 1.3 May, 2006 Fourth edition. Reviewed by Finechips 1.4 April, 2007 Fifth edition. Reviewed by Finechips Preliminary spec for internal release only.
REVISION DESCRIPTIONS 1. Electrical Data Table 17-12. A.C. Electrical Characteristics for Internal Flash ROM (TA = − 25 °C to + 85 °C, VDD = 2.0 V Parameter to 3.6 V) Symbol Conditions Min Typ Max Unit Ftp − 30 − − µs Chip erasing time (2) Ftp1 − 50 − − ms Sector erasing time (3) Ftp2 − 10 − − ms Data access time FtRS − − 25 − ns FNwe − − − 10,000(4) Times Programming time (1) Number of writing/erasing NOTES: 1.
Descriptions of Revision 1.4 1. Smart Option Area The Figures are modified about smart option area. Those are “Figure 2-1. Program Memory Address Space” and “Figure 5-3. ROM Vector Address Area”. 2. CHAPTHER 17. Electrical Data It is changed “VDD = 2.0 V to 3.6 V” into “VDD = 2.2 V to 3.6 V” in the Table 17-12. 3. DEVICE NAME The device name is changed S3C8275/F8275/C8278/F8278/C8274/F8274 to S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X. The ‘X’ means ‘Commercial type’.
Preface The S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Microcontroller User's Manual is designed for application designers and programmers who are using the S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X microcontroller for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptions Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure.
Table of Contents Part I — Programming Model Chapter 1 Product Overview S3C8-Series Microcontrollers .......................................................................................................................1-1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Microcontroller.......................................................1-1 Flash..............................................................................................................................................................
Table of Contents (Continued) Chapter 4 Control Registers Overview ....................................................................................................................................................... 4-1 Chapter 5 Interrupt Structure Overview ....................................................................................................................................................... 5-1 Interrupt Types .........................................................................
Table of Contents (Continued) Part II Hardware Descriptions Chapter 7 Clock Circuit Overview........................................................................................................................................................7-1 System Clock Circuit ............................................................................................................................7-1 Main Oscillator Circuits.........................................................................................
Table of Contents (Continued) Chapter 11 Timer 1 One 16-bit Timer Mode (Timer 1) ................................................................................................................. 11-1 Overview .............................................................................................................................................. 11-1 Function Description ............................................................................................................................
Table of Contents (Continued) Chapter 16 Embedded Flash Memory Interface Overview........................................................................................................................................................16-1 User Program Mode ......................................................................................................................................16-2 Flash Memory Control Registers (User Program Mode).................................................................
List of Figures Figure Number 1-1 1-2 Title Page Number 1-4 1-5 1-6 1-7 1-8 1-9 1-10 Block Diagram ............................................................................................................1-3 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Assignments (64-QFP-1420F) .........................................................................................................1-4 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Assignments (64-LQFP-1010) ......................................
List of Figures Figure Number Title Page Number 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 S3C8-Series Interrupt Types ..................................................................................... 5-2 S3C8275X/C8278X/C8274X Interrupt Structure ....................................................... 5-3 ROM Vector Address Area ........................................................................................ 5-4 Interrupt Function Diagram ...........................................................
List of Figures (Continued) Page Number Title Page Number 9-19 9-20 9-21 9-22 9-23 Port 4 High-Byte Control Register (P4CONH) ...........................................................9-15 Port 4 Low-Byte Control Register (P4CONL).............................................................9-16 Port 5 High-Byte Control Register (P5CONH) ...........................................................9-17 Port 5 Low-Byte Control Register (P5CONL).............................................................
List of Figures (Concluded) Page Number Title Page Number 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 Stop Mode Release Timing When Initiated by an External Interrupt......................... 17-5 Stop Mode Release Timing When Initiated by a RESET .......................................... 17-6 Input Timing for External Interrupts ........................................................................... 17-7 Input Timing for RESET ......................................................................
List of Tables Table Number Title Page Number 1-1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Descriptions ................. 1-6 2-1 2-2 S3C8275X Register Type Summary .......................................................................... 2-5 S3C8278X/C8274X Register Type Summary............................................................ 2-5 4-1 4-2 4-3 Set 1 Registers...........................................................................................................
List of Tables (Continued) Table Number Title Page Number 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 Absolute Maximum Ratings........................................................................................17-2 D.C. Electrical Characteristics ....................................................................................17-2 Data Retention Supply Voltage in Stop Mode ............................................................17-5 Input/Output Capacitance.................
List of Programming Tips Description Chapter 2: Page Number Address Spaces Using the Page Pointer for RAM Clear (Page 0, Page 1) ........................................................................ 2-9 Setting the Register Pointers .................................................................................................................... 2-13 Using the RPs to Calculate the Sum of a Series of Registers .................................................................
List of Register Descriptions Register Identifier BLDCON BTCON CLKCON CLOCON EXTICONH EXTICONL EXITPND FLAGS FMCON FMSECH FMSECL FMUSR IMR IPH IPL IPR IRQ LCON OSCCON P0CONH P0CONL P0PUR P1CONH P1CONL P1PUR P2CONH P2CONL P2PUR P3CONH P3CONL P3PUR P4CONH P4CONL P5CONH P5CONL P6CON PP RP0 RP1 SIOCON SPH SPL STPCON SYM TACON TBCON WTCON Full Register Name Page Number Battery Level Detector Control Register ....................................................................
List of Instruction Descriptions Instruction Mnemonic ADC ADD AND BAND BCP BITC BITR BITS BOR BTJRF BTJRT BXOR CALL CCF CLR COM CP CPIJE CPIJNE DA DEC DECW DI DIV DJNZ EI ENTER EXIT IDLE INC INCW IRET JP JR LD LDB Full Register Name Page Number Add with Carry............................................................................................................ 6-14 Add .............................................................................................................................
List of Instruction Descriptions (Continued) Instruction Mnemonic LDC/LDE LDCD/LDED LDCI/LDEI LDCPD/LDEPD LDCPI/LDEPI LDW MULT NEXT NOP OR POP POPUD POPUI PUSH PUSHUD PUSHUI RCF RET RL RLC RR RRC SB0 SB1 SBC SCF SRA SRP/SRP0/SRP1 STOP SUB SWAP TCM TM WFI XOR xxii Full Register Name Page Number Load Memory..............................................................................................................6-52 Load Memory and Decrement .............................................................
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 1 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes.
PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X FEATURES CPU Watch Timer • SAM88RC CPU core Memory • • Program Memory(ROM) - 16K×8 bits program memory(S3C8275X/F8275X) - 8K×8 bits program memory(S3C8278X/F8278X) - 4K×8 bits program memory(S3C8274X/F8274X) - Internal flash memory(Program memory) √ Sector size: 128 Bytes √ 10 Years data retention √ Fast programming time: + Chip erase: 50ms + Sector erase: 10ms + Byte program: 30us √ User programmable by ‘LDC’ instruction √ Endurance: 10,00
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW BLOCK DIAGRAM TAOUT/P0.4 T1CLK/P0.3 TBOUT/P0.5 8-Bit Timer/ Counter A 8-Bit Timer/ Counter B P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/T1CLK P0.4/TAOUT P0.5/TBOUT P0.6/CLKOUT P0.7/BUZ 16-Bit Timer/ Counter 1 XIN nRESET XTIN XOUT XTOUT VREG Watchdog Timer Basic Timer Low Voltage Reset Port I/O and Interrupt Control I/O Port 0 Clock Out Block CLKOUT/P0.6 Battery Level Detector VBLDREF/ P2.0/SEG31 Watch Timer BUZ/P0.7 COM0-COM3/P6.0-P6.
PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 64 63 62 61 60 59 58 57 56 55 54 53 52 SEG1/P5.6 SEG2/P5.5 SEG3/P5.4 SEG4/P5.3 SEG5/P5.2 SEG6/P5.1 SEG7/P5.0 SEG8/P4.7 SEG9/P4.6 SEG10/P4.5 SEG11/P4.4 SEG12/P4.3 SEG13/P4.2 PIN ASSIGNMENT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 S3C8275X/F8275X S3C8278X/F8278X S3C8274X/F8274X (64-QFP-1420F) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG14/P4.1 SEG15/P4.0 SEG16/P3.7 SEG17/P3.6 SEG18/P3.5 SEG19/P3.4 SEG20/P3.3 SEG21/P3.
PRODUCT OVERVIEW 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SEG1/P5.6 SEG2/P5.5 SEG3/P5.4 SEG4/P5.3 SEG5/P5.2 SEG6/P5.1 SEG7/P5.0 SEG8/P4.7 SEG9/P4.6 SEG10/P4.5 SEG11/P4.4 SEG12/P4.3 SEG13/P4.2 SEG14/P4.1 SEG15/P4.0 SEG16/P3.7 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S3C8275X/F8275X S3C8278X/F8278X S3C8274X/F8274X (64-LQFP-1010) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG17/P3.6 SEG18/P3.5 SEG19/P3.4 SEG20/P3.3 SEG21/P3.2 SEG22/P3.1 SEG23/P3.
PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PIN DESCRIPTIONS Table 1-1. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Descriptions Pin Names Pin Type Pin Description Circuit Type Pin No. Shared Functions P0.0−P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 I/O I/O port with bit-programmable pins; Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups; P0.0−P0.2 are alternately used for external interrupt input(noise filters, interrupt enable and pending control).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW Table 1-1. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Descriptions (Continued) Pin Names VLC0−VLC2 Pin Type − Pin Description LCD power supply pins. Circuit Type Pin No. Shared Functions − 6−8 − INT0−INT2 INT3−INT7 I/O External interrupts input pins. E-4 18−20 29−33 P0.0−P0.2 P1.3−P1.7 T1CLK I/O Timer 1/A external clock input. E-4 21 P0.3 TAOUT I/O Timer 1/A clock output. E-4 22 P0.
PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PIN CIRCUITS VDD VDD Pull-Up Resistor P-Channel In In N-Channel Schmitt Trigger Figure 1-5. Pin Circuit Type B (nRESET) Figure 1-4. Pin Circuit Type A VDD VDD Pull-up Resistor Resistor Enable Open Drain P-CH I/O Data N-CH Output Disable Schmitt Trigger Figure 1-6.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW VLC0 VLC1 COM/SEG Out Output Disable VLC2 VSS Figure 1-7. Pin Circuit Type H-4 VDD VDD Pull-Up Resistor Resistor Enable Open Drain P-CH Data I/O Output Disable 1 N-CH SEG Output Disable 2 Circuit Type H-4 Figure 1-8. Pin Circuit Type H-8 (P2.1– P2.
PRODUCT OVERVIEW S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X VDD VDD Pull-Up Resistor Resistor Enable P-CH Data I/O Output Disable 1 N-CH COM/SEG Output Disable 2 Circuit Type H-4 Figure 1-9.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PRODUCT OVERVIEW VDD VDD Pull-Up Resistor Resistor Enable Open-Drain P-CH Data I/O Output Disable 1 SEG Alternative Function N-CH Circuit Type H-4 BLDEN BLD Select To BLD Figure 1-10. Pin Circuit Type H-10 (P2.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 2 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C8275X/C8278X/C8274X microcontroller has two types of address space: • Internal program memory (ROM) • Internal register file A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file. The S3C8275X has an internal 16-Kbyte mask-programmable ROM. The S3C8278X has an internal 8-Kbyte mask-programmable ROM.
ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PROGRAM MEMORY (ROM) Program memory (ROM) stores program codes or table data. The S3C8275X has 16K bytes internal maskprogrammable program memory, the S3C8278X has 8K bytes, the S3C8274X has 4K bytes. The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this address range can be used as normal program memory.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES SMART OPTION ROM Address: 003EH MSB .7 .6 .5 .4 .3 .2 .
ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Smart option is the ROM option for start condition of the chip. The ROM address used by smart option is from 003CH to 003FH. The ISP of smart option (003EH) is available in the S3F8275X only. The default value of ROM address 003EH is FFH. And ROM address 003EH should be kept FFH when used the S3C8275X/C8278X/F8278X/C8274X/F8274X. The LVR of smart option (003FH) is available in all the device, S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES REGISTER ARCHITECTURE In the S3C8275X/C8278X/C8274X implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area. In case of S3C8275X the total number of addressable 8-bit registers is 605.
ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Set1 FFH Bank 1 FFH 64 Bytes FFH Bank 0 and System Peripheral Control System and Registers Peripheral Control Registers (Register Addressing Mode) 32 Bytes E0H DFH Page 0 Set 2 General-Purpose Data Registers E0H (Indirect Register, Indexed Mode, and Stack Operations) System Registers (Register Addressing Mode) D0H CFH Page 1 256 Bytes C0H BFH General Purpose Register (Register Addressing Mode) Page 0 C0H Page 2 ~ 0FH 192 Bytes
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES Set1 Bank 1 FFH E0H 64 Bytes FFH Bank 0 and System Peripheral Control System and Registers Peripheral Control Registers (Register Addressing Mode) 32 Bytes DFH Page 0 Set 2 General-Purpose Data Registers E0H (Indirect Register, Indexed Mode, and Stack Operations) System Registers (Register Addressing Mode) D0H CFH C0H BFH General Purpose Register (Register Addressing Mode) 256 Bytes Page 0 C0H Page 2 ~ 0FH 192 Bytes Prime Data
ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X REGISTER PAGE POINTER (PP) The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES PROGRAMMING TIP — Using the Page Pointer for RAM Clear (Page 0, Page 1) RAMCL0 RAMCL1 ; Destination ← 0, Source ← 0 LD PP,#00H SRP #0C0H LD CLR DJNZ CLR R0,#0FFH @R0 R0,RAMCL0 @R0 ; R0 = 00H LD PP,#10H ; Destination ← 1, Source ← 0 LD CLR DJNZ CLR R0,#0FFH @R0 R0,RAMCL1 @R0 ; Page 1 RAM clear starts ; Page 0 RAM clear starts ; R0 = 00H NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is
ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH. The upper 32-byte area of this 64-byte space (E0H–FFH) is expanded two 32-byte register banks, bank 0 and bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware reset operation always selects bank 0 addressing.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes (00H–BFH) of the S3C8275X/C8278X/C8274X's two or one 256-byte register pages is called prime register area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing Modes.") The prime register area on page 0 is immediately addressable following a reset.
ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES USING THE REGISTER POINTS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH. To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction. (see Figures 2-8 and 2-9).
ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X F7H (R7) 8-Byte Slice F0H (R0) 1 1 1 1 0 X X X Register File Contains 32 8-Byte Slices X X X 8-Byte Slice 16-Byte Contiguous working Register block RP0 7H (R15) 0 0 0 0 0 0H (R0) RP1 Figure 2-9. Non-Contiguous 16-Byte Working Register Block PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H–85H using the register pointer.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file except for set 2.
ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Special-Purpose Registers Bank 1 General-Purpose Register Bank 0 FFH FFH Control Registers E0H Set 2 System Registers D0H CFH C0H C0H BFH RP1 Register Pointers RP0 Each register pointer (RP) can independently point to one of the 24 8-byte "slices" of the register file (other than set 2). After a reset, RP0 points to locations C0H-C7H and RP1 to locations C8H-CFH (that is, to the common working register area).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–CFH, as the active 16-byte working register block: RP0 → C0H–C7H RP1 → C8H–CFH This 16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file.
ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only. Examples 1. LD 0C2H,40H ; Invalid addressing mode! Use working register addressing instead: SRP #0C0H LD R2,40H ; R2 (C2H) → the value in location 40H 0C3H,#45H ; Invalid addressing mode! 2.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES RP0 RP1 Selects RP0 or RP1 Address OPCODE 4-bit address provides three low-order bits Register pointer provides five high-order bits Together they create an 8-bit register address Figure 2-13. 4-Bit Working Register Addressing RP0 0 1 1 1 0 RP1 0 0 0 0 1 1 1 1 0 0 0 Selects RP0 0 1 1 1 0 1 1 0 Register address (76H) R6 OPCODE 0 1 1 0 1 1 1 0 Instruction 'INC R6' Figure 2-14.
ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 8-BIT WORKING REGISTER ADDRESSING You can also use 8-bit working register addressing to access registers in a selected working register area. To initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value "1100B." This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working register addressing.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X RP1 RP0 0 1 1 0 0 ADDRESS SPACES 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 Selects RP1 R11 1 1 0 0 1 0 1 1 8-bit address form instruction 'LD R11, R2' Register address (0ABH) Specifies working register addressing Figure 2-16.
ADDRESS SPACES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SYSTEM AND USER STACK The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations. The S3C8275X/C8278X/C8274X architecture supports stack operations in the internal register file. Stack Operations Return addresses for procedure calls, interrupts, and data are stored on the stack.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESS SPACES Programming TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: SPL,#0FFH ; SPL ← FFH ; (Normally, the SPL is set to 0FFH by the initialization ; routine) PUSH PP ; Stack address 0FEH ← PP PUSH RP0 ; Stack address 0FDH ← RP0 PUSH RP1 ; Stack address 0FCH ← RP1 PUSH R3 ; Stack address 0FBH ← R3 POP R3 ; R3 ←
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 3 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand.
ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X REGISTER ADDRESSING MODE (R) In Register addressing mode (R), the operand value is the content of a specified register or register pair (see Figure 3-1). Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register.
ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory Example Instruction References Program Memory dst OPCODE REGISTER PAIR Points to Register Pair Program Memory Sample Instructions: CALL JP @RR2 @RR2 Value used in Instruction OPERAND Figure 3-4.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 Program Memory 4-bit Working Register Address dst src OPCODE ~ ~ 3 LSBs Point to the Working Register (1 of 8) ADDRESS ~ Sample Instruction: OR R3, @R6 Value used in Instruction Selected RP points to start fo working register block ~ OPERAND Figure 3-5.
ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INDIRECT REGISTER ADDRESSING MODE (Concluded) Register File MSB Points to RP0 or RP1 RP0 or RP1 Selected RP points to start of working register block Program Memory 4-bit Working Register Address Example Instruction References either Program Memory or Data Memory dst src OPCODE Next 2-bit Point to Working Register Pair (1 of 4) LSB Selects Value used in Instruction Register Pair Program Memory or Data Memory 16-Bit address points to pro
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. Please note, however, that you cannot access locations C0H–FFH in set 1 using Indexed addressing mode.
ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INDEXED ADDRESSING MODE (Continued) Register File MSB Points to RP0 or RP1 RP0 or RP1 ~ ~ Program Memory 4-bit Working Register Address OFFSET dst/src x OPCODE Selected RP points to start of working register block NEXT 2 Bits Point to Working Register Pair (1 of 4) LSB Selects + 8-Bits Register Pair Program Memory or Data Memory 16-Bit address added to offset 16-Bits 16-Bits OPERAND Value used in Instruction Sample Instructions:
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES INDEXED ADDRESSING MODE (Concluded) Register File MSB Points to RP0 or RP1 RP0 or RP1 Program Memory ~ ~ OFFSET 4-bit Working Register Address OFFSET src dst/src OPCODE Selected RP points to start of working register block NEXT 2 Bits Point to Working Register Pair LSB Selects + 8-Bits Register Pair Program Memory or Data Memory 16-Bit address added to offset 16-Bits 16-Bits OPERAND Value used in Instruction Sample Instructions
ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions: JP CALL C,JOB1 DISPLAY ; ; Where JOB1 is a 16-bit immediate address Where DISPLAY is a 16-bit immediate address Figure 3-11.
ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed. Only the CALL instruction can use the Indirect Address mode.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADDRESSING MODES RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction.
ADDRESSING MODES S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers. Program Memory OPERAND OPCODE (The Operand value is in the instruction) Sample Instruction: LD R0,#0AAH Figure 3-14.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 4 CONTROL REGISTER CONTROL REGISTERS OVERVIEW In this chapter, detailed descriptions of the S3C8275X/C8278X/C8274X control registers are presented in an easy-to-read format. You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format. Control register descriptions are arranged in alphabetical order according to register mnemonic.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 4-2.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER Table 4-3.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Bit number(s) that is/are appended to the register name for bit addressing Register ID Name of individual bit or related bits Register location in the internal register file Register address (hexadecimal) Full Register name FLAGS - System Flags Register D5H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER BLDCON — Battery Level Detector Control Register F4H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value – – 0 0 0 0 0 0 Read/Write – – R/W R R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 Not used for the S3C8275X/C8278X/C8274X .5 VIN Source Bit .4 .3 .2–.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BTCON — Basic Timer Control Register D3H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.4 Watchdog Timer Function Disable Code (for System Reset) 1 0 1 0 Other values .3–.2 .1 .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER CLKCON — System Clock Control Register D4H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 – – 0 0 – – – Read/Write R/W – – R/W R/W – – – Addressing Mode Register addressing mode only .7 Oscillator IRQ Wake-up Function Bit 0 Enable IRQ for main wake-up in power down mode 1 Disable IRQ for main wake-up in power down mode .6–.5 Not used for the S3C8275X/C8278X/C8274X (must keep always “0”) .4–.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CLOCON — Clock Output Control Register E8H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value – – – – – – 0 0 Read/Write – – – – – – R/W R/W Addressing Mode Register addressing mode only .7–.2 Not used for the S3C8275X/C8278X/C8274X (must keep always “0”) .1–.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER EXTICONH — External Interrupt Control Register (High Byte) F8H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P1.7 External Interrupt (INT7) Configuration Bits .5–.4 .3–.2 .1–.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X EXTICONL — External Interrupt Control Register (Low Byte) F9H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P1.3 External Interrupt (INT3) Configuration Bits .5–.4 .3–.2 .1–.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER EXTIPND — External Interrupt Pending Register F7H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P1.7/INT7 Interrupt Pending Bit .6 .5 .4 .3 .2 .1 .0 0 Interrupt request is not pending, pending bit clear when write 0 1 Interrupt request is pending (when read) P1.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X FLAGS — System Flags Register Bit Identifier .7 .6 D5H .5 Reset Value Read/Write Addressing Mode x x x R/W R/W R/W Register addressing mode only .7 Carry Flag (C) .6 .5 .4 .3 .2 .1 .0 4-12 Set 1 .4 .3 .2 .1 .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER FMCON — Flash Memory Control Register F0H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 – – 0 Read/Write R/W R/W R/W R/W R – – R/W Addressing Mode Register addressing mode only .7–.4 Flash Memory Mode Selection Bits 0 1 0 1 Programming mode 1 0 1 0 Sector erase mode 0 1 1 0 Hard lock mode Other values .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X FMSECH — Flash Memory Sector Address Register (High Byte) F2H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER FMUSR — Flash Memory User Programming Enable Register F1H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X IMR — Interrupt Mask Register DDH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W Addressing Mode R/W Register addressing mode only .7 Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P1.4–1.7 0 Disable (mask) 1 Enable (unmask) .6 Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P1.3 0 Disable (mask) 1 Enable (unmask) .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER IPH — Instruction Pointer (High Byte) DAH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.0 Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8).
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X IPR — Interrupt Priority Register Bit Identifier .7 FFH .6 .5 .4 .3 .2 .1 .0 x R/W x R/W x R/W x R/W x R/W Reset Value Read/Write Addressing Mode x x x R/W R/W R/W Register addressing mode only .7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C (note) .6 .5 .3 .2 .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER IRQ — Interrupt Request Register DCH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Addressing Mode Register addressing mode only .7 Level 7 (IRQ7) Request Pending Bit; External Interrupt P1.4–1.7 .6 .5 .4 .3 .2 .1 .0 0 Not pending 1 Pending Level 6 (IRQ6) Request Pending Bit; External Interrupt P1.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCON — LCD Control Register E0H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 – 0 Read/Write R/W R/W R/W R/W R/W R/W – R/W Addressing Mode Register addressing mode only .7 Internal LCD Dividing Resistors Enable Bit .6–.5 .4–.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER OSCCON — Oscillator Control Register E0H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 – – – 0 0 – 0 Read/Write R/W – – – R/W R/W – R/W Addressing Mode Register addressing mode only .7 Sub Oscillator Circuit Selection Bit 0 Initial state 1 Power saving circuit for sub oscillator (Automatically cleared to "0" when the sub oscillator is stopped by OSCCON.2). NOTES: 1. The OSCCON.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P0CONH — Port 0 Control Register (High Byte) E4H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P0.7/BUZ Configuration Bits .5–.4 .3–.2 .1–.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER P0CONL — Port 0 Control Register (Low Byte) E5H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P0.3/T1CLK Configuration Bits .5–.4 .3–.2 .1–.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P0PUR — Port 0 Pull-Up Control Register Bit Identifier .7 .6 E6H .5 .4 .3 .2 .1 .0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Reset Value Read/Write Addressing Mode 0 0 0 R/W R/W R/W Register addressing mode only .7 P0.7's Pull-up Resistor Enable Bit .6 .5 .4 .3 .2 .1 .0 0 Disable pull-up resistor 1 Enable pull-up resistor Set 1, Bank 0 P0.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER P1CONH — Port 1 Control Register (High Byte) E7H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P1.7/INT7 Configuration Bits .5–.4 .3–.2 .1–.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P1CONL — Port 1 Control Register (Low Byte) E8H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P1.3/INT3 Configuration Bits .5–.4 .3–.2 .1–.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER P1PUR — Port 1 Pull-up Control Register Bit Identifier .7 .6 F9H .5 .4 .3 .2 .1 .0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Reset Value Read/Write Addressing Mode 0 0 0 R/W R/W R/W Register addressing mode only .7 P1.7's Pull-up Resistor Enable Bit .6 .5 .4 .3 .2 .1 .0 0 Disable pull-up resistor 1 Enable pull-up resistor Set 1, Bank 0 P1.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P2CONH — Port 2 Control Register (High Byte) EAH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P2.7/SEG24 Configuration Bits .5-.4 .3–.2 .1–.0 4-28 0 0 Input mode 0 1 N-channel open-drain output mode 1 0 Push-pull output mode 1 1 Alternative function (SEG24) P2.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER P2CONL — Port 2 Control Register (Low Byte) EBH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P2.3/SEG28 Configuration Bits .5–.4 .3–.2 .1–.0 0 0 Input mode 0 1 N-channel open-drain output mode 1 0 Push-pull output mode 1 1 Alternative function (SEG28) P2.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P2PUR — Port 2 Pull-up Control Register Bit Identifier .7 .6 ECH .5 .4 .3 .2 .1 .0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Reset Value Read/Write Addressing Mode 0 0 0 R/W R/W R/W Register addressing mode only .7 P2.7's Pull-up Resistor Enable Bit .6 .5 .4 .3 .2 .1 .0 0 Disable pull-up resistor 1 Enable pull-up resistor Set 1, Bank 0 P2.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER P3CONH — Port 3 Control Register (High Byte) EDH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P3.7/SEG16 Configuration Bits .5–.4 .3–.2 .1–.0 0 0 Input mode 0 1 N-channel open-drain output mode 1 0 Push-pull output mode 1 1 Alternative function (SEG16) P3.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P3CONL — Port 3 Control Register (Low Byte) EEH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P3.3/SEG20 Configuration Bits .5–.4 .3–.2 .1–.0 4-32 0 0 Input mode 0 1 N-channel open-drain output mode 1 0 Push-pull output mode 1 1 Alternative function (SEG20) P3.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER P3PUR — Port 3 Pull-up Control Register Bit Identifier .7 .6 EFH .5 .4 .3 .2 .1 .0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W Reset Value Read/Write Addressing Mode 0 0 0 R/W R/W R/W Register addressing mode only .7 P3.7's Pull-up Resistor Enable Bit .6 .5 .4 .3 .2 .1 .0 0 Disable pull-up resistor 1 Enable pull-up resistor Set 1, Bank 0 P3.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P4CONH — Port 4 Control Register (High Byte) E9H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P4.7/SEG8 Configuration Bits .5–.4 .3–.2 .1–.0 4-34 0 0 Input mode 0 1 Input mode with pull-up resistor 1 0 Push-pull output mode 1 1 Alternative function (SEG8) P4.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER P4CONL — Port 4 Control Register (Low Byte) EAH Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P4.3/SEG12 Configuration Bits .5–.4 .3–.2 .1–.0 0 0 Input mode 0 1 Input mode with pull-up resistor 1 0 Push-pull output mode 1 1 Alternative function (SEG12) P4.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P5CONH — Port 5 Control Register (High Byte) EBH Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P5.7/SEG0 Configuration Bits .5–.4 .3–.2 .1–.0 4-36 0 0 Input mode 0 1 Input mode with pull-up resistor 1 0 Push-pull output mode 1 1 Alternative function (SEG0) P5.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER P5CONL — Port 5 Control Register (Low Byte) ECH Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P5.3/SEG4 Configuration Bits .5–.4 .3–.2 .1–.0 0 0 Input mode 0 1 Input mode with pull-up resistor 1 0 Push-pull output mode 1 1 Alternative function (SEG4) P5.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X P6CON — Port 6 Control Register EDH Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P6.3/COM3 Configuration Bits .5–.4 .3–.2 .1–.0 4-38 0 0 Input mode 0 1 Input mode with pull-up resistor 1 0 Push-pull output mode 1 1 Alternative function (COM3) P6.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER PP — Register Page Pointer DFH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.4 Destination Register Page Selection Bits 0 0 0 0 Destination: page 0 0 0 0 1 Destination: page 1 (Not used for the S3C8278X/C8274X) 0 0 1 0 Destination: page 2 Others .3– .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X RP0 — Register Pointer 0 D6H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 1 1 0 0 0 – – – Read/Write R/W R/W R/W R/W R/W – – – Addressing Mode Register addressing only .7–.3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256-byte working register areas in the register file.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER SIOCON — SIO Control Register E1H Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 SIO Shift Clock Selection Bit .6 .5 .4 .3 .2 .1 .0 0 Internal clock (P.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SPH — Stack Pointer (High Byte) D8H Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.0 Stack Pointer Address (High Byte) The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (SP15–SP8).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER STPCON — Stop Control Register FBH Set 1, Bank 0 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.0 STOP Control Bits 10100101 Enable stop instruction Other values Disable stop instruction NOTE: Before execute the STOP instruction, set this STPCON register as “10100101b”.
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SYM — System Mode Register DEH Set 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 – – x x x 0 0 Read/Write R/W – – R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 This bit must remain logic "0" .6–.5 Not used for the S3C8275X/C8278X/C8274X .4–.2 Fast Interrupt Level Selection Bits (1) .1 .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER TACON — Timer 1/A Control Register E6H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Timer 1 Operating Mode Selection Bit .6–.4 .3 .2 .1 .
CONTROL REGISTERS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TBCON — Timer B Control Register E7H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value – 0 0 0 0 0 0 0 Read/Write – R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Not used for the S3C8275X/C8278X/C8274X .6–.4 Timer B Clock Selection Bits 0 0 0 fxx/512 0 0 1 fxx/256 0 1 0 fxx/64 0 1 1 fxx/8 1 0 0 fxt (sub clock) Others .3 .2 .1 .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONTROL REGISTER WTCON — Watch Timer Control Register E1H Set 1, Bank 1 Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 Reset Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Watch Timer Clock Selection Bit .6 .5–.4 .3–.2 .1 .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 5 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vector address, the vector priorities are established in hardware. A vector address can be assigned to one or more sources.
INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT TYPES The three components of the S3C8 interrupt structure described before ⎯ levels, vectors, and sources ⎯ are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE S3C8275X/C8278X/C8274X INTERRUPT STRUCTURE The S3C8275X/C8278X/C8274X microcontroller supports twelve interrupt sources. All twelve of the interrupt sources have a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Figure 5-2.
INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C8275X/C8278X/C8274X interrupt structure are stored in the vector address area of the internal 16-Kbyte ROM, 0H−3FFFH, or 8, 4-Kbyte (see Figure 5-3). You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE Table 5-1. Interrupt Vectors Vector Address Decimal Value Hex Value 256 100H 242 Interrupt Source Request Reset/Clear Interrupt Level Priority in Level H/W S/W Basic timer overflow Reset − √ F2H Timer B match IRQ0 1 √ 240 F0H Timer 1/A match 0 √ 244 F4H SIO interrupt IRQ1 − √ 246 F6H Watch timer overflow IRQ2 − √ 224 E0H P0.0 external interrupt IRQ3 − √ 226 E2H P0.
INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur according to the established priorities. NOTE The system initialization routine executed after a reset must always contain an EI instruction to globally enable the interrupt structure.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The system-level control points in the interrupt structure are: — Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.
INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see Table 5-3). Table 5-3.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE SYSTEM MODE REGISTER (SYM) The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to control fast interrupt processing (see Figure 5-5). A reset clears SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4−SYM.2, is undetermined.
INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine. Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine.
INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Interrupt Priority Register (IPR) FFH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued for that level.
INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source. 3. The CPU checks the source's interrupt level. 4. The CPU generates an interrupt acknowledge signal. 5. Interrupt logic determines the interrupt's vector address. 6.
INTERRUPT STRUCTURE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H−FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to the stack. 2. Push the program counter's high-byte value to the stack. 3. Push the FLAG register values to the stack. 4.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INTERRUPT STRUCTURE FAST INTERRUPT PROCESSING (Continued) Two other system registers support fast interrupt processing: • The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the program counter values), and • When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated register called FLAGS' (“FLAGS prime”).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 6 INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM88RC instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 6-1.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET Table 6-1.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 6-1.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET Table 6-1.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.7−FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and FLAGS.2 are used for BCD arithmetic. The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank address status bit (FLAGS.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag. Z Zero Flag (FLAGS.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag D Decimal-adjust flag H Half-carry flag 0 Cleared to logic zero 1 Set to logic one * Set or cleared according to operation − Value is unaffected x Value is undefined Table 6-3.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET Table 6-4. Instruction Notation Conventions Notation cc Description Actual Operand Range Condition code See list of condition codes in Table 6-6. r Working register only Rn (n = 0−15) rb Bit (b) of working register Rn.b (n = 0−15, b = 0−7) r0 Bit 0 (LSB) of working register Rn (n = 0−15) rr Working register pair RRp (p = 0, 2, 4, ...
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) − 0 1 2 3 4 5 6 7 U 0 DEC R1 DEC IR1 ADD r1,r2 ADD r1,Ir2 ADD R2,R1 ADD IR2,R1 ADD R1,IM BOR r0–Rb P 1 RLC R1 RLC IR1 ADC r1,r2 ADC r1,Ir2 ADC R2,R1 ADC IR2,R1 ADC R1,IM BCP r1.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET Table 6-5.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADC — Add with carry ADC dst,src Operation: dst ← dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two'scomplement addition is performed.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ADD INSTRUCTION SET — Add ADD dst,src Operation: dst ← dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Z: S: V: Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise.
INSTRUCTION SET AND S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X — Logical AND AND dst,src Operation: dst ← dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected. Flags: C: Z: S: V: D: H: Unaffected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BAND INSTRUCTION SET — Bit AND BAND dst,src.b BAND dst.b,src Operation: dst(0) ← dst(0) AND src(b) dst(b) AND src(0) or dst(b) ← The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source). The resultant bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Z: S: V: D: H: Unaffected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BCP — Bit Compare BCP dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison. Flags: C: Z: S: V: D: H: Unaffected. Set if the two bits are the same; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BITC INSTRUCTION SET — Bit Complement BITC dst.b Operation: dst(b) ← NOT dst(b) This instruction complements the specified bit within the destination without affecting any other bits in the destination. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Cleared to "0". Undefined. Unaffected. Unaffected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BITR — Bit Reset BITR dst.b Operation: dst(b) ← 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET BITS — Bit Set BITS dst.b Operation: dst(b) ← 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BOR — Bit OR BOR dst,src.b BOR dst.b,src Operation: dst(0) ← dst(0) OR src(b) dst(b) OR src(0) or dst(b) ← The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Z: S: V: D: H: Unaffected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BTJRF INSTRUCTION SET — Bit Test, Jump Relative on False BTJRF dst,src.b Operation: If src(b) is a "0", then PC ← PC + dst The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRF instruction is executed. Flags: No flags are affected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b Operation: If src(b) is a "1", then PC ← PC + dst The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRT instruction is executed. Flags: No flags are affected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0) ← dst(0) XOR src(b) dst(b) XOR src(0) or dst(b) ← The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Z: S: V: D: H: Unaffected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CALL — Call Procedure CALL dst Operation: SP @SP SP @SP PC ← ← ← ← ← SP – 1 PCL SP –1 PCH dst The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET CCF — Complement Carry Flag CCF Operation: C ← NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CLR — Clear CLR dst Operation: dst ← "0" The destination location is cleared to "0". Flags: No flags are affected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET COM — Complement COM dst Operation: dst ← NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CP — Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Z: S: V: D: H: Set if a "borrow" occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA Operation: If dst – src Ir ← Ir = + "0", PC ← PC + RA 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. Otherwise, the instruction immediately following the CPIJE instruction is executed.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA Operation: If dst – src Ir ← Ir "0", PC + ← PC + RA 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise the instruction following the CPIJNE instruction is executed.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET DA — Decimal Adjust DA dst Operation: dst ← DA dst The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DA — Decimal Adjust DA (Continued) Example: Given: Working register R0 contains the value 15 (BCD), working register R1 contains 27 (BCD), and address 27H contains 46 (BCD): ADD DA R1,R0 R1 ; ; C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = C, R1 ← 3CH R1 ← 3CH + 06 If addition is performed using the BCD values 15 and 27, the result should be 42.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET DEC — Decrement DEC dst Operation: dst ← dst – 1 The contents of the destination operand are decremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DECW — Decrement Word DECW dst Operation: dst ← dst – 1 The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET DI — Disable Interrupts DI Operation: SYM (0) ← 0 Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled. Flags: No flags are affected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DIV — Divide (Unsigned) DIV dst,src Operation: dst ÷ dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT src The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst Operation: r ← If r r – 1 ≠ 0, PC ← PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X EI — Enable Interrupts EI Operation: SYM (0) ← 1 An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction. Flags: No flags are affected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET ENTER — Enter ENTER Operation: SP @SP IP PC IP ← ← ← ← ← SP – 2 IP PC @IP IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer. The program memory word that is pointed to by the instruction pointer is loaded into the PC, and the instruction pointer is incremented by two.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X EXIT — Exit EXIT Operation: ← ← ← ← IP SP PC IP @SP SP + 2 @IP IP + 2 This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two. Flags: No flags are affected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. In application programs, a IDLE instruction must be immediately followed by at least three NOP instructions. This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INC — Increment INC dst Operation: dst ← dst + 1 The contents of the destination operand are incremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET INCW — Increment Word INCW dst Operation: dst ← dst + 1 The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred; cleared otherwise. Unaffected. Unaffected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X IRET — Interrupt Return IRET IRET (Normal) Operation: FLAGS SP ← PC ← SP ← SYM(0) ← @SP SP + 1 @SP SP + 2 ← 1 IRET (Fast) PC ↔ IP FLAGS ← FLAGS' FIS ← 0 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0").
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ← dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X JR — Jump Relative JR cc,dst Operation: If cc is true, PC ← PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed. (See list of condition codes).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET LD — Load LD dst,src Operation: dst ← src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: 6-50 LD R0,#10H → R0 = 10H LD R0,01H → R0 = 20H, register 01H = 20H LD 01H,R0 → Register 01H LD R1,@R0 → R1 = 20H, R0 = 01H LD @R0,R1 → R0 = 01H, R1 = 0AH, register 01H = 0AH LD 00H,01H → Register 00H = 20H, register 01H = 20H LD 02H,@00H → Regi
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET LDB — Load Bit LDB dst,src.b LDB dst.b,src Operation: dst(0) ← src(b) or dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: No flags are affected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ← src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number for data memory. Flags: No flags are affected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst rr ← ← src rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Operation: dst rr ← ← src rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/ LDEPD dst,src Operation: rr dst ← ← rr – 1 src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented. The contents of the source location are then loaded into the destination location. The contents of the source are unaffected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src Operation: rr dst ← ← rr + 1 src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented. The contents of the source location are loaded into the destination location. The contents of the source are unaffected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LDW — Load Word LDW dst,src Operation: dst ← src The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: No flags are affected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET MULT — Multiply (Unsigned) MULT dst,src Operation: dst ← dst × src The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. Both operands are treated as unsigned integers. Flags: C: Z: S: V: D: H: Set if result is > 255; cleared otherwise. Set if the result is "0"; cleared otherwise.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X NEXT — Next NEXT Operation: PC IP ← ← @ IP IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two. Flags: No flags are affected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected. Format: opc Example: Bytes Cycles Opcode (Hex) 1 4 FF When the instruction NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X OR — Logical OR OR dst,src Operation: dst ← dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET POP — Pop From Stack POP dst Operation: dst ← @SP SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X POPUD — Pop User Stack (Decrementing) POPUD dst,src Operation: dst IR ← ← src IR – 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented. Flags: No flags are affected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET POPUI — Pop User Stack (Incrementing) POPUI dst,src Operation: dst IR ← ← src IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented. Flags: No flags are affected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PUSH — Push To Stack PUSH src Operation: SP ← @SP SP ← – 1 src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: No flags are affected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src Operation: IR dst ← ← IR –1 src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer. Flags: No flags are affected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src Operation: IR dst ← ← IR + 1 src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer. Flags: No flags are affected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET RCF — Reset Carry Flag RCF RCF Operation: C ← 0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: opc Example: Given: C = "1" or Bytes Cycles Opcode (Hex) 1 4 CF "0": The instruction RCF clears the carry flag (C) to logic zero.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X RET — Return RET Operation: PC ← @SP SP ← SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value. Flags: No flags are affected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET RL — Rotate Left RL dst Operation: C ← dst (7) dst (0) ← dst (7) dst (n 1) + ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag. 7 0 C Flags: C: Z: S: V: D: H: Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X RLC — Rotate Left Through Carry RLC dst Operation: dst (0) ← C ← dst (n C dst (7) + 1) ← dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero. 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the most significant bit position (bit 7) was "1".
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET RR — Rotate Right RR dst Operation: C ← dst (7) dst (0) ← dst (n) ← dst (0) dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C). 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0"; cleared otherwise.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X RRC — Rotate Right Through Carry RRC dst Operation: dst (7) C ← dst (n) ← C dst (0) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB). 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the least significant bit position (bit zero) was "1".
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET SB0 — Select Bank 0 SB0 Operation: BANK ← 0 The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file. Flags: No flags are affected. Format: opc Example: Bytes Cycles Opcode (Hex) 1 4 4F The statement SB0 clears FLAGS.0 to "0", selecting bank 0 register addressing.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SB1 — Select Bank 1 SB1 Operation: BANK ← 1 The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some S3C8-series microcontrollers.) Flags: No flags are affected. Format: opc Example: Bytes Cycles Opcode (Hex) 1 4 5F The statement SB1 sets FLAGS.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET SBC — Subtract with Carry SBC dst,src Operation: dst ← dst – src – c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SCF — Set Carry Flag SCF Operation: C ← 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: opc Example: The statement SCF sets the carry flag to logic one.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET SRA — Shift Right Arithmetic SRA dst Operation: dst (7) C ← dst (n) ← dst (7) dst (0) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. 7 6 0 C Flags: C: Z: S: V: D: H: Set if the bit shifted from the LSB position (bit zero) was "1".
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SRP/SRP0/SRP1 — Set Register Pointer SRP src SRP0 src SRP1 src Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7) ← src (3–7) If src (1) = 0 and src (0) = 1 then: RP1 (3–7) ← src (3–7) If src (1) = 0 and src (0) = 0 then: RP0 (4–7) ← src (4–7), RP0 (3) ← 0 RP1 (4–7) ← src (4–7), RP1 (3) ← 1 The source data bits one and zero (LSB) determine whether to write one or both of the register pointers, RP0 an
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SUB — Subtract SUB dst,src Operation: dst ← dst – src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand. Flags: C: Z: S: V: Set if a "borrow" occurred; cleared otherwise. Set if the result is "0"; cleared otherwise.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET SWAP — Swap Nibbles SWAP dst Operation: dst (0 – 3) ↔ dst (4 – 7) The contents of the lower four bits and upper four bits of the destination operand are swapped. 7 Flags: C: Z: S: V: D: H: 4 3 0 Undefined. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Undefined. Unaffected. Unaffected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TCM — Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET TM — Test Under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected.
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X WFI — Wait for Interrupt WFI Operation: The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt. Flags: No flags are affected.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X INSTRUCTION SET XOR — Logical Exclusive OR XOR dst,src Operation: dst ← dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 7 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The S3C8275X/C8278X/C8274X microcontroller has two oscillator circuits: a main clock and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU clock frequency of S3C8275X/C8278X/C8274X is determined by CLKCON register settings.
CLOCK CIRCUIT S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MAIN OSCILLATOR CIRCUITS SUB OSCILLATOR CIRCUITS 32.768 kHz XTIN XIN XTOUT XOUT 104 VREG Figure 7-1. Crystal/Ceramic Oscillator (fx) Figure 7-4. Crystal Oscillator (fxt) XTIN XIN XOUT XTOUT Figure 7-5. External Oscillator (fxt) Figure 7-2. External Oscillator (fx) XIN R XOUT Figure 7-3.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CLOCK CIRCUIT CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: • In stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation or an external interrupt (with RC delay noise filter). • In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers and timer/ counters.
CLOCK CIRCUIT S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in the set 1, at address D4H. It is read/write addressable and has the following functions: • Oscillator IRQ wake up function enable/disable • Oscillator frequency divide-by value CLKCON register settings control whether or not an external interrupt can be used to trigger a stop mode release (This is called the "IRQ wake-up" function).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CLOCK CIRCUIT CLOCK OUTPUT CONTROL REGISTER (CLOCON) The clock output control register, CLOCON, is located in set 1 bank 1, at address E8H. It is read/write addressable and has the following functions: • Clock output frequency selection After a reset, fxx/64 is select for clock output frequency because the reset value of CLOCON.1−.0 is "00b". Clock Output Control Register (CLOCON) E8H, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .
CLOCK CIRCUIT S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X OSCILLATOR CONTROL REGISTER (OSCCON) The oscillator control register, OSCCON, is located in set 1, bank 0, at address E0H. It is read/write addressable and has the following functions: • System clock selection • Main oscillator control • Sub oscillator control • Sub oscillator circuit selection OSCCON.0 register settings select Main clock or Sub clock as system clock.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X CLOCK CIRCUIT SWITCHING THE CPU CLOCK Data loading in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies. OSCCON.0 select the main clock (fx) or the sub clock (fxt) for the CPU clock. OSCCON.
CLOCK CIRCUIT S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X STOP Control Register (STPCON) FBH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB STOP control bits: Other values = Disable STOP instruction 10100101 = Enable STOP instruction NOTE: Before execute the STOP instruction, set this STPCON register as "10100101B". Otherwise the STOP instuction will not execute as well as reset will be generated. Figure 7-11.
RESET and POWER-DOWN S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 8 RESET and POWER-DOWN SYSTEM RESET OVERVIEW During a power-on reset, the voltage at VDD goes to High level and the nRESET pin is forced to Low level. The nRESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings the S3C8275X/C8278X/C8274X into a known operating status.
RESET and POWER-DOWN S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X HARDWARE RESET VALUES Table 8-1, 8-2, 8-3 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values: • A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. • An "x" means that the bit value is undefined after a reset.
RESET and POWER-DOWN S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 8-2.
RESET and POWER-DOWN S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 8-3.
RESET and POWER-DOWN S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 3 µA. All system functions stop when the clock “freezes”, but data stored in the internal register file is retained.
RESET and POWER-DOWN S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all peripherals remain active. Port pins retain the mode (input or output) they had at the time idle mode was entered. There are two ways to release idle mode: 1. Execute a reset.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 9 I/O PORTS I/O PORTS OVERVIEW The S3C8275X/C8278X/C8274X microcontroller has seven bit-programmable I/O ports, P0−P6. Port 0−port 5 are 8-bit ports, port 6 is 4-bit. This gives a total of 52 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all seven S3C8275X/C8278X/C8274X I/O port data registers. Data registers for ports 0, 1, 2, 3, 4, 5, and 6 have the general format shown in Figure 9-1. Table 9-2.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS PORT 0 Port 0 is an 8-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location F0H in set 1, bank 0. P0.0-P0.7 can serve as inputs (with or without pullup), as outputs (push-pull or open-drain) or you can be configured the following functions. • Low-nibble pins (P0.0−P0.3): INT0–INT2, T1CLK • High-nibble pins (P0.4−P0.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Port 0 Control Register, High Byte (P0CONH) E4H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 P0.7/BUZ .3 .2 .1 .0 LSB P0.5/TBOUT P0.6/CLKOUT P0.4/TAOUT P0CONH bit-pair pin configuration settings: 00 Schmitt trigger input mode 01 N-channel open-drain output mode 10 Push-pull output mode 11 Alternative function (BUZ, CLKOUT, TBOUT, TAOUT) Figure 9-2.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS Port 0 Pull-up Control Register (P0PUR) E6H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 LSB P0PUR bit configuration settings: 0 Disable pull-up resistor 1 Enable pull-up resistor NOTE: A pull-up resistor of port 0 is automatically disabled when the corresponding pin is selected as push-pull output or alternative function. Figure 9-4.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X External Interrupt Pending Register (EXTIPND) F7H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.7 P1.6 P1.5 P1.4 P1.3 P0.2 P0.1 P0.0 (INT7) (INT6) (INT5) (INT4) (INT3) (INT2) (INT1) (INT0) EXTIPND bit configuration settings: 0 No interrupt pending (when read), clear pending bit (when write) 1 Interrupt is pending (when read) Figure 9-6.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS PORT 1 Port 1 is an 8-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location F1H in set 1, bank 0. P1.0−P1.7 can serve as inputs (with or without pullup), as outputs (push-pull or open-drain) or you can be configured the following functions. • Low-nibble pins (P1.0−P1.3): SCK, SO, SI, INT3 • High-nibble pins (P1.4−P1.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Port 1 Control Register, High Byte (P1CONH) E7H, Set 1, Bank 0, R/W MSB .7 .6 P1.7/INT7 .5 .4 P1.6/INT6 .3 .2 P1.5/INT5 .1 .0 LSB P1.4/INT4 P1CONH bit-pair pin configuration settings: 00 Schmitt trigger input mode 01 N-channel open-drain output mode 10 Push-pull output mode 11 Not available Figure 9-7. Port 1 High-Byte Control Register (P1CONH) Port 1 Control Register, Low Byte (P1CONL) E8H, Set 1, Bank 0, R/W MSB .7 .6 P1.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS Port 1 Pull-up Control Register (P1PUR) E9H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 LSB P1PUR bit configuration settings: NOTE: 0 Disable pull-up resistor 1 Enable pull-up resistor A pull-up resistor of port 1 is automatically disabled when the corresponding pin is selected as push-pull output or alternative function. Figure 9-9.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X External Interrupt Control Register, Low Byte (EXTICONL) F9H, Set 1, Bank 0, R/W MSB .7 .6 P1.3/INT3 .5 .4 P0.2/INT2 .3 .2 P0.1/INT1 .1 .0 LSB P0.0/INT0 EXTICONL bit configuration settings: 00 Disable interrupt 01 10 Enable interrupt by falling edge Enable interrupt by rising edge 11 Enable interrupt by both falling and rising edge Figure 9-11.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS PORT 2 Port 2 is an 8-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location F2H in set 1, Bank 0. P2.0-P2.7 can serve as inputs (with or without pullup), as outputs (push-pull or open-drain) or you can be configured the following functions. • Low-nibble pins (P2.0-P2.3): SEG31−SEG28, VBLDREF • High-nibble pins (P2.4-P2.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Port 2 Control Register, Low Byte (P2CONL) EBH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 P2.3/SEG28 P2.2/SEG29 P2.1/SEG30 .1 .0 LSB P2.0/SEG31/VBLDREF P2CONL bit-pair pin configuration settings: 00 Input mode 01 N-channel open-drain output mode 10 Push-pull output mode 11 Alternative function (SEG28-SEG31/VBLDREF) Figure 9-14.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS PORT 3 Port 3 is an 8-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location F3H in set 1, bank 0. P3.0-P3.7 can serve as inputs (with or without pullup), as outputs (push-pull or open-drain) or you can be configured the following functions. • Low-nibble pins (P3.0-P3.3): SEG23-SEG20 • High-nibble pins (P3.4-P3.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Port 3 Control Register, Low Byte (P3CONL) EEH, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P3.3/SEG20 P3.2/SEG21 P3.1/SEG22 P3.0/SEG23 P3CONL bit-pair pin configuration settings: 00 Input mode 01 N-channel open-drain output mode 10 Push-pull output mode 11 Alternative function (SEG20-SEG23) Figure 9-17. Port 3 Low Byte Control Register (P3CONL) Port 3 Pull-up Control Register (P3PUR) EFH, Set 1, Bank 0, R/W MSB .7 .6 .5 .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location F4H in set 1, bank 0. P4.0-P4.7 can serve as inputs (with or without pullup), as push-pull output or you can be configured the following functions. • Low-nibble pins (P4.0-P4.3): SEG15-SEG12 • High-nibble pins (P4.4-P4.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Port 4 Control Register, Low Byte (P4CONL) EAH, Set 1, Bank 1, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P4.3/SEG12 P4.2/SEG13 P4.1/SEG14 P4.0/SEG15 P4CONH bit-pair pin configuration settings: 00 Input mode 01 Input with pull-up resistor 10 Push-pull output mode 11 Alternative function (SEG12-SEG15) Figure 9-20.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location F5H in set 1, bank 0. P5.0-P5.7 can serve as inputs (with or without pullup), as push-pull output or you can be configured the following functions. • Low-nibble pins (P5.0-P5.3): SEG7−SEG4 • High-nibble pins (P5.4-P5.
I/O PORTS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Port 5 Control Register, Low Byte (P5CONL) ECH, Set 1, Bank 1, R/W MSB .7 .6 P5.3/SEG4 .5 .4 P5.2/SEG5 .3 .2 P5.1/SEG6 .1 .0 LSB P5.0/SEG7 P5CONL bit-pair pin configuration settings: 00 Input mode 01 Input with pull-up resistor 10 Push-pull output mode 11 Alternative function (SEG4-SEG7) Figure 9-22.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X I/O PORTS PORT 6 Port 6 is a 4-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing or reading the port 6 data register, P6 at location F6H in set 1, bank 0. P6.0-P6.3 can serve as inputs (with or without pullup), as push-pull output or you can be configured the following functions. • Low-nibble pins (P6.0-P6.3): COM0−COM3 Port 6 Control Register (P6CON) Port 6 has an 8-bit control register: P6CON for P6.0-P6.3.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 10 BASIC TIMER BASIC TIMER OVERVIEW Basic timer (BT) can be used in two different ways: • As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. • To signal the end of the required oscillation stabilization interval after a reset or a stop mode release.
BASIC TIMER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1, address D3H, and is read/write addressable using Register addressing mode. A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of fxx/4096.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7−BTCON.4 to any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H", automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock.
BASIC TIMER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X RESET or STOP Bit 1 Bits 3, 2 Basic Timer Control Register (Write '1010xxxxB' to Disable) Data Bus fXX/4096 Clear fXX/1024 fXX DIV fXX/128 MUX 8-Bit Up Counter (BTCNT, Read-Only) OVF fXX/16 u Start the CPU (note) Bit 0 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). Figure 10-2.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 11 TIMER 1 TIMER 1 ONE 16-BIT TIMER MODE (TIMER 1) The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7 is set to "1", timer 1 is used as a 16-bit timer. If TACON.7 is set to "0", timer 1 is used as two 8-bit timers. • One 16-bit timer mode (Timer 1) • Two 8-bit timers mode (Timer A and B) OVERVIEW The 16-bit timer 1 is a 16-bit general-purpose timer. Timer 1 has the interval timer mode by using the appropriate TACON setting.
TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Timer 1 Control Register (TACON) You use the timer 1 control register, TACON, to • Enable the timer 1 operating (interval timer) • Select the timer 1 input clock frequency • Clear the timer 1 counter, TACNT and TBCNT • Enable the timer 1 interrupt • Clear timer 1 interrupt pending conditions TACON is located in set 1, bank 1, at address E6H, and is read/write addressable using Register addressing mode. A reset clears TACON to "00H".
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BTCON.0 TIMER 1 TACON.6-.4 1/512 R TACON.3 Data Bus 1/256 TACON.2 fxx (XIN or XTIN) DIV 1/64 1/8 1/1 fxt M U LSB TBCNT MSB Clear TACNT R TACON.1 Match X 16-Bit Comparator TACON.0 T1CLK T1INT TAOUT LSB MSB TBDATA TADATA Buffer Buffer Match Signal T1CLR TBDATA TADATA Data Bus NOTE: When one 16-bit timer mode (TACON.7 <- "1": Timer 1) Figure 11-2.
TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TWO 8-BIT TIMERS MODE (TIMER A and B) OVERVIEW The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have the interval timer mode by using the appropriate TACON and TBCON setting, respectively.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X TIMER 1 TACON and TBCON are located in set 1, bank 1, at address E6H and E7H, and is read/write addressable using Register addressing mode. A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer A interrupt. You can clear the timer A counter at any time during normal operation by writing a "1" to TACON.3. A reset clears TBCON to "00H".
TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Timer B Control Register (TBCON) E7H, Set 1, Bank 1, R/W MSB .7 .6 .5 Not used for S3C8275X/C8278X/C8274X Timer B clock selection bits: 000 = fxx/512 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxt (sub clock) Others = Not available .4 .3 .2 .1 .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BTCON.0 R TIMER 1 TACON.6-.4 1/512 1/256 TACON.3 Data Bus TACON.2 fxx (XIN or XTIN) DIV 1/64 M 1/8 U 1/1 X LSB MSB TACNT (8-Bit Up-Counter) R TACON.1 Match 8-Bit Comparator fxt Clear TACON.0 T1CLK LSB TAINT TAOUT MSB TADATA Buffer Match Signal TACLR TADATA Register Data Bus NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer A) Figure 11-5.
TIMER 1 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BTCON.0 R TBCON.6-.4 1/512 1/256 fxx (XIN or XTIN) DIV 1/64 TBCON.3 Data Bus M U 1/8 TBCON.2 LSB MSB TBCNT (8-Bit Up-Counter) R X TBCON.1 Match 8-Bit Comparator fxt Clear LSB TBCON.0 TBINT TBOUT MSB TBDATA Buffer Match Signal TBCLR TBDATA Register Data Bus NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer B) Figure 11-6.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 12 WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1". And if you want to service watch timer overflow interrupt (IRQ 2, vector F6H), then set the WTCON.6 to "1". The watch timer overflow interrupt pending condition (WTCON.
WATCH TIMER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer function. It is located in set 1, bank 1 at address E1H, and is read/write addressable using Register addressing mode. A reset clears WTCON to "00H". This disable the watch timer and select fx/128 as the watch timer clock.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X WATCH TIMER WATCH TIMER CIRCUIT DIASGRAM WTCON.7 BUZ (P0.7) WT INT Enable WTCON.6 WTCON.6 WTCON.5 8 MUX WTCON.4 WTCON.3 WTCON.2 WTCON.1 WTINT fW/64 (0.5 kHz) fW/32 (1 kHz) fW/16 (2 kHz) fW/8 (4 kHz) Enable/Disable Selector Circuit WTCON.0 WTCON.0 (Pending Bit) Clock Selector fW 32.768 kHz Frequency Dividing Circuit fW/27 fW/213 fW/214 fW/215 (1 Hz) fLCD = 2048 Hz fxt fx/128 fX = Main clock (where fx = 4.19 MHz) fxt = Sub clock (32.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 13 LCD CONTROLLER/DRIVER LCD CONTROLLER/DRIVER OVERVIEW The S3C8275X/C8278X/C8274X microcontroller can directly drive an up-to-128-dot (32 segments x 4 commons) LCD panel.
LCD CONTROLLER/DRIVER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CIRCUIT DIAGRAM SEG31/P2.0 Port Latch SEG/Port Driver SEG16/P3.7 SEG15/P4.0 Data BUS SEG0/P5.7 LCD Display RAM (200H-20FH) fLCD COM/Port Driver COM3/P6.3 COM2/P6.2 COM0/P6.0 Timing Controller LCON LCD Voltage Controller Figure 13-2.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROLLER/DRIVER LCD RAM ADDRESS AREA RAM addresses of page 2 are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off.
LCD CONTROLLER/DRIVER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROL REGISTER (LCON) A LCON is located in set 1, bank 1, at address E0H, and is read/write addressable using Register addressing mode. It has the following control functions.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X LCD CONTROLLER/DRIVER LCD VOLTAGE DIVIDING RESISTOR Static and 1/3 Bias 1/2 Bias S3C8275X/C8278X/C8274X VDD S3C8275X/C8278X/C8274X VDD LCON.0 LCON.7 = 0: Enable internal resistors VLC0 VLC1 VLC2 R R LCON.0 VLC1 VLCD R LCON.7 = 0: Enable internal resistors VLC0 VLC2 R R VLCD R VSS VSS Voltage Dividing Resistor Adjustment S3C8275X/C8278X/C8274X VDD LCON.0 LCON.7 = 1: Disable internal resistors VLC0 R' R' VLC1 VLC2 VLCD R' VSS NOTES: 1.
LCD CONTROLLER/DRIVER S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X COMMON (COM) SIGNALS The common signal output pin selection (COM pin selection) varies according to the selected duty cycle. • In 1/4 duty mode, COM0-COM3 pins are selected • In 1/3 duty mode, COM0-COM2 pins are selected • In 1/2 duty mode, COM0-COM1 pins are selected SEGMENT (SEG) SIGNALS The 32 LCD segment signal pins are connected to corresponding display RAM locations at page 2.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Select LCD CONTROLLER/DRIVER Non-Select FR 1 Frame VLC 0 VLC1, 2 COM Vss VLC 0 VLC1, 2 SEG Vss VLC 0 VLC1, 2 COM-SEG Vss -VLC1, 2 -VLC 0 Figure 13-7. Select/No-Select Signal in 1/2 Duty, 1/2 Bias Display Mode Select Non-Select FR 1 Frame COM VLC0 VLC1 VLC2 VSS SEG VLC0 VLC1 VLC2 VSS VLC0 VLC1 VLC2 VSS -VLC2 -VLC1 -VLC0 COM-SEG Figure 13-8.
LCD CONTROLLER/DRIVER 3 SEG1.4 x C0 1 Frame Figure 13-9. LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode 13-8 SEG5 0 1 1 0 .4 .5 .6 .7 SEG4 Data Register page 4, address B2H LD B2H, #63h 1 1 0 0 SEG3 COM1 -SEG1 VLC0 VLC1 VLC2 VSS -VLC2 -VLC1 -VLC0 .0 .1 .2 .3 COM1 -SEG0 VLC0 VLC1 VLC2 VSS -VLC2 -VLC1 -VLC0 1 1 1 0 COM0 -SEG1 VLC0 VLC1 VLC2 VSS -VLC2 -VLC1 -VLC0 SEG2 COM0 -SEG0 VLC0 VLC1 VLC2 VSS -VLC2 -VLC1 -VLC0 .4 .5 .6 .
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 14 SERIAL I/O INTERFACE SERIAL I/O INTERFACE OVERVIEW Serial I/O modules, SIO can interface with various types of external device that require serial data transfer.
SERIAL I/O INTERFACE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SIO CONTROL REGISTERS (SIOCON) The control register for serial I/O interface module, SIOCON, is located at E1H in set 1, bank 0. It has the control setting for SIO module.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SERIAL I/O INTERFACE SIO PRE-SCALER REGISTER (SIOPS) The prescaler register for serial I/O interface module, SIOPS, is located at E3H in set 1, bank 0. The value stored in the SIO pre-scaler register, SIOPS, lets you determine the SIO clock rate (baud rate) as follows: Baud rate = Input clock (fxx/4)/(Prescaler value + 1), or SCK input clock. SIO Pre-scaler Register (SIOPS) E3H, Set 1, Bank 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .
SERIAL I/O INTERFACE S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X SERIAL I/O TIMING DIAGRAM (SIO) SCK SI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Transmit Complete SIO INT Set SIOCON.3 Figure 14-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0) SCK SI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Transmit Complete SIO INT Set SIOCON.3 Figure 14-5.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 15 BATTERY LEVEL DETECTOR BATTERY LEVEL DETECTOR OVERVIEW The S3C8275X/C8278X/C8274X micro-controller has a built-in BLD (Battery Level Detector) circuit which allows detection of power voltage drop or external input level through software. Turning the BLD operation on and off can be controlled by software. Because the IC consumes a large amount of current during BLD operation. It is recommended that the BLD operation should be kept OFF unless it is necessary.
BATTERY LEVEL DETECTOR S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X BATTERY LEVEL DETECTOR CONTROL REGISTER (BLDCON) The bit 3 of BLDCON controls to run or disable the operation of Battery Level Detector. Basically this VBLD is set as 2.2V by system reset and it can be changed in 3 kinds voltages by selecting Battery Level Detector Control Register (BLDCON). When you write 3-bit data value to BLDCON, an established resistor string is selected and the VBLD is fixed in accordance with this resistor.
S3F8275X 16 EMBEDDED FLASH MEMORY INTERFACE EMBEDDED FLASH MEMORY INTERFACE OVERVIEW This chapter is only for the S3F8275X. The S3F8275X has an on-chip full-flash memory internally instead of masked ROM. The flash memory is accessed by "LDC" instruction and the type of sector erase and a byte programmable flash, a user can program the data in the flash memory area any time you want.
EMBEDDED FLASH MEMORY INTERFACE S3F8275X USER PROGRAM MODE This mode supports sector erase, byte programming, byte read and one protection mode (Hard lock protection). The read protection mode is available only in Tool Program mode. So in order to make a chip into read protection, you need to select a read protection option when you program an initial your code to a chip by using Tool Program mode by using a programming tool. The S3F8275X has the pumping circuit internally. Therefore, 12.
S3F8275X EMBEDDED FLASH MEMORY INTERFACE Flash Memory User Programming Enable Register The FMUSR register is used for a safety operation of the flash memory. This register will protect undesired erase or program operation from malfunctioning of CPU caused by an electrical noise. After reset, the user-programming mode is disabled, because the value of FMUSR is "00000000B" by reset operation.
EMBEDDED FLASH MEMORY INTERFACE S3F8275X Flash Memory Sector Address Registers There are two sector address registers for addressing a sector to be erased. The FMSECL (Flash Memory Sector Address Register Low Byte) indicates the low byte of sector address and FMSECH (Flash Memory Sector Address Register High Byte) indicates the high byte of sector address. The FMSECH is needed for S3F8275X because it has 128 sectors, respectively. One sector consist of 128-bytes.
S3F8275X EMBEDDED FLASH MEMORY INTERFACE ISPTM (ON-BOARD PROGRAMMING) SECTOR ISPTM sectors located in program memory area can store on board program software (boot program code for upgrading application code by interfacing with I/O pin). The ISPTM sectors can not be erased or programmed by LDC instruction for the safety of On Board Program software. The ISP sectors are available only when the ISP enable/disable bit is set 0, that is, enable ISP at the Smart Option.
EMBEDDED FLASH MEMORY INTERFACE S3F8275X Table 16-1. ISP Sector Size Smart Option(003EH) ISP Size Selection Bit Area of ISP Sector ISP Sector Size Bit 2 Bit 1 Bit 0 1 x x − 0 0 0 0 100H – 1FFH (256 byte) 256 Bytes 0 0 1 100H – 2FFH (512 byte) 512 Bytes 0 1 0 100H – 4FFH (1024 byte) 1024 Bytes 0 1 1 100H – 8FFH (2048 byte) 2048 Bytes NOTE: The area of the ISP sector selected by Smart Option bit (003EH.2 − 003EH.
S3F8275X EMBEDDED FLASH MEMORY INTERFACE SECTOR ERASE User can erase a flash memory partially by using sector erase function only in User Program Mode. The only unit of flash memory to be erased and programmed in User Program Mode is called sector. The program memory of S3F8275X is divided into 128 sectors for unit of erase and programming. Every sector has all 128-byte sizes of program memory areas. So each sector should be erased first to program a new data (byte) into a sector.
EMBEDDED FLASH MEMORY INTERFACE S3F8275X The Sector Erase Procedure in User Program Mode 1. Set Flash Memory User Programming Enable Register (FMUSR) to "10100101B". 2. Set Flash Memory Sector Address Register (FMSECH/FMSECL). 3. Check user’s ID code (written by user). 4. Set Flash Memory Control Register (FMCON) to "10100001B". 5. Set Flash Memory User Programming Enable Register (FMUSR) to "00000000B" 6. Check the "sector erase status bit" whether "sector erase" is success or not.
S3F8275X EMBEDDED FLASH MEMORY INTERFACE PROGRAMMING A flash memory is programmed in one byte unit after sector erase. And for programming safety's sake, must set FMSECH and FMSECL to flash memory sector value. The write operation of programming starts by 'LDC' instruction. You can write until 128byte, because this flash sector's limits is 128byte. So if you written 128byte, must reset FMSECH and FMSECL. The Program Procedure in User program Mode 1. Must erase sector before programming. 2.
EMBEDDED FLASH MEMORY INTERFACE S3F8275X PROGRAMMING TIP ⎯ Program • • SB1 LD LD LD LD LD LD CP JR LD LDC NOP LD FMUSR,#0A5H ; User Program mode enable FMSECH,#17H FMSECL,#80H ; Set sector address (1780H−17FFH) R2,#17H ; Set a ROM address in the same sector 1780H−17FFH R3,#84H R4,#78H ; Temporary data UserID_Code,#User_value ; Check user’s ID code (written by user) ; User_value is any value by user NE,Not_ID_Code ; If not equal, jump to Not_ID_Code FMCON,#01010001B ; Start program @RR2,R4 ; Write the da
S3F8275X EMBEDDED FLASH MEMORY INTERFACE READING The read operation of programming starts by 'LDC' instruction. The Reading Procedure in User Program Mode 1. Load a flash memory upper address into upper register of pair working register. 2. Load a flash memory lower address into lower register of pair working register. 3. Load receive data from flash memory location area on 'LDC' instruction by indirectly addressing mode.
EMBEDDED FLASH MEMORY INTERFACE S3F8275X HARD LOCK PROTECTION User can set Hard Lock Protection by write ‘0110’ in FMCON.7−4. If this function is enabled, the user cannot write or erase the data in a flash memory area. This protection can be released by the chip erase execution (in the tool program mode). In terms of user program mode, the procedure of setting Hard Lock Protection is following that. Whereas in tool mode the manufacturer of serial tool writer could support Hardware Protection.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 17 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter, S3C8275X/C8278X/C8274X electrical characteristics are presented in tables and graphs. The information is arranged in the following order: • Absolute maximum ratings • D.C. electrical characteristics • Data retention supply voltage in Stop mode • Stop mode release timing when initiated by an external interrupt • Stop mode release timing when initiated by a RESET • I/O capacitance • A.C.
ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 17-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions VDD − Supply voltage Input voltage VI Output voltage VO Output current High I OH I OL Output current Low Operating temperature Storage temperature Rating − 0.3 Ports 0–6 − Unit to + 4.6 V − 0.3 to VDD + 0.3 V − 0.3 to V VDD + 0.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA Table 17-2. D.C. Electrical Characteristics (Continued) (TA = − 25°C Parameter to + 85°C, VDD = Symbol 2.0 V to 3.
ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 17-2. D.C. Electrical Characteristics (Concluded) (TA = − 25°C to + 85°C, VDD = Parameter Symbol Supply current (1) IDD1(2) IDD2(2) 2.0 V to 3.6 V) Conditions Min Typ Max Unit − 3.0 6.0 mA Run mode: VDD = 3.3 V ± 0.3 V 8.0 MHz Crystal oscillator C1 = C2 = 22pF 4.0 MHz 1.5 3.0 Idle mode: VDD = 3.3 V ± 0.3 V 8.0 MHz 0.5 1.6 Crystal oscillator C1 = C2 = 22pF 4.0 MHz 0.4 1.2 IDD3(3) Run mode: VDD = 3.3 V ± 0.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA Table 17-3. Data Retention Supply Voltage in Stop Mode (TA = − 25 °C to Parameter + 85 °C) Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR − 2.0 − 3.6 V Data retention supply current IDDDR − − 1 µA Stop mode, TA = 25 °C VDDDR = 2.0 V Disable LVR block Idle Mode (Basic Timer Active) ~ ~ Stop Mode Normal Operating Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instruction 0.
ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Oscillation Stabilization TIme RESET Occurs ~ ~ Stop Mode Normal Operating Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instrction nRESET 0.8 VDD 0.2 VDD NOTE: tWAIT tWAIT is the same as 16 × 1/BT clock. Figure 17-2. Stop Mode Release Timing When Initiated by a RESET Table 17-4.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA Table 17-5. A.C. Electrical Characteristics (TA = − 25°C to + 85°C, VDD = 2.0 V Parameter to Symbol tKCY SCK cycle time tKH, tKL SCK high, low width tSIK SI setup time to SCK high tKSI SI hold time to SCK high tKSO Output delay for SCK to SO 3.
ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X tRSL nRESET 0.2 VDD Figure 17-4. Input Timing for RESET tKCY tKL tKH SCK 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI 0.2VDD tKSO SO Output Data Figure 17-5.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA Table 17-6. Battery Level Detector Electrical Characteristics (TA = 25°C, VDD = 2.0 V Parameter Operating voltage of BLD to 3.6 V) Symbol Conditions Min Typ Max Unit VDDBLD − 2.0 − 3.6 V BLDCON.2-.0 = 000b 2.0 2.2 2.4 BLDCON.2-.0 = 101b 2.15 2.4 2.65 BLDCON.2-.0 = 011b 2.5 2.8 3.1 VDD = 3.3 V − 70 120 VDD = 2.
ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 17-8. Main Oscillation Characteristics (TA = − 25°C Oscillator to + 85°C) Clock Configuration Crystal C1 XIN Parameter Main oscillation frequency Test Condition Min Typ Max Units 2.5 V − 3.6 V 0.4 − 8 MHz 2.0 V − 3.6 V 0.4 − 4.2 2.5 V − 3.6 V 0.4 − 8 2.0 V − 3.6 V 0.4 − 4.2 2.5 V − 3.6 V 0.4 − 8 2.0 V − 3.6 V 0.4 − 4.2 3.3 V 0.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA Table 17-10. Main Oscillation Stabilization Time (TA − 25 °C = to + 85 °C, VDD = 2.0 V Oscillator to 3.6 V) Test Condition Min Typ Max Unit Crystal fx > 1 MHz − − 40 ms Ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. − − 10 ms External clock XIN input high and low width (tXH, tXL) 62.5 − 1250 ns 1/fx tXL tX XIN VDD-0.1 V 0.1 V Figure 17-7.
ELECTRICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 17-11. Sub Oscillation Stabilization Time (TA − 25 °C = Oscillator to + 85 °C, VDD = 2.0 V to Test Condition Min Typ Max Unit – − − 10 s 5 − 15 µs Crystal External clock 3.6 V) XTIN input high and low width (tXH, tXL) 1/fxt tXTL tXTH XTIN VDD-0.1 V 0.1 V Figure 17-8.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X ELECTRICAL DATA Instruction Clock fx (Main/Sub oscillation frequency) 8 MHz 2 MHz 1.05 MHz 4.2 MHz 6.25 kHz(main)/8.2 kHz(sub) 400 kHz (main)/32.8 kHz(sub) 1 2 3 2.5 3.6 4 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) Figure 17-9. Operating Voltage Range Table 17-12. A.C. Electrical Characteristics for Internal Flash ROM (TA = − 25 °C to + 85 °C, VDD = 2.2 V Parameter to 3.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 18 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C8275X/C8278X/C8274X microcontroller is currently available in a 64-pin QFP and LQFP package. 23.90 ± 0.30 0-8 20.00 ± 0.20 14.00 ± 0.20 + 0.10 - 0.05 0.10 MAX 64-QFP-1420F 0.80 ± 0.20 17.90 ± 0.30 0.15 #64 #1 1.00 + 0.10 0.40 - 0.05 0.15 MAX 0.05 MIN (1.00) 2.65 ± 0.10 3.00 MAX 0.80 + 0.20 NOTE: Dimensions are in millimeters. Figure 18-1.
MECHANICAL DATA S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 12.00 BSC 10.00 BSC 0-7 10.00 BSC 0.08 MAX 64-LQFP-1010 0.45~0.75 12.00 BSC 0.09~0.20 #64 #1 0.20 + 0.07 - 0.03 0.50 BSC 0.10 ± 0.05 1.40 ± 0.05 1.60 MAX NOTE: Dimensions are in millimeters. Figure 18-2.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 19 S3F8275X/F8278X/F8274X FLASH MCU S3F8275X/F8278X/F8274X FLASH MCU OVERVIEW The S3F8275X/F8278X/F8274X single-chip CMOS microcontroller is the Flash MCU version of the S3C8275X/C8278X/C8274X microcontroller. It has an on-chip Flash ROM instead of masked ROM. The Flash ROM is accessed by serial data format. The S3F8275X/F8278X/F8274X is fully compatible with the S3C8275X/C8278X/C8274X, both in function and in pin configuration.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 64 63 62 61 60 59 58 57 56 55 54 53 52 SEG1/P5.6 SEG2/P5.5 SEG3/P5.4 SEG4/P5.3 SEG5/P5.2 SEG6/P5.1 SEG7/P5.0 SEG8/P4.7 SEG9/P4.6 SEG10/P4.5 SEG11/P4.4 SEG12/P4.3 SEG13/P4.2 S3F8275X/F8278X/F8274X FLASH MCU 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 S3F8275X S3F8278X S3F8274X (64-QFP-1420F) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG14/P4.1 SEG15/P4.0 SEG16/P3.7 SEG17/P3.6 SEG18/P3.5 SEG19/P3.4 SEG20/P3.3 SEG21/P3.2 SEG22/P3.1 SEG23/P3.
S3F8275X/F8278X/F8274X FLASH MCU 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SEG1/P5.6 SEG2/P5.5 SEG3/P5.4 SEG4/P5.3 SEG5/P5.2 SEG6/P5.1 SEG7/P5.0 SEG8/P4.7 SEG9/P4.6 SEG10/P4.5 SEG11/P4.4 SEG12/P4.3 SEG13/P4.2 SEG14/P4.1 SEG15/P4.0 SEG16/P3.7 S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S3F8275X S3F8278X S3F8274X (64-LQFP-1010) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG17/P3.6 SEG18/P3.5 SEG19/P3.4 SEG20/P3.3 SEG21/P3.2 SEG22/P3.1 SEG23/P3.
S3F8275X/F8278X/F8274X FLASH MCU S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 19-1. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function VLC1 SDAT 7 I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as an Input or push-pull output port. VLC2 SCLK 8 I/O Serial clock pin. Input only pin. TEST VPP 13 I S3F8278X/F8274X: Power supply pin for Flash ROM cell reading/writing. 12.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X S3F8275X/F8278X/F8274X FLASH MCU OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3F8275X/F8278X/F8274X, the Flash ROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 19-3 below. Table 19-3. Operating Mode Selection Criteria VDD VPP (TEST) REG/MEM Address (A15-A0) R/W 3.3 V 3.3 V 0 0000H 1 Flash ROM read 12.
S3F8275X/F8278X/F8274X FLASH MCU S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 19-4. D.C. Electrical Characteristics (TA = − 25°C to + 85°C, VDD = Parameter Symbol Supply current (1) IDD1 (2) IDD2 (2) 2.0 V to 3.6 V) Min Typ Max Unit − 3.0 6.0 mA 4.0 MHz 1.5 3.0 8.0 MHz 0.5 1.6 4.0 MHz 0.4 1.2 Conditions Run mode: VDD = 3.3 V ± 0.3 V Crystal oscillator C1 = C2 = 22pF Idle mode: VDD = 3.3 V ± 0.3 V Crystal oscillator C1 = C2 = 22pF 8.0 MHz IDD3 (3) Run mode: VDD = 3.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X S3F8275X/F8278X/F8274X FLASH MCU Instruction Clock fx (Main/Sub oscillation frequency) 2 MHz 8 MHz 1.05 MHz 4.2 MHz 6.25 kHz (main)/8.2 kHz(sub) 400 kHz(main)/32.8 kHz(sub) 1 2 2.5 3 3.6 4 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) Figure 19-3.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X 20 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use development support system in turnkey form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS, Windows 95, and 98 as its operating system can be used.
DEVELOPMENT TOOLS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X IBM-PC AT or Compatible RS-232C SMDS2+ Target Application System PROM/OTP Writer Unit RAM Break/Display Unit BUS Probe Adapter Trace/Timer Unit SAM8 Base Unit Power Supply Unit POD TB8275/8/4 Target Board EVA Chip Figure 20-1.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DEVELOPMENT TOOLS TB8275/8/4 TARGET BOARD The TB8275/8/4 target board is used for the S3C8275X/C8278X/C8274X microcontroller. It is supported with the SMDS2+.
DEVELOPMENT TOOLS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 20-1. Power Selection Settings for TB8275/8/4 "To User_Vcc" Settings Operating Mode TB8275 TB8278 TB8274 To User_V CC Off On Comments Target System VSS VCC The SMDS2/SMDS2+ supplies VCC to the target board (evaluation chip) and the target system. VCC SMDS2/SMDS2+ TB8275 TB8278 TB8274 To User_V CC Off On External VCC Target System VSS The SMDS2/SMDS2+ supplies VCC only to the target board (evaluation chip).
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DEVELOPMENT TOOLS Table 20-3. Select Smart Option Source Setting for TB8275/8/4 "Smart Option Source" Settings Operating Mode Select Smart Option Source Internal TB8275/8/4 External Select Smart Option Source Internal TB8275/8/4 External Comments Target System Target System The Smart Option is selected by external smart option switch (SW1) The Smart Option is selected by internal smart option area (003EH–003FH of ROM).
DEVELOPMENT TOOLS S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Table 20-5.
S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X DEVELOPMENT TOOLS J101 P6.0/COM0 P6.2/COM2 VLC0 VLC2 VSS N.C N.C nRESET P0.0/INT0 P0.2/INT2 P0.4/TAOUT P0.6/CLKOUT P1.0/SCK P1.2/SI P1.4/INT4 P1.6/INT6 N.C N.C N.C N.C 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 INT7/P1.7 SEG30/P2.1 SEG28/P2.3 SEG26/P2.5 SEG24/P2.7 SEG22/P3.1 SEG20/P3.3 SEG18/P3.5 SEG16/P3.7 SEG14/P4.1 SEG12/P4.3 SEG10/P4.5 SEG8/P4.7 SEG6/P5.1 SEG4/P5.3 SEG2/P5.5 N.C N.C N.C N.