Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1053 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.5.5 Serial Data Reception (Clock Synchronous Mode)
Figure 33.29 and Figure 33.30 show an example of SCI operation for serial reception in clock synchronous mode.
In serial data reception, the SCI operates as described below.
1. The value of the SCR.RE bit becoming 1 places the signal output on the RTSn# pin at the low level (when the RTS
function is in use).
2. The SCI performs internal initialization and starts receiving data in synchronization with a synchronization clock
input or output, and stores the receive data in the RSR register.
3. If an overrun error occurs, the SSR.ORER flag is set to 1. If the SCR.RIE bit is 1 at this time, an ERI interrupt
request is generated. Receive data is not transferred to the RDR register.
4. When reception finishes successfully, receive data is transferred to the RDR register. If the SCR.RIE bit is 1 at this
time, an RXI interrupt request is generated. Continuous reception is enabled by reading the receive data transferred
to the RDR register in this RXI interrupt handling routine before reception of the next receive data is completed.
Reading out the received data that have been transferred to the RDR register causes the RTSn# pin to output the low
level (when the RTS function is in use).
Figure 33.29 Example of Operation for Serial Reception in Clock Synchronous Mode (1)
(When RTS Function is Not Used)
1 frame
RXI interrupt flag
(IRn in ICU*
1
)
SSR.ORER flag
Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 7Bit 6
RDR data read in RXI
interrupt handling routine
RXI interrupt
request
generated
RXI interrupt
request
generated
ERI interrupt request
generated by overrun error
Synchronization
clock
Serial data
Note 1. Refer to section 15, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number.