User Manual

W9864G6GB
Publication Release Date: August 14, 2006
- 5 - Revision A01
5. PIN DESCRIPTION
BALL LOCATION PIN NAME FUNCTION DESCRIPTION
M1,M2,N1,N2,N6,
N7,P1,P2,P6,P7,
R6,
A0−A11
Address
Multiplexed pins for row and column address.
Row address: A0−A11. Column address: A0−A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or
bank selected by BS0, BS1.
M6,M7
BS0, BS1 Bank Select
Select bank to activate during row address latch
time, or bank to read/write during address latch
time.
A2,A6,B1,B7,C1,C7
,D1,D2,D6,D7,E1,E
7,F1,F7,G1,G7
DQ0−DQ15
Data Input/
Output
Multiplexed pins for data output and input.
L7
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
K6
RAS
Row Address
Strobe
Command input. When sampled at the rising edge
of the clock
RAS
,
CAS
and
WE
define the
operation to be executed.
K7
CAS
Column
Address
Strobe
Referred to
RAS
J7
WE
Write Enable
Referred to
RAS
J2,J6
UDQM
LDQM
Input/output
mask
The output buffer is placed at Hi-Z (with latency of
2) when DQM is sampled high in read cycle. In
write cycle, sampling DQM high will block the
write operation with zero latency.
K2 CLK Clock Inputs
System clock used to sample inputs on the rising
edge of clock.
L1 CKE Clock Enable
CKE controls the clock activation and
deactivation. When CKE is low, Power Down
mode, Suspend mode, or Self Refresh mode is
entered.
A7,H6,R7 VDD
Power
(+3.3V)
Power for input buffers and logic circuit inside
DRAM.
A1,H2,R1 VSS Ground
Ground for input buffers and logic circuit inside
DRAM.
B6,C2,E6,F2 VDDQ
Power
(+3.3V) for I/O
buffer
Separated power from VDD, to improve DQ noise
immunity.
B2,C6,E2,F6 VSSQ
Ground for I/O
buffer
Separated ground from V
SS, to improve DQ noise
immunity.
G2,G6,H1,H7,J1,K1
,L2,L6
NC
No
Connection
No connection