User guide

BR24L04-W / BR24L04F-W / BR24L04FJ-W
Memory ICs BR24L04FV-W / BR24L04FVM-W
10/25
zByte write
SDA
LINE
WP
S
T
A
R
T
SLAVE
ADDRESS
10 01
R
/
W
W
R
I
T
E
A
C
K
A
C
K
D7
DATA
D0
S
T
O
P
Fig.8 BYTE WRITE CYCLE TIMING
A
C
K
WORD
ADDRESS
WA
0
WA
7
PSA1A2
• By using this command, the data is programmed into the indicated word address.
• When the master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory
array.
zPage write
Fig.9 PAGE WRITE CYCLE TIMING
SDA
LINE
WP
SLAVE
ADDRESS
10 01
R
/
W
A
C
K
A
C
K
A
C
K
D7
DATA (n)
D0
DATA (n+15)
D0
WORD
ADDRESS (n)
A
C
K
WA
0
WA
7
PSA1A2
S
T
A
R
T
W
R
I
T
E
S
T
O
P
• This device is capable of sixteen byte Page Write operation.
• When two or more byte data are inputted, the four low order address bits are internally incremented by one after the
receipt of each word. The five higher order bits of the address (PS WA7 to WA4) remain constant.
• If the master transmits more than sixteen words, prior to generating the STOP condition, the address counter will
“roll over”, and the previous transmitted data will be overwritten.