User's Manual

Page 15
SVR-200 Service Manual
P1.5 Serial clock line output. Serial data that is sent to the PLL, the E²PROM and the audio processor chips
are clocked by each low-high-low transition on this line.
P1.6 Serial data output. Data sent to U10, U4 and U5 are output on this line and clocked by P1.5.
P1.7 Data input to the microprocessor. Serial data is read from U10 (E²PROM) and U5 (sub-audio
processor) on this line.
P2.0 Lock tone output. Lock tone encode is generated by this pin at power up and during lock tone test mode.
All of the queuing tones are also generated by this pin for trunking operation.
P2.1 Lock tone decode input, active high. The output of lock tone decoder U3D is input on this line and
checked during receiver activity. If lock tone is detected, the microprocessor increments its priority
counter and ceases activity as priority unit.
P2.2 Repeater Tx enable. This line is used to turn on the TX 9V signal to the RF PCB. The output drives
buffers Q7 and Q6. The output of Q6 switches Q4 on during transmit for TX 9V. RV10 and APC
circuit U13 are used to set the TX 9V level for RF power control.
P2.3 Mobile PTT output, active low. This line is brought low to key the mobile radio during portable-to-base
repeat operations.
P2.4 Mobile COR input. U1A is a threshold detector for the mobile COR input on pin 7 of P1. The output
of U1A is read by the microprocessor on this port to determine if the SVR-200 should repeat base to
portable. Polarity of this input is determined by PC programming.
P2.5 Repeater COR input, active low. RSSI output from the RF module is sent to threshold detector U2D
for comparison with the squelch setting at RV9. R47 and R70 provide hysteresis to prevent chatter.
Repeater COR is used to enable the CTCSS decoder circuitry; the microprocessor will not decode
the signal from U5 unless repeater COR is also active.
P2.6 Chip select output for U4 (audio processor), active low. Serial data is sent to U4 on P1.6 and clocked
by P1.5. These lines are shared by U5, U10 and the PLL; data is ignored by U4 unless the chip select
line is asserted during data write operations.
P2.7 Chip select output for U5 (sub-audio processor), active low. Serial data is sent to U5 on P1.6 and
clocked by P1.5. These lines are shared by U4, U10 and the PLL; data is ignored by U5 unless the
chip select line is asserted during data read and write operations.
INT0 External interrupt #0. This line monitors the PLL lock detector output. The line is active high to indicate
the PLL is functioning on frequency during transmit-receive and receive to transmit changes. The
output will go briefly unlocked, then revert back to a locked condition. If the PLL does not achieve
lock within 50mS, the transmitter will be disabled and the OPT LED will flash rapidly to alert the user
that the unit should be brought in for service.
INT1 External interrupt #1 active low. This line is used by U5 to signal the microprocessor that it has
completed a decode cycle and data can be read. During receiver activity, this line will go active
approximately every 122 mS in the presence of sub-audio signalling. During transmit mode and
receiver activity without sub-audio signalling, this line will be inactive.