Datasheet ADS1015

SCL
SDA
t
LOW
t
R
t
F
t
HDSTA
t
HDSTA
t
HDDAT
t
BUF
t
SUDAT
t
HIGH
t
SUSTA
t
SUSTO
P S S P
8
ADS1013 , ADS1014 , ADS1015
SBAS473E –MAY 2009–REVISED JANUARY 2018 www.ti.com
Product Folder Links: ADS1013 ADS1014 ADS1015
Submit Documentation Feedback Copyright © 2009–2018, Texas Instruments Incorporated
(1) For high-speed mode maximum values, the capacitive load on the bus line must not exceed 400 pF.
7.6 Timing Requirements: I
2
C
over operating ambient temperature range and VDD = 2.0 V to 5.5 V (unless otherwise noted)
FAST MODE HIGH-SPEED MODE
UNITMIN MAX MIN MAX
f
SCL
SCL Clock Frequency 0.01 0.4 0.01 3.4 MHz
t
BUF
Bus free time between START and STOP
condition
600 160 ns
t
HDSTA
Hold time after repeated START condition.
After this period, the first clock is generated.
600 160 ns
t
SUSTA
Setup time for a repeated START condition 600 160 ns
t
SUSTO
Setup time for STOP condition 600 160 ns
t
HDDAT
Data hold time 0 0 ns
t
SUDAT
Data setup time 100 10 ns
t
LOW
Low period of the SCL clock pin 1300 160 ns
t
HIGH
High period for the SCL clock pin 600 60 ns
t
F
Rise time for both SDA and SCL signals
(1)
300 160 ns
t
R
Fall time for both SDA and SCL signals
(1)
300 160 ns
Figure 1. I
2
C Interface Timing