User Manual

AND9932/D
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13
The waveform shown in Figure 16 is a result of driving
two HEMT, GIT, 600 V, 26 A, 56 mW GaNFETs which have
higher current capability compared to the devices used in
Figure 15. To achieve high dV/dt, a significant amount of
drain current, I
D
is required. For example, the measurement
shown is taken at I
D
= 20 A
PK
resulting in a measured V
DS
,
dV/dt = 75 V/ns. The triangular, peak inductor current
appears as DC only because of the time base (2 ns/div)
necessary to make this measurement. The 100 V undershoot
of the VSW waveform is the result of the measurement
technique used to show the high dV/dt and is not actually
present on the switch node.
CONCLUSION
The successful adoption of wide band gap
semiconductors demands a greater awareness of the
negative effects parasitic inductance and capacitance have
in any high voltage, high frequency, PCB design.
A thorough understanding of the importance of electrical
return planes, shielding, current separation, isolation and
careful routing are essential for deriving the maximum
performance benefits offered from GaN technology. This
paper has highlighted the most important PCB design
guidelines that must be adopted for achieving a successful
design using the NCP51820 for driving GaN power switches
used in high−speed power topologies. These techniques
have been validated with measured waveforms and shown
to produce excellent results.
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