Datasheet

SA56004X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 25 February 2013 10 of 43
NXP Semiconductors
SA56004X
Digital temperature sensor with overtemperature alarms
7.8 SA56004X SMBus registers
7.8.1 Command register
The command register selects which register will be read or written to. Data for this
register should be transmitted during the Command Byte of the SMBus write
communication.
7.8.2 Local and remote temperature registers (LTHB, LTLB, RTHB, RTLB)
7.8.3 Configuration register (CON)
The configuration register is an 8-bit register with read address 03h and write address
09h. Table 8
shows how the bits in this register are used.
Table 6. Temperature data format
Temperature Digital output
Binary Hexadecimal
+125 C 0111 1101 0000 0000 7D00h
+25 C 0001 1001 0000 0000 1900h
+1 C 0000 0001 0000 0000 0100h
+0.125 C 0000 0000 0010 0000 0020h
0 C 0000 0000 0000 0000 0000h
0.125 C 1111 1111 1110 0000 FFE0h
1 C 1111 1111 0000 0000 FF00h
25 C 1110 0111 0000 0000 E700h
55 C 1100 1001 0000 0000 C900h
Table 7. LTHB, LTLB, RTHB, RTLB - Local and remote temperature registers
Byte High byte (read only; address 00h, 01h) Low byte (read only; address 10h)
Bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Valuesign64321684210.50.250.12500000
Table 8. CON - Configuration register (read address 03h; write address 09h)
bit assignments
Bit Description POR state
7ALERT
mask.
The ALERT interrupt is enabled when this bit is LOW. The ALERT interrupt
is disabled (masked) when this bit is HIGH.
0
6 RUN
/STOP.
Standby or run mode control. Running mode is enabled when this bit is
LOW. The SA56004X is in standby mode when this bit is HIGH.
0
5 Not defined; defaults to logic 0. 0
4 Remote T_CRIT
mask.
The T_CRIT
output will be activated by a remote temperature that exceeds
the remote T_CRIT setpoint when this bit is LOW. The T_CRIT output
will not be activated under this condition when this bit is HIGH.
0
3 Not defined; defaults to logic 0. 0