PCA9665 Fm+ parallel bus to I2C-bus controller Rev. 02 — 7 December 2006 Product data sheet 1. General description The PCA9665 serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial I2C-bus and allows the parallel bus system to communicate bidirectionally with the I2C-bus. The PCA9665 can operate as a master or a slave and can be a transmitter or receiver.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 3. Applications n Add I2C-bus port to controllers/processors that do not have one n Add additional I2C-bus ports to controllers/processors that need multiple I2C-bus ports n Converts 8 bits of parallel data to serial data stream to prevent having to run a large number of traces across the entire printed-circuit board 4. Ordering information Table 1.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 5.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 6. Pinning information 6.1 Pinning D0 1 1 20 VDD 2 20 VDD 19 SDA D0 D1 D1 2 19 SDA D2 3 18 SCL D2 3 18 SCL D3 4 17 RESET D3 4 17 RESET D4 5 16 INT D4 5 D5 6 15 A1 D5 6 D6 7 14 A0 D6 7 14 A0 D7 8 13 CE D7 8 13 CE i.c. 9 12 RD i.c.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 6.2 Pin description Table 2. Pin description Symbol Pin Type Description Data bus: Bidirectional 3-state data bus used to transfer commands, data and status between the bus controller and the CPU. D0 is the least significant bit. DIP20, SO20, TSSOP20 HVQFN20 D0 1 18 I/O D1 2 19 I/O D2 3 20 I/O D3 4 1 I/O D4 5 2 I/O D5 6 3 I/O D6 7 4 I/O D7 8 5 I/O i.c.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 7. Functional description 7.1 General The PCA9665 acts as an interface device between standard high-speed parallel buses and the serial I2C-bus. On the I2C-bus, it can act either as a master or slave. Bidirectional data transfer between the I2C-bus and the parallel-bus microcontroller is carried out on a byte or buffered basis, using either an interrupt or polled handshake. 7.2 Internal oscillator The PCA9665 contains an internal 28.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Table 4.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 7.3.1 Direct registers 7.3.1.1 The Status register, I2CSTA (A1 = 0, A0 = 0) I2CSTA is an 8-bit read-only register. The two least significant bits are always zero. The six most significant bits contain the status code. There are 30 possible status codes. When I2CSTA contains F8h, it indicates the idle state and therefore no serial interrupt is requested. All other I2CSTA values correspond to defined states.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller In Byte mode, the CPU can read or write a single byte at a time. In Buffered mode, the CPU can read or write up to 68 bytes at a time. See Section 8.1 “Configuration modes” for more detail. Remark: The I2CDAT register will capture the serial address as data when addressed via the serial bus.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Table 12. I2CCON - Control register (A1 = 1, A0 = 1) bit description Bit Symbol Description 7 AA The Assert Acknowledge flag. AA = 1: If the AA flag is set, an acknowledge (LOW level on SDA) will be returned during the acknowledge clock pulse on the SCL line when: • • ‘Own slave address’ has been received (as defined in I2CADR register).
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Table 12. I2CCON - Control register (A1 = 1, A0 = 1) bit description …continued Bit Symbol Description 5 STA The START flag. STA = 1: When the STA bit is set to enter a master mode, the bus controller hardware checks the status of the I2C-bus and generates a START condition if the bus is free.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 7.3.2 Indirect registers 7.3.2.1 The Byte Count register, I2CCOUNT (indirect address 00h) The I2CCOUNT register is an 8-bit read/write register. It contains the number of bytes that have been stored in Master/Slave Buffered Receiver mode, and the number of bytes to be sent in Master/Slave Buffered Transmitter mode. Bit 7 is the last byte control bit and applies to the Master/Slave Buffered Receiver mode only.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 7.3.2.3 The Clock Rate registers, I2CSCLL and I2CSCLH (indirect addresses 02h and 03h) I2CSCLL and I2CSCLH are 8-bit read/write registers. They define the data rate for the PCA9665 when used as a bus master. The actual frequency is determined by tHIGH (time where SCL is HIGH), tLOW (time where SCL is LOW), tr (rise time), and tf (fall time) values.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 7.3.2.4 The Time-out register, I2CTO (indirect address 04h) I2CTO is an 8-bit read/write register. It is used to determine the maximum time that SCL is allowed to be in a LOW logic state before the I2C-bus state machine is reset or the PCA9665 initiates a forced action on the I2C-bus. When the I2C-bus interface is operating, I2CTO is loaded in the time-out counter at every LOW SCL transition. Table 21.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 7.3.2.6 The I2C-bus mode register, I2CMODE (indirect address 06h) I2CMODE is an 8-bit read/write register. It contains the control bits that select the correct timing parameters when the device is used in master mode (AC[1:0]). Timing parameters involved with AC[1:0] are tBUF, tHD;STA, tSU;STA, tSU;STO, tHIGH, tLOW. Table 23.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 8. PCA9665 modes 8.1 Configuration modes Byte mode and Buffered mode are selected using the MODE bit in I2CCON register: MODE = 0: Byte mode MODE = 1: Buffered mode 8.1.1 Byte mode The Byte mode allows communication on a single command basis. Only one specific command is executed at a time and the Status Register is updated once this single command has been performed. A command can be a START, a STOP, a Byte Write, a Byte Read, and so on.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller P — STOP condition In Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13 and Figure 14, circles are used to indicate when the serial interrupt flag is set. A serial interrupt is not generated when I2CSTA = F8h. This happens on a STOP condition or when an external reset is generated (at power-up, when RESET pin is going LOW or during a software reset on the parallel bus).
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller • B0h if the PCA9665 lost the arbitration and is addressed as a slave transmitter (slave mode enabled with AA = 1) • 68h if the PCA9665 lost the arbitration and is addressed as a slave receiver (slave mode enabled with AA = 1) • D8h if the PCA9665 lost the arbitration and is addressed as a slave receiver during a General Call sequence (slave mode enabled with AA = 1 and General Call address enabled with GC = 1 in I2CADR register) The app
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller MT successful transmission to a Slave Receiver S SLA 08h W A DATA 18h A P 28h F8h (2) next transfer started with a repeated START condition S SLA W 10h Not Acknowledge received after the slave address A P 20h F8h R Not Acknowledge received after a data byte A P 30h F8h to Master Receiver mode entry = MR(4) (3) arbitration lost in slave address or data byte A or A other MST continues A or A 38h arbitratio
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Table 27.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Table 27.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 8.3.2 Master Receiver Byte mode In the Master Receiver Byte mode, a number of data bytes are received from a slave transmitter one byte at a time (see Figure 8). The transfer is initialized as in the Master Transmitter Byte mode. The Master Receiver Byte mode may now be entered by setting the STA bit. The I2C-bus state machine will first test the I2C-bus and generate a START condition as soon as the bus becomes free.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller MR successful reception from a Slave Transmitter S SLA 08h R A DATA 40h A DATA A P 50h 58h F8h (2) (3) next transfer started with a repeated START condition S SLA R 10h Not Acknowledge received after the slave address A P 48h F8h W to Master Transmitter mode entry = MT(4) arbitration lost in slave address or Acknowledge bit A or A other MST continues 38h arbitration lost and addressed as slave from master t
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Table 28.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 8.3.3 Slave Receiver Byte mode In the Slave Receiver Byte mode, a number of data bytes are received from a master transmitter one byte at a time (see Figure 9). To initiate the Slave Receiver mode, I2CADR and I2CCON must be loaded as shown in Table 29 and Table 30. Table 29.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller reception of own slave address and one or more data bytes; all are Acknowledged.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Table 31.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Table 31.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 8.3.4 Slave Transmitter Byte mode In the Slave Transmitter Byte mode, a number of data bytes are transmitted to a master receiver one byte at a time (see Figure 10). Data transfer is initialized as in the Slave Receiver Byte mode.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Table 32.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 8.4 Buffered mode 8.4.1 Master Transmitter Buffered mode In the Master Transmitter Buffered mode, a number of data bytes are transmitted to a slave receiver several bytes at a time (see Figure 11). Before the Master Transmitter Buffered mode can be entered, I2CCON must be initialized as shown in Table 33. Table 33. Bit Symbol Value Table 34.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller • 30h if the slave address with direction bit has been successfully sent and no acknowledgement (NACK) has been received while transmitting the data bytes (number of total bytes sent is lower than or equal to value in I2CCOUNT). • 38h if the PCA9665 lost the arbitration when sending the slave address with the direction bit or when sending data bytes.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller MT successful transmission to a Slave Receiver S SLA 08h W A A P 18h 28h F8h (2) (3) DATA next transfer started with a repeated START condition S SLA W 10h Not Acknowledge received after the slave address A P 20h F8h R Not Acknowledge received after a data byte A P 30h F8h to MST/REC mode entry = MR(5) (4) arbitration lost in slave address or data byte A or A other MST continues A or A 38h arbitration l
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PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 8.4.2 Master Receiver Buffered mode In the Master Receiver Buffered mode, a number of data bytes are received from a slave transmitter several bytes at a time (see Figure 12). The transfer is initialized as in the Master Transmitter Byte mode. The Master Receiver Buffered mode may now be entered by setting the STA bit. The I2C-bus state machine will first test the I2C-bus and generate a START condition as soon as the bus becomes free.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller MR successful reception from a Slave Transmitter S SLA R A DATA A A P 50h 58h F8h (3) (4) DATA A DATA (2) 08h next transfer started with a repeated START condition S SLA R 10h Not Acknowledge received after the slave address A P 48h F8h W to Master Transmitter mode entry = MT(5) arbitration lost in slave address or Acknowledge bit A or A other MST continues 38h arbitration lost and addressed as slave A fr
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PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 8.4.3 Slave Receiver Buffered mode In the Slave Receiver Buffered mode, a number of data bytes are received from a master transmitter several bytes at a time (see Figure 13). To initiate the Slave Receiver Byte mode, I2CADR and I2CCON must be loaded as shown in Table 37 and Table 38. Table 37.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller If the LB bit is reset (logic 0), the PCA9665 will return an acknowledge for all the bytes that will be received. The maximum number of bytes that are received in a single sequence is defined by BC[6:0] in I2CCOUNT register as shown in Table 39. If the LB bit is set (logic 1) during a transfer, the PCA9665 will return a not acknowledge (logic 1) on SDA after receiving the last byte.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Slave Receiver Buffered mode (MODE = 1) Status Status of the code I2C-bus and the (I2CSTA) PCA9665 Applica
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Slave Receiver Buffered mode (MODE = 1) …continued Status Status of the code I2C-bus and the (I2CSTA) PCA96
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Slave Receiver Buffered mode (MODE = 1) …continued Status Status of the code I2C-bus and the (I2CSTA) PCA96
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 8.4.4 Slave Transmitter Buffered mode In the Slave Transmitter Buffered mode, a number of data bytes are transmitted to a master receiver several bytes at a time (see Figure 14). Data transfer is initialized as in the Slave Receiver Buffered mode.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Slave Transmitter Buffered mode (MODE = 1) Application software response A8h Load data bytes or X Total
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Slave Transmitter Buffered mode (MODE = 1) …continued Status Status of the code I2C-bus and the (I2CSTA) PC
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 8.5 Buffered mode examples 8.5.1 Buffered Master Transmitter mode of operation 1. Program the I2CCOUNT register with the number of bytes that need to be sent to the I2C-bus (BC[6:0] has a value from 01h to 44h). LB bit is used for Receiver mode only and can be set to 0 or 1. 2. Load the data bytes in I2CDAT buffer. The different bytes to be sent will be stored in the PCA9665 buffer.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 3. Program I2CCON register to initiate the Master Receiver Buffered sequence. In Master mode, if STA = 1, a START command is sent. An interrupt will be asserted and the SI bit is set in the I2CCON register after the START has been sent. The I2CSTA register contains the status of the transmission. MODE bit must be set to ‘1’ each time a write to the I2CCON register is performed. 4.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 6. More sequences (program I2CCOUNT register, load data bytes in I2CDAT buffer, write the I2CCON register to send the data to the I2C-bus, read the I2CSTA register when sequence has been executed) can be performed as long as the master acknowledges the bytes sent by the PCA9665 and AA = 1. Slave Transmitter Buffered mode ends when the I2C-bus master does not acknowledge a byte or when the PCA9665 goes to Non-addressed Slave mode. 8.5.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller – the SCL line is held LOW by the PCA9665 after the 2 bytes have been sent – the PCA9665 sends an Interrupt, sets SI = 1 and updates I2CSTA register – I2CSTA reads 28h 5. Program I2CCOUNT = 40h (64 bytes to read and Last byte acknowledged). 6. Load I2CDAT with A1h (I2C-bus slave address and Read command). 7. Program I2CCON with STA = 1, SI = 0, MODE = 1.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller In Buffered Receiver mode, when an interrupt is generated and SI is set to 1 (after a STOP command or a buffer full condition), the buffer pointer is reset and points at the first received data byte. Reading the I2CCOUNT register then indicates the number of bytes that have been sent or received (BC[6:0]). Reading of the data from I2CDAT buffer can then be initiated starting with the first received byte. Table 42.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Remark: Request to send or receive a number of bytes equal to 0 or higher than 68 (BC[6:0] = 000 0000 or BC[6:0] > 100 0100) will cause no data to be transferred and an interrupt to be generated after writing to the I2CCON register. I2CSTA status register is loaded with FCh that indicates that an invalid value was requested to be loaded in I2CCOUNT. 8.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Table 44.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Table 45.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Table 45.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 8.8 Miscellaneous states There are four I2CSTA codes that do not correspond to a defined PCA9665 state (see Table 46). These are discussed in Section 8.8.1 through Section 8.8.4. Table 46.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 8.8.4 I2CSTA = 78h This status code indicates that the SCL line is stuck LOW. 8.9 Some special cases The PCA9665 has facilities to handle the following special cases that may occur during a serial transfer. 8.9.1 Simultaneous repeated START conditions from two masters A repeated START condition may be generated in the Master Transmitter or Master Receiver modes.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller time-out STA flag SDA line SCL line START condition 002aab029 Fig 16. Forced access to a busy I2C-bus 8.9.4 I2C-bus obstructed by a LOW level on SCL or SDA An I2C-bus hang-up occurs if SDA or SCL is pulled LOW by an uncontrolled source. If the SCL line is obstructed (pulled LOW) by a device on the bus, no further serial transfer is possible, and the PCA9665 cannot resolve this type of problem.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller STA flag SDA line 1 2 3 4 5 6 7 8 9 SCL line STOP condition START condition 002aab030 Fig 17. Recovering from a bus obstruction caused by a LOW level on SDA 8.9.5 Bus error A bus error occurs when a START or STOP condition is present at an illegal position in the format frame. Examples of illegal positions are during the serial transfer of an address byte, a data or an acknowledge bit.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 8.11 Reset Reset of the PCA9665 to its default state can be performed in 2 different ways: • By holding the RESET pin LOW for a minimum of tw(rst). • By using the Parallel Software Reset sequence as described in Figure 18.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller SCL SDA INT 7-bit address interrupt R/W = 1 START condition interrupt first byte ACK n byte STOP condition no ACK ACK from master receiver from slave 002aab032 Master PCA9665 reads data from slave transmitter. Fig 20.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 8.13 I2C-bus timing diagrams, Buffered mode The diagrams (Figure 23 through Figure 26) illustrate typical timing diagrams for the PCA9665 in master/slave functions. SCL SDA INT 7-bit address(1) first byte(1) R/W = 0 START condition ACK n byte(1) interrupt ACK ACK STOP condition 002aab267 from slave receiver Master PCA9665 writes data to slave transmitter.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller SCL SDA INT 7-bit address(1) interrupt first byte(2) R/W = 1 START condition n byte(2) ACK interrupt no ACK ACK from master receiver from slave PCA9665 STOP condition 002aab269 External master receiver reads data from PCA9665. (1) As defined in I2CADR register. (2) Number of bytes received = value programmed in I2CCOUNT register (BC[6:0] ≤ 68). Fig 25.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 9. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 9.1 Bit transfer One data bit is transferred during each clock pulse.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 30. System configuration 9.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 10. Application design-in information VDD address bus VDD VDD A0 A1 PCA9665 DECODER ALE CE SCL 80C51 8 D0 to D7 RD VDD SDA WR SLAVE INT INT SLAVE RESET VDD RESET VSS VSS 002aab035 Fig 32. Application diagram using the 80C51 10.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller control signals SDA MICROCONTROLLER, MICROPROCESSOR, OR ASIC PCA9665 SCL 8 bits data 002aab036 Fig 33. Adding I2C-bus port application 10.3 Add additional I2C-bus ports The PCA9665 can be used to convert 8-bit parallel data into additional multiple master capable I2C-bus port as shown in Figure 34. It is used if the microcontroller, microprocessor, custom ASIC, DSP, etc.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 11. Limiting values Table 47. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage Conditions Min Max Unit −0.3 +4.6 V VI input voltage any input −0.8 +6.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 12. Static characteristics Table 48. Static characteristics VDD = 2.3 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supply VDD supply voltage IDD supply current VPOR 2.3 - 3.6 V standby mode - 0.1 3.0 mA operating mode; no load - - 8.0 mA - 1.8 2.2 V 0 - 0.8 V 2.0 - 5.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 13. Dynamic characteristics Table 49. Dynamic characteristics (3.3 volt)[1][2][3] VCC = 3.3 V ± 0.3 V; Tamb = −40 °C to +85 °C; unless otherwise specified. (See Table 50 on page 72 for 2.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Table 50. Dynamic characteristics (2.5 volt)[1][2][3] VCC = 2.5 V ± 0.2 V; Tamb = −40 °C to +85 °C; unless otherwise specified. (See Table 49 on page 71 for 3.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller ACK or read cycle START SCL 30 % SDA 30 % 30 % trst RESET 50 % 50 % 50 % trec(rst) tw(rst) trst Dn on Dn 30 % Dn off 002aab272 Fig 36. Reset timing D7 to D0 write to I2CCON WR 6 7 8 9 1 2 3 SCL INT tas(int) tdas(int) 002aac227 Fig 37. Interrupt timing PCA9665_2 Product data sheet © NXP B.V. 2006. All rights reserved. Rev.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller A0 to A1 tsu(A) th(A) CE tsu(CE_N) th(CE_N) tw(RDL) tw(RDH) RD td(QZ) td(DV) D0 to D7 (read) float not valid valid float 002aac693 Fig 38. Bus timing (read cycle) A0 to A1 tsu(A) th(A) CE tsu(CE_N) th(CE_N) tw(WRL) tw(WRH) WR tsu(Q) D0 to D7 (write) th(Q) valid 002aac692 Fig 39. Parallel bus timing (write cycle) PCA9665_2 Product data sheet © NXP B.V. 2006. All rights reserved. Rev.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller VI RD, CE input VM GND VM t d(QLZ) t d(QZL) VDD Dn output LOW-to-float float-to-LOW VM VX VOL t d(QZH) t d(QHZ) Dn output HIGH-to-float float-to-HIGH VOH VY VM GND outputs enabled outputs floating outputs enabled 002aab274 VM = 1.5 V VX = VOL + 0.3 V VY = VOH − 0.3 V VOL and VOH are typical output voltage drops that occur with the output load. Fig 40. Data timing PCA9665_2 Product data sheet © NXP B.V. 2006.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Table 51. I2C-bus frequency and timing specifications All the timing limits are valid within the operating supply voltage and ambient temperature range; VDD = 2.5 V ± 0.2 V and 3.3 V ± 0.3 V; Tamb = −40 °C to +85 °C; and refer to VIL and VIH with an input voltage of VSS to VDD.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller SDA tLOW tf tSU;DAT tr tHD;STA tSP tf tBUF tr SCL tHIGH tSU;STA tHD;DAT tHD;STA S tSU;STO Sr P S 002aab271 Fig 41. Definition of timing on the I2C-bus protocol START condition (S) tSU;STA bit 7 MSB tLOW bit 6 tHIGH 1/f bit n bit 0 acknowledge (A) STOP condition (P) SCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aac696 Rise and fall times refer to VIL and VIH. Fig 42.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 14. Test information VDD PULSE GENERATOR VI RL 500 Ω VO VDD × 2 open VSS DUT CL 50 pF RT RL 500 Ω 002aac694 Test data are given in Table 52. RL = load resistance. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance ZO of the pulse generators. Fig 43. Test circuitry for switching times Table 52.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 15. Package outline DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 11 20 pin 1 index E 1 10 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.014 0.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller HVQFN20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm A B D SOT662-1 terminal 1 index area A A1 E c detail X C e1 e b 6 y y1 C v M C A B w M C 10 L 11 5 e e2 Eh 1 15 terminal 1 index area 20 16 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.38 0.23 c D(1) Dh E(1) Eh 0.2 5.1 4.9 3.25 2.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 16. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits. 17. Soldering 17.1 Introduction There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 54 and 55 Table 54. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) ≥ 350 < 350 < 2.5 235 220 ≥ 2.5 220 220 Table 55.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 17.3.2 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Table 56. Suitability of IC packages for wave, reflow and dipping soldering methods …continued Mounting Package[1] Soldering method Wave Surface mount HTSSON..T[5], not suitable BGA, LBGA, LFBGA, SQFP, SSOP..
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 18. Abbreviations Table 57. Abbreviations Acronym Description ASIC Application Specific Integrated Circuit CDM Charged Device Model CPU Central Processing Unit DSP Digital Signal Processing ESD ElectroStatic Discharge HBM Human Body Model I2C-bus Inter-Integrated Circuit bus I/O Input/Output MM Machine Model PCB Printed-Circuit Board SMBus System Management Bus 19. Revision history Table 58.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller Table 58.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 22. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.3.1.1 7.3.1.2 7.3.1.3 7.3.1.4 7.3.1.5 7.3.2 7.3.2.1 7.3.2.2 7.3.2.3 7.3.2.4 7.3.2.5 7.3.2.6 8 8.1 8.1.1 8.1.2 8.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.4 8.4.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . .
PCA9665 NXP Semiconductors Fm+ parallel bus to I2C-bus controller 12 13 14 15 16 17 17.1 17.2 17.2.1 17.2.2 17.3 17.3.1 17.3.2 17.3.3 17.4 18 19 20 20.1 20.2 20.3 20.4 21 22 Static characteristics. . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Test information . . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information. . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . .
