Freescale Semiconductor Advance Information Document number: MC34708 Rev. 10.0, 2/2013 Power Management Integrated Circuit (PMIC) for i.MX50/53 Families 34708 The MC34708 is the Power Management Integrated Circuit (PMIC) designed specifically for use with the Freescale i.MX50 and i.MX53 families.
Table of Contents 1 Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Part Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9 Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.9.1 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.9.2 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Orderable Parts 1 Orderable Parts This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers. Table 1. Orderable Part Variations Part Number (1) Temperature (TA) MC34708VK MC34708VM -40 to 85 °C Package 206 MAPBGA - 8.0 x 8.0 mm - 0.
Part Identification 2 Part Identification This section provides an explanation of the part numbers and their alpha numeric breakdown. 2.1 Description Part numbers for the chips have fields that identify the specific part configuration. You can use the values of these fields to determine the specific part you have received. 2.
Input/Battery Monitoring O/P Drive General Purpose LED Drivers SW1 Dual Phase GP 2000 mA Buck LICELL, UID, Die Temp, GPO4 GNDADC ADIN9 Voltage / Current Sensing & Translation 10 Bit GP ADC O/P Drive SW2 LP ` 1000 mA Buck ADIN13/TSX2 ADIN15/TSY2 Touch Screen Interface Die Temp & Thermal Warning Detection TSREF BPTHERM To Interrupt Section SW3 INT MEM 500 mA Buck NTCREF BATTISNSCCP SW4 Dual Phase DDR 1000 mA Buck BATTISNSCCN CFP Package Pin Legend CFN Input Pin CS CLK MOSI MISO GNDSPI Shi
Pin Connections 4 Pin Connections 4.
Pin Connections 4.2 Pin Definitions Table 3. MC34708 Pin Definitions Pin Number Pin Name Pin Function Definition Charger (Function no longer supported on MC34708) A7, B7, C7, D7 VBUSVIN NC Charger Not supported. No Connect B1, B2, C1, C2 AUXVIN NC Charger Not supported. No Connect VAUX NC Charger Not supported. No Connect A8, B8, C8, D8 CHRGLX NC Charger Not supported. No Connect C5 CHRGFB I GOTG NC Charger Not supported. No Connect GAUX NC Charger Not supported.
Pin Connections Table 3.
Pin Connections Table 3.
Pin Connections Table 3. MC34708 Pin Definitions (continued) Pin Number Pin Name Pin Function L12 GNDREG2 GND A13 GPIOVDD I E11 GPIOLV0 I/O General purpose input/output 0 B11 GPIOLV1 I/O General purpose input/output 1 D11 GPIOLV2 I/O General purpose input/output 2 C11 GPIOLV3 I/O General purpose input/output 3 A12 PWM1 O PWM output 1 C10 PWM2 O PWM output 2 B12 GNDGPIO - GPIO ground LICELL I/O M15 XTAL1 I 32.
Pin Connections Table 3.
Pin Connections Table 3. MC34708 Pin Definitions (continued) Pin Number Pin Name Pin Function C3 SUBSANA3 GND Definition Substrate ground connection for analog circuitry Notes 2. In applications without USB support, leave all USB pins unconnected.
General Product Characteristics 5 General Product Characteristics 5.1 Maximum Ratings Table 4. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Description (Rating) Max. Unit Notes ELECTRICAL RATINGS VBATT, VBP, VLICELL Input Supply Pins V • BATT, BP, BPSNS 4.8 • LICELL 4.8 Input Sense Pins V • CHRGFB 7.5 • BATTISNSP, BATTISNSN 5.
General Product Characteristics Table 4. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol VESD Description (Rating) Max.
General Product Characteristics Table 5. Thermal Ratings (continued) Symbol RθJMA Description (Rating) Junction to Ambient (@200 ft/min.) Min. Max. Unit Notes - 48 °C/W (8), (10) - 32 °C/W (8), (10) • Single layer board (1s) RθJMA Junction to Ambient (@200 ft/min.) • Four layer board (2s2p) RθJB Junction to Board - 22 °C/W (11) RθJC Junction to Case - 15 °C/W (12) θJT Junction to Package Top - 3.0 °C/W (13) • Natural Convection Notes 5.
General Product Characteristics 5.2.1 Power Dissipation During operation, the temperature of the die should not exceed the maximum junction temperature. To optimize the thermal management scheme and avoid overheating, the MC34708 PMIC provides a thermal management system. The thermal protection is based on a circuit with a voltage output proportional to the absolute temperature.This voltage can be read out via the ADC for specific temperature readouts, see Channel 3 Die Temperature.
General Product Characteristics 5.3 Electrical Characteristics 5.3.1 Recommended Operating Conditions Table 8. Recommended Operating Conditions Symbol Description (Rating) VBP VLICELL TA 5.3.2 Min. Max. Unit Main Input Supply 3.0 4.5 V LICELL Backup Battery 1.8 3.6 V Ambient Temperature -40 85 °C Notes General PMIC Specifications Table 9.
General Product Characteristics Table 9. Pin Logic Thresholds Pin Name MISO, INT PUMS1,2,3,4,5 ICTEST SW1CFG, SW4CFG Notes 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. Internal Termination (19) Load Condition Min Max (22) Unit Output Low -100 A 0.0 0.2 V Output High 100 A SPIVCC - 0.2 SPIVCC V Input Low PUMSxS = 0 - 0.0 0.3 V (17) Input High PUMSxS = 1 - 1.0 VCOREDIG V (17) Input Low - 0.0 0.3 V (18) Input High - 1.1 1.7 V (18) Input Low - 0.0 0.
General Product Characteristics 5.3.3 Current Consumption The current consumption of the individual blocks is described in detail throughout this specification. For convenience, a summary table follows for standard use cases. Table 10. Current Consumption Summary (27) Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
General Product Characteristics Table 10. Current Consumption Summary (27) Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
General Description 6 General Description 6.
General Description 6.2 Block Diagram SIX BUCK REGULATORS Processor Core Split Power Domains DDR Memory I/O EIGHT LDO REGULATORS Peripherals 10-BIT ADC CORE General Purpose Resistive Touch Screen Interface 32.
Functional Block Description 7 Functional Block Description 7.1 Startup Requirements When power is applied, there is an initial delay of 8.0 ms during which the core circuitry is enabled. The switching and linear regulators are then sequentially enabled in time slot steps of 2.0 ms. This allows the PMIC to limit the inrush current. The outputs of the switching regulators not enabled are discharged with weak pull-downs on the output to ensure a proper powerup sequence.
Functional Block Description Table 11. Power Up Defaults i.MX Reserved 53 LPM 53 DDR2 53 DDR3 53 LVDDR3 53 LVDDR2 50 MDDR 50 50 50 50 50 LPDDR2 LPDDR2 MDDR LPDDR2 MDDR VSRTC Reserved 1.2 1.3 1.3 1.3 1.3 1.2 1.2 1.2 1.2 1.2 1.2 VPLL Reserved 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 VREFDDR Reserved On On On On On On On On On On On VDAC Reserved 2.775 2.775 2.775 2.775 2.775 2.5 2.5 2.5 2.5 2.5 2.5 VGEN1 Reserved 1.2 1.3 1.3 1.3 1.3 1.
Functional Block Description Table 13. Power Up Sequence i.MX50 Tap x 2.0 ms PUMS [4:1] = [0100, 1011, 1100, 1101, 1110, 1111] (i.MX50/I.MX53) 0 SW2 1 SW3 2 SW1A/B 3 VDAC 4 SW4A/B, VREFDDR 5 SW5 6 VGEN2, VUSB2 7 VPLL 8 VGEN1 9 VUSB (34) Notes: 34. The VUSB regulator is only enabled if 5.0 V is present on the VBUS pin. By default VUSB will be supplied by the VBUS pin. 7.
Functional Block Description Table 14. Core Voltages Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit • ON mode - 2.775 - • OFF and RTC mode - 0.0 - - 1.0 - F Output voltage - 1.2 - V Absolute Accuracy - 0.5 - % Temperature Drift - 0.
Functional Block Description 7.3.1.2 Oscillator Specifications The crystal oscillator has been optimized for use in conjunction with the Micro Crystal CC7V-T1A32.768 kHz-9.0 pF-30 ppm or equivalent (such as Micro Crystal CC5V-T1A or Epson FC135) and is capable of handling its parametric variations. The electrical characteristics of the 32 kHz Crystal oscillator are given in the following table, taking into account the crystal characteristics noted above.
Functional Block Description 7.3.2 SRTC Support When configured for DRM mode (SPI bit DRM = 1), the CLK32KMCU driver will be kept enabled through all operational states to ensure the SRTC module always has its reference clock. If DRM = 0, the CLK32KMCU driver will not be maintained in the Off state. It is also necessary to provide a means for the processor to do an RTC initiated wake-up of the system if it has been programmed for such capability.
Functional Block Description Table 16. VSRTC Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit 1.15 1.20 1.28 V 1.15 1.2 1.25 V 1.25 1.3 1.
Functional Block Description frequency and more accurate system clock such as a TCXO. If the RTC timer needs a correction, a 5-bit 2’s complement calibration word can be sent via the SPI to compensate the RTC for inaccuracy in its reference oscillator. Table 17.
Functional Block Description Table 19. Coin Cell Voltage Specifications VCOIN[2:0] Output Voltage 000 2.50 001 2.70 010 2.80 011 2.90 100 3.00 101 3.10 110 3.20 111 3.30 Table 20. Coin Cell Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Functional Block Description 7.4.2 Interrupt Bit Summary Table 21 summarizes all interrupt, mask, and sense bits associated with INT control. For more detailed behavioral descriptions, refer to the related chapters. Table 21. Interrupt, Mask and Sense Bits Interrupt Mask Sense Purpose Debounce Time Trigger ADCDONEI ADCDONEM - ADC has finished requested conversions L2H 0 TSDONEI TSDONEM - Touch screen has finished conversion L2H 0 TSPENDET TSPENDETM - Touch screen pen detect Dual 1.
Functional Block Description Table 21.
Functional Block Description 7.5 Power Generation The MC34708 PMIC provides reference and supply voltages for the application processor as well as peripheral devices. Six buck (step down) converters and one boost (step up) converter are included. One of the buck regulators can be configured in dual phase, single phase mode, or operate as separate independent outputs (in this case, there are six buck converters).
Functional Block Description 7.5.2 Modes of Operation The MC34708 PMIC is fully programmable via the SPI/I2C interface and associated register map. Additional communication is provided by direct logic interfacing, including interrupt, watchdog, and reset. Default startup of the device is selectable by hardwiring the Power Up Mode Select (PUMS) pins. Power cycling of the application is driven by the MC34708 PMIC.
Functional Block Description The following are text descriptions of the power states of the system for additional details of the state machine to complement the drawing in Figure 6. Note that the SPI control is only possible in the Watchdog, On and User Off Wait states and the interrupt line INT is kept low in all states except for Watchdog and On. 7.5.2.
Functional Block Description 7.5.2.7 Memory Hold and User Off (Low Power Off States) As noted in the User Off Wait description, the system is directed into low power Off states based on a SPI command in response to an intentional turn off by the user. The only exit then will be a turn on event. To the user, the Memory Hold and User Off states look like the product has been shut down completely.
Functional Block Description RESETB is kept low and RESETBMCU is kept high. CLK32KMCU is kept active if CLK32KMCU was set. The reset timer starts running when entering Warm Start. When expired, the Warm Start state is exited for the Watchdog state, a WARMI interrupt is generated, and RESETB will go high. 7.5.2.11 Internal MemHold Power Cut As described in the Power Cut Description, a momentary power interruption will put the system into the Internal MemHold Power Cut state if PCUTs are enabled.
Functional Block Description 7.5.3.2 Silent Restart from PCUT Event If a short duration power cut event occurs (such as from a battery bounce, for example), it may be desirable to perform a silent restart, so the system is reinitialized without alerting the user. This can be facilitated by setting the PCUTEXPB bit to “1” at booting or after a Cold Start. This bit resets on RTCPORB, therefore any subsequent Cold Start can first check the status of PCUTEXPB and the PCI bit.
Functional Block Description Table 23. PWRONx Hardware Debounce Bit Settings(39) Bits State Turn On Debounce (ms) Falling Edge INT Debounce (ms) Rising Edge INT Debounce (ms) PWRONxDBNC[1:0] 00 0.0 31.25 31.25 01 31.25 31.25 31.25 10 125 125 31.25 11 750 750 31.25 Notes 39. The sense bit PWRONxS is not debounced and follows the state of the PWRONx pin.
Functional Block Description Table 25. Turn OFF Voltage Threshold 7.5.3.6 VBAT_TRKL[1:0] Turn off Voltage threshold 00 2.8 01 2.9 10 3.0 (default) 11 3.1 Timers The different timers as used by the state machine are listed in Table 26. This listing does not include RTC timers for timekeeping. A synchronization error of up to one clock period may occur with respect to the occurrence of an asynchronous event, the duration listed below is therefore the effective minimum time period. Table 26.
Functional Block Description 7.5.3.7 Power Monitoring The voltage at BATT and BP are monitored by detectors as summarized in Table 27. Table 27. LOWBATT Detection Thresholds Threshold in V Bit setting(40) UVDET (V) LOWBATT1 LOWBATT0 0 0 3.1 (Rising) L to H transition (Power on)(41),(42) H to L transition (Low battery detect)(41),(42) LOWBATT LOWBATT 3.1 3.0 3.2 3.1 3.3 3.2 3.4 3.3 2.65 (Falling) 0 1 3.1 (Rising) 2.65 (Falling) 1 0 3.1 (Rising) 2.65 (Falling) 1 1 3.1 (Rising) 2.
Functional Block Description is attached by de-asserting the STANDBY pin and waking up for a period to see if a device is attached and then re-asserting Standby if a device has not been detected. If a device has been detected then the software can bring up the appropriate application etc. Note the STANDBY pin is programmable for Active High or Active Low polarity, and decoding of a Standby event will take into account the programmed input polarity associated with each pin.
Functional Block Description 7.5.4 Buck Switching Regulators Six buck switching regulators are provided with integrated power switches and synchronous rectification. In a typical application, SW1 and SW2 are used for supplying the application processor core power domains. Split power domains allow independent DVS control for processor power optimization, or to support technologies with a mix of device types with different voltage ratings.
Functional Block Description Table 32. Switching regulator Mode Control for Normal and Standby Operation SWxMODE[3:0] Normal Mode Standby Mode 0100 APS Off 0101 PWM PWM 0110 PWM APS 0111 Off Off 1000 APS APS 1001 Reserved Reserved 1010 Reserved Reserved 1011 Reserved Reserved 1100 APS PFM 1101 PWM PFM 1110 Reserved Reserved 1111 PFM PFM In addition to controlling the operating mode in Standby, the voltage setting can be changed.
Functional Block Description 7.5.4.2 Switching Frequency A PLL generates the switching system clocking from the 32.768 kHz crystal oscillator reference. The switching frequency can be programmed to 2.0 MHz or 4.0 MHz by setting the PLLX SPI bit as shown in Table 35. Table 35. Buck Regulator Frequency PLLX Switching Frequency (Hz) 0 2 000 000 1 4 000 000 The clocking system provides a near instantaneous activation when the Switching regulators are enabled or when exiting PFM operation for PWM mode.
Functional Block Description BP SW1IN SW1AMODE ISENSE CINSW1A SW1 Controller SW1ALX Driver L SW1A DSW1A COSW1A SW1FAULT GNDSW1A Internal Compensation SW1FB SPI Z2 Z1 EA SPI Interface V REF DAC BP SW1BIN SW1BMODE ISENSE CINSW1B Controller SW1BLX LSW 1B Driver DSW1B COSW 1B SW1BFAULT GNDSW1B SW1CFG Figure 9. SW1 Dual Phase Output Mode Block Diagram The peak current is sensed internally for over-current protection purposes.
Functional Block Description Table 37. SW1A/B Output Voltage Programmability Set Point SW1A[5:0] SW1A/B Set Point SW1A[5:0] Output (V) SW1A/B Output (V) 13 001101 0.8125 45 101101 1.2125 14 001110 0.8250 46 101110 1.2250 15 001111 0.8375 47 101111 1.2375 16 010000 0.8500 48 110000 1.2500 17 010001 0.8625 49 110001 1.2625 18 010010 0.8750 50 110010 1.2750 19 010011 0.8875 51 110011 1.2875 20 010100 0.9000 52 110100 1.3000 21 010101 0.9125 53 110101 1.
Functional Block Description Table 38. SW1A/B Electrical Specification Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol tON-SW1 Characteristic Min Typ Max - - 500 • PLLX = 0 - 2.0 - • PLLX = 1 - 4.
Functional Block Description Table 39. SW2 Output Voltage Programmability Set Point SW2[5:0] SW2x Output (V) Set Point SW2[5:0] SW2 Output (V) 0 000000 0.6500 32 100000 1.0500 1 000001 0.6625 33 100001 1.0625 2 000010 0.6750 34 100010 1.0750 3 000011 0.6875 35 100011 1.0875 4 000100 0.7000 36 100100 1.1000 5 000101 0.7125 37 100101 1.1125 6 000110 0.7250 38 100110 1.1250 7 000111 0.7375 39 100111 1.1375 8 001000 0.7500 40 101000 1.
Functional Block Description Table 40. SW2 Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max • PWM operation, 0 < IL < IMAX 3.0 - 4.5 • PFM operation, 0 < IL < ILMAX 2.8 - 4.
Functional Block Description 7.5.4.5 SW3 SW3 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator. BP SW3IN SW3MODE ISENSE CINSW 3 SW3 Controller SW3LX Driver L SW3 COSW3 DSW3 SW3FAULT GNDSW3 Internal Compensation SW3FB SPI Interface SPI Z2 Z1 EA DAC V REF Figure 11. SW3 Block Diagram The peak current is sensed internally for over-current protection purposes.
Functional Block Description Table 42. SW3 Electrical Specification Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max • PWM operation, 0 < IL < IMAX 3.0 - 4.5 • PFM operation, 0 < IL < ILMAX 2.8 - 4.
Functional Block Description 7.5.4.6 SW4 SW4A/B is fully integrated synchronous Buck PWM voltage-mode control DC/DC regulator. It can be operated in (single phase/ dual phase mode) or as separate independent outputs. The operating mode of the Switching regulator is configured by the SW4CFG pin. The SW4CFG pin is sampled at startup. Table 43.
Functional Block Description BP SWAIN SW4AMODE ISENSE CINSW4A SW4 SW4ALX LSW4A Controller Driver DSW4 COSW4a SW4AFAULT GNDSW4A Internal Compensation SW4AFB SPI Z2 Z1 VREF EA DAC SPI Interface BP SW4BIN SW4BMODE ISENSE CINSW4B SW4BLX Controller Driver SW4BFAULT GNDSW4B Internal Compensation SW4BFB SPI Z2 Z1 EA VCOREDIG VREF DAC SW4CFG Figure 13.
Functional Block Description BP SWAIN SW4AMODE ISENSE CINSW4A SW4 SW4ALX LSW4A Controller Driver DSW4A COSW4A SW4AFAULT GNDSW4A Internal Compensation SW4AFB SPI Z2 Z1 VREF EA DAC SPI Interface BP SW4BIN SW4BMODE ISENSE CINSW4B SW4BLX LSW4B Controller Driver DSW4B COSW4B SW4BFAULT GNDSW4B Internal Compensation SW4BFB SPI Z2 Z1 EA VCORE VREF DAC SW4CFG Figure 14. SW4 Dual Phase Output Mode Block Diagram The peak current is sensed internally for over-current protection purposes.
Functional Block Description Table 45. SW4A/B Output Voltage Programmability Set Point SW4x[4:0] SW4x Output (V) 0 00000 1.2000 16 10000 1.6000 1 00001 1.2250 17 10001 1.6250 2 00010 1.2500 18 10010 1.6500 3 00011 1.2750 19 10011 1.6750 4 00100 1.3000 20 10100 1.7000 5 00101 1.3250 21 10101 1.7250 6 00110 1.3500 22 10110 1.7500 7 00111 1.3750 23 10111 1.7750 8 01000 1.4000 24 11000 1.8000 9 01001 1.4250 25 11001 1.8250 10 01010 1.
Functional Block Description Table 46. SW4A/B Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol tON-SW4 Characteristic Min Typ Max - - 500 • PLLX = 0 - 2.0 - • PLLX = 1 - 4.0 - • APS MODE, IL = 0 mA; High output voltage range (VSW4x = 3.15 V or 2.
Functional Block Description 7.5.4.7 SW5 SW5 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator. BP SW5IN SW5MODE ISENSE CINSW5 SW5 Controller SW5LX Driver LSW5 COSW5 DSW5 SW5FAULT GNDSW5 Internal Compensation SW5FB SPI Interface SPI Z2 Z1 VREF EA DAC Figure 15. SW5 Block Diagram The peak current is sensed internally for over-current protection purposes.
Functional Block Description Table 48. SW5 Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max • PWM operation, 0 < IL < IMAX 3.0 - 4.5 • PFM operation, 0 < IL < ILMAX 2.8 - 4.
Functional Block Description 7.5.4.8 Dynamic Voltage Scaling To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor. SW1A/B and SW2 allow for two different set points with controlled transitions to avoid sudden output voltage changes, which could cause logic disruptions on their loads. Preset operating points for SW1A/B and SW2 can be set up for: • Normal operation: output value selected by SPI bits SWx[5:0].
Functional Block Description Request ed Set Point Output Voltage wit h light Load Internally Cont rolled Steps Example Actual Output Voltage Output Voltage Init ial Set Point Actual Output Voltage Internally Controlled St eps Request for Higher Voltage Voltage Change Request Possible Output Voltage Window Request for Lower Voltage I nit iated by SPI Programming, Standby Control SWxP WGD Figure 16. Voltage Stepping with DVS 7.5.
Functional Block Description Table 51. SWBST Voltage Programming Parameter Voltage SWBST Output Voltage SWBST[1:0] 00 5.000 (default) 01 5.050 10 5.100 11 5.150 SWBST can be controlled by SPI programming in PFM, APS, and Auto mode. Auto mode transitions between PFM and APS mode based on the load current. By default SWBST is powered up in Auto mode. Table 52.
Functional Block Description Table 53. SWBST Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol VSWBST TRANSIENT VSWBST TRANSIENT VSWBST TRANSIENT SWBST ISWBSTBIAS Characteristic Min Typ Max - - 300 - - 500 Transient Load Response, IL from 100 to 1.0 mA in 1.
Functional Block Description 7.5.6.2 LDO Regulator Control The regulators with embedded pass devices (VPLL, VGEN1, and VUSB) have an adaptive biasing scheme thus, there are no distinct operating modes such as a Normal mode and a Low Power mode. Therefore, no specific control is required to put these regulators in a Low Power mode. The external pass regulator (VDAC) can also operate in a normal and low power mode.
Functional Block Description VNOM + 0.8V IMAX VIN ILOAD VNOM + 0.3V 0 mA 10us 10us 1us VIN Stimulus for Transient Line Response IL = 0 mA 1us ILOAD Stimulus for Transient Load Response IL = IMAX Overshoot VOUT Overshoot VOUT for Transient Load Response Active Mode Active Mode Low Power Mode Overshoot VOUT Mode Transition Time Overshoot IL < ILMAX IL < ILMAXLP IL < ILMAX VOUT for Mode Transition Response (VGEN2, VUSB2, VDAC) Figure 18. Transient Waveforms 7.5.6.
Functional Block Description noise injection must be avoided and filtering added, if necessary to ensure suitable PLL performance. The VPLL regulator has a dedicated input supply pin. VINPLL can be connected to either BP or a 1.8 V switched mode power supply rail such as from SW5 for the two lower set points of each regulator VPLL[1:0] = [00], [01]. In addition, when the two upper set points (VPLL[1:0] = [10],[11]) are used, the VINPLL inputs can be connected to either BP or a 2.
Functional Block Description Table 57. VPLL Electrical Specification Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V,- 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol VPLL-LO TRANSIENT VPLL-LI TRANSIENT 7.5.6.6 Characteristic Min Typ Max - 50 70 Transient Load Response Unit Notes mV • VIN = VINMIN, VINMAX Transient Line Response mV • IL = 75% of ILMAX - 5.0 8.
Functional Block Description 7.5.6.7 VUSB2 VUSB2 has an internal PMOS pass FET which will support loads up to 65 mA. To support load currents an external PNP is provided. The external PNP configuration is offered to avoid excess on-chip power dissipation at higher loads and large differentials between BP and output settings. For lower current requirements, an integrated PMOS pass FET is included. The input pin for the integrated PMOS option is shared with the base current drive pin for the PNP option.
Functional Block Description Table 60. VUSB2 Electrical Specification Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max VNOM - 3% VNOM VNOM + 3% 0.0 - 3.0 - 8.0 10.5 VUSB2PSRR PSRR, IL = 75% of ILMAX 20 Hz to 20 kHz • VIN = VINMIN + 100 mV - 30 - • VIN = VNOM + 1.0 V - 30 - - - 1.
Functional Block Description Table 61. VDAC Voltage Control Parameter Value Output Voltage ILoad max VDAC 00 2.500 V 250 mA 01 2.600 V 250 mA 10 2.700 V 250 mA 11 2.775 V 250 mA Table 62. VDAC Electrical Specification Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit VNOM + 0.25 - 4.5 V 0.
Functional Block Description Table 62. VDAC Electrical Specification Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max - 1.0 2.0 - 1.0 2.
Functional Block Description The nominal output voltage of VGEN2 is SPI configurable, and can be 2.5 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 3.15 V, or 3.3 V. The output current when working with the internal pass FET is 50 mA, and could be up to 250 mA when working with an external PNP. Table 64. VGEN2 Control Register Bit Assignments Parameter Value Output Voltage VGEN2[2:0] 000 ILoad max VGEN2CONFIG=0 Internal Pass FET VGEN2CONFIG=1 External PNP 2.50 50 mA 250 mA 001 2.
Functional Block Description Table 65. VGEN1 Electrical Specification Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max - 50 - - 45 - - - 1.0 0.01 - 10 - 1.0 2.0 - 1.0 2.
Functional Block Description Table 66. VGEN2 Electrical Specification Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max VNOM - 3% VNOM VNOM + 3% - 0.20 - Unit Notes VGEN2 ACTIVE MODE - DC VGEN2 Output Voltage VOUT • VINMIN < VIN < VINMAX ILMIN < IL < ILMAX VGEN2LOPP Load Regulation • 1.
Functional Block Description 7.6 Battery Management BATTERY CHARGER NO LONGER SUPPORTED ON MC34708. 7.7 Analog to Digital Converter The ADC core is a 10-bit converter. The ADC core and logic run at an internally generated frequency of approximately 1.33 MHz. The ADC is supplied from VCORE. The ADC core has an integrated auto calibration circuit which reduces the offset and gain errors. 7.7.1 Input Selector The ADC has 16 input channels.
Functional Block Description Table 68. ADC Input Specification Parameter Condition Min Typ Max Units Source Impedance No bypass capacitor at input - - 5.0 kOhm Bypass capacitor at input 10 nF - - 30 kOhm When exceeding the maximum input of the ADC at the scaled or unscaled inputs, the reading result will return a full scale. It has to be noted however, that this full scale does not necessarily yield a 1022 DEC reading due to the offsets and calibration applied.
Functional Block Description from address 0 to the stop address programmed in ADSTOP. By default, the ADCONT is set low (disabled). In the continuous mode, the ADHOLD bit will allow the software to hold the ADC sequencer from updating the results register while the ADC results are read. Once the sequence of A/D conversions is complete, the ADRESULTx results are stored in 4 SPI registers (ADC 4 ADC 7). 7.7.3 7.7.3.
Functional Block Description BP R1 20m C1 10u C2 BPSNS BP GBAT BATTISNSP CHRGFB BATT BATTISNSN 10u Battery Input/Battery Monitoring Figure 19. Input Configuration with Battery Current Sense 7.7.3.3 Channel 2 Application Supply The application supply voltage is read at the BPSNS pin on channel 2. The battery voltage is first scaled as VBPSNS /2 to fit the input range of the ADC. Table 72. Application Supply Voltage Reading Coding Conversion Code ADRESULTx[9:0] 7.7.3.
Functional Block Description 7.7.3.8 Channel 8 Coin Cell Voltage The voltage of the coin cell connected to the LICELL pin can be read on channel 8. Since the voltage range of the coin cell exceeds the input voltage range of the ADC, the LICELL voltage is scaled as V(LICELL)*2/3. See . Table 74. Coin Cell Voltage Reading Coding 7.7.3.9 Conversion Code ADRESULTx[9:0] Voltage at ADC input (V) Voltage at LICELL (V) 1 111 111 110 2.400 3.6 1 000 000 000 1.200 1.8 0 000 000 000 0.
Functional Block Description Table 75. Touch Screen Action Select TSSELx[1:0] Signals Sampled 00 Dummy to discharge TSREF cap 01 X plate 10 Y –plate 11 Contact The touch screen readings can be repeated, as in the following example readout sequence, to reduce the interrupt rate and to allow for easier noise rejection. The dummy conversion inserted between the different readings allows the references in the system to be pre-biased for the change in touch screen plate polarity.
Functional Block Description 7.7.5 ADC Specifications Table 77. ADC Electrical Specifications Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit - 1.0 - mA Notes ADC ICONVER Conversion Current VADCIN Converter Core Input Range tCONVERT tON-OFF-ADC V • Single ended voltage readings 0.0 - 2.
Functional Block Description 7.8 7.8.1 Auxiliary Circuits General Purpose I/Os The MC34708 contains four configurable GPIOs for general purpose use. When configured as outputs, they can be configured as open-drain (OD) or CMOS (push-pull outputs). These GPIOs are low voltage capable (1.2 or 1.8 V). In open drain configuration these outputs can only be pulled up to 2.5 V maximum. Each individual GPIO has a dedicated 16-bit control register. Table 78 provides detailed bit descriptions. Table 78.
Functional Block Description Table 78. GPIOLVx Control SPI Bit Description PUS[1:0] Pull-up/Pull-down enable 00: 10 K active pull-down 01: 10 K active pull-up 10: 100 K active pull-down 11: 100 K active pull-up (default) SRE[1:0] Slew rate enable 00: slow (default) 01: normal 10: fast 11: very fast x= 0, 1, 2, or 3 7.8.2 PWM Outputs There are two PWM outputs on the MC34708. PWM1 and PWM2 are controlled by the PWMxDUTY and PWMxCLKDIV registers shown in Table 79.The base clock will be the 2.
Functional Block Description 7.8.3 General Purpose LED Drivers To turn on the LEDs, the following bits must be set, CHRLEDxEN = 1, CHRGLEDOVRD =1, THERM bit = 1, and programming the duty cycle > 0/32. Table 81. LED Driver Control THERM CHRGLEDxEN(67) CHRGLEDOVRD CHRGLEDx(67) x 0 (default) 0 Off 1 x x Off 1 1 On 0 1 Off 0 Notes 67. “x” represents R or G The general purpose LED drivers, CHRGLEDR, and CHRLEDG are independent current sink channels.
Functional Block Description Table 84. General Purpose LED Drivers Period Control CHRGLEDxPER[1:0] Repetition Rate Units 00 256 Hz 01 8.0 Hz 10 1.0 Hz 11 1/2 Hz Table 85. LED Driver Electrical Specifications Characteristics noted under conditions BP = 3.6 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Absolute Accuracy - - 30 % Matching - At 1.
Functional Block Description GND ID Detect To/From Mini-USB Connector ID VBUS VBUS Detect M0 VUSB Regulator M1 MOTG VINUSB VUSB VINUSB2 VUSB2 Regulator VUSB2 TXD RXD To/From Application Processor To/From Audio IC D+ DP UART Switches D- USB Switches SPKR SPKRL MIC Audio Switches DM SWBST (5.0 V boosted supply) 3.3 V USB Analog supply BP 2.5V USB Analog supply To/from Mini-USB Connector VBUS Figure 20. USB Interface 7.8.4.
Functional Block Description will reset to a 1, when either RESETB is valid or VBUS is invalid. This allows the VUSBEN regulator to be enabled automatically if the VUSB regulator was disabled by software. With PUMS4:1 equal to [0100], the VUSBEN bit will be enabled in the power up sequence. The MC34708 also supports USB OTG mode by supplying 5.0 V to the VBUS pin. The OTGEN SPI bit along with the VUSBSEL SPI bit, control switching the SWBST to drive VBUS in OTG mode.
Functional Block Description what ID resistor is attached and the Power Supply Type Identification or PSTI circuit will determine what type of power supply is connected. The 32 kHz crystal must be placed across the XTAL 1 and XTAL2 pins for the accessory identification to work. An identification conclusion is made when the identification flow is finished.
Functional Block Description Reset VBUS_DET? Yes No Yes Standby Detection Delay ID_FLOAT? ID_FLOAT? No No RID < 100? No Yes DP 0.6V ID_DET_EN D? ADC = 00000 No DM > 0.8V Yes RID = 75? Yes No Video cable? No DM < 0.4V? Yes USB-OTG No UART jig cable w/o boot option Yes RID = UART jig w/o boot? No Phone Powered Device Yes RID = 102k? No ID_FLOAT Yes ID_FLOAT? DM 0.
Functional Block Description Figure 22. Stuck Key Process Flow Diagram 7.8.4.5 Power Supply Type Identification The PSTI (Power Supply Type Identification) circuit is used in Active mode to identify the type of the connected power supply. The PSTI circuit first detects whether the DP and DM pins are shorted. If the DP and DM pins are found to be shorted, the PSTI circuit will continue to determine whether DP and DM pins are a forward short or reverse short.
Functional Block Description Figure 23. Power Supply Type Identification Circuit Block Diagram Figure 24.
Functional Block Description Table 92. Timing Delays for PSTI Circuit Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max • TD = 0000 - 100 - • TD = 0001 - 200 - • TD = 0010 - 300 - • TD = 0011 - 400 - • TD = 0100 - 500 - • ... ... ... ...
Functional Block Description Figure 25. Operating Waveforms of the Wait Bit 7.8.4.6.2 Automatic Switching OR Manual Switching (Switch_open & Manual S/W Bits) When a supported accessory is identified, the default behavior of the MC34708 automatically turns on the corresponding signal switches. The user can also choose to turn on optional signal switches manually.
Functional Block Description Type 1 and other accessories will not be affected by the RAW DATA bit. LKR and the button bits will not set when RAW DATA = 0. The period of ADC conversion is determined by the Device Wake-up bits in the Timing Set 1 register. All other behaviors of Audio Type 1 and other accessories will not be affected by the RAW DATA bit. 7.8.4.7 Analog and Digital Switches The signal switches in the MC34708 are shown in Figure 26.
Functional Block Description Table 93. Switch Configuration When Controlled by the Device Type Register Device Type Audio USB UART USB CHG Dedicated CHG On SW# 4, 5, 7 3, 6, 1, 2 3, 6 - Off SW MOTG, M0 - (69) - - Device Type 5WT1 CHG 5WT2 CHG JIG_USB_ON JIG_UART_ON TTY JIG_USB_OFF JIG_UART 3, 6 3, 6 4, 5, 7 - (69) MOTG, M0 On SW# Off SW - - Notes 69. Switches M0, M1, and MOTG are controlled by software by the OTGEN and VUSBSEL bits. 7.8.4.
Functional Block Description Baseband VBUS MIC VBUS SPKR_R DP D+ SPKR_L DM D- ID ID ADC ID Det GND AUDIO ACCESSORY GND SHLD Figure 28.
Functional Block Description 7.8.4.9 JiG Cable USB and UART The JIG cable is used for test and development and has an ID resistance to differentiate it from a regular USB cable. The Jig cable has 2 ID resistance values to resemble a USB JIG type1/2, and 2 ID resistance values to resemble a UART JIG type1/2 cable. 7.8.4.9.
Functional Block Description Baseband UART Cable VBUS Det UART VBUS RxD DP D+ TxD DM D- ID ID ADC ID Det GND UART Interface VBUS ` GND SHLD Figure 30. UART Operation 7.8.4.12 USB Host (PC or HUB) Operation Mode When the attached accessory is a USB host or hub, the ID pin floats. During normal operation, when setting the control bits, both the D PLUS to DP and the D MINUS to DM switches are switched on (see Figure 31).
Functional Block Description 7.8.4.14 5-Wire Charger or A/V Charger Mode When the attached accessory is a 5-Wire Charger or A/V Charger, the MC34708 enables the appropriate device type 5.0 W CHG or A/V in the USB device type register. The VBUS detector is used to monitor the detachment of the charger. The falling edge of USBDETS is an indication of the charger detachment. Both unplugging the mini-USB connector and unplugging the ac side lead to the same detachment conclusion.
Functional Block Description Table 95. ID Resistance Assignment Item# ADC Result ID Resistance K Assignment 5 00101 4.820 S4 6 00110 6.03 S5 7 00111 8.03 S6 8 01000 10.03 S7 9 01001 12.03 S8 10 01010 14.46 S9 11 01011 17.26 S10 12 01100 20.5 S11 13 01101 24.07 S12 14 01110 28.7 UART JIG Cable 2 15 01111 34.0 UART JIG Cable 1 16 10000 40.2 USB JIG Cable 2 17 10001 49.9 USB JIG Cable 1 18 10010 64.9 Factory Mode 19 10011 80.
Functional Block Description Table 96. ID Remote Control Values 7.8.4.19 Resistor Standard Value K ID Resistance R1 2.0 2.0 R2 0.604 2.604 R3 0.604 3.208 R4 0.806 4.014 R5 0.806 4.82 R6 1.21 6.03 R7 2.0 8.03 R8 2.0 10.03 R9 2.0 12.03 R10 2.43 14.46 R11 2.8 17.26 R12 3.24 20.5 R13 3.57 24.07 R14 590/976 614/1000 USB Interface Electrical Specifications Table 97. USB Interface Electrical Characteristics Characteristics noted under conditions BP = 3.
Functional Block Description Table 97. USB Interface Electrical Characteristics Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max • On resistance - - 60 • On resistance flatness (from 0.0 to 3.3 V) - - 6.0 RxD and TxD Switches RUART_ON RUART_ONFLT RMIC_ON RPD_AUDIO - 75 150 - 100 - - - 1.
Functional Block Description Table 97. USB Interface Electrical Characteristics Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.
Functional Block Description For each MOSI SPI transfer, first a one is written to the write/read_b bit if this SPI transfer is to be a write. A zero is written to the write/read_b bit if this is to be a read command. If a zero is written, then any data sent after the address bits are ignored and the internal contents of the field addressed do not change when the 32nd CLK is sent. For a SPI write, the first bit sent to the MC34708 must be a one, indicating a SPI write cycle.
Functional Block Description 7.9.1.2 SPI Timing Requirements The following diagram and table summarize the SPI timing requirements. The SPI input and output levels are set via the SPIVCC pin, by connecting it to the desired supply. This would typically be tied to SW5 and programmed for 1.80 V. The strength of the MISO driver is programmable through the SPIDRV [1:0] bits. See Thermal Protection Thresholds for detailed SPI electrical characteristics.
Functional Block Description 7.9.2 7.9.2.1 I2C Interface I2C Configuration When configured for I2C mode, the interface may be used to access the complete register map previously described for SPI access. Since SPI configuration is more typical, references within this document will generally refer to the common register set as a “SPI map” and bits as “SPI bits”; however, it should be understood that access reverts to I2C mode when configured as such.
Functional Block Description Packet Type Device Address Register Address 7 Host SDA (to MISO) START 0 7 0 0 0 Continuation 0 R/W Slave SDA (from MISO) A C K Packet Type Host SDA (to MISO) Master Driven Data ( byte 2 ) 23 A C K Master Driven Data ( byte 1 ) 16 Host can also drive another Start instead of Stop Master Driven Data ( byte 0 ) 15 8 7 0 STOP A C K Slave SDA (from MISO) A C K A C K Figure 36.
Functional Block Description SPI/I2C Specification 7.9.3 Table 100. SPI/I2C Electrical Characteristics Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, - 40 C TA 85 C, unless otherwise noted. Typical values at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes SPI Interface Logic IO VINCSLO Input Low CS 0.0 - 0.4 V VINCSHI Input High CS 1.1 - SPIVCC+0.3 V 0.0 - 0.3*SPIVCC V 0.
Functional Block Description Table 101.
Functional Block Description 7.10.3 SPI/I2C Register Map The complete SPI bitmap is given in Table 103. Table 103.
Functional Block Description Table 104.
Functional Block Description Table 104.
Functional Block Description Table 104.
Functional Block Description Table 104.
Functional Block Description Table 104.
Functional Block Description Table 104.
Functional Block Description Table 104.
Functional Block Description 7.10.4 SPI Register’s Bit Description Table 105.
Functional Block Description Table 106. Interrupt Mask 0 Name Bit # R/W Reset Default Description ADC_CHANGE_M 21 R/W RESETB 0x1 VBUS power supply type identification completed mask STUCK_KEY_M 22 R/W RESETB 0x1 ID resistance detection finished mask STUCK_KEY_RCV_M 23 R/W RESETB 0x1 For future use Table 107.
Functional Block Description Table 108.
Functional Block Description Table 109. Register 4, Interrupt Mask 1 Name Bit # R/W Reset Default Description Reserved 22 R NONE 0x0 Reserved Unused 23 R 0x1 Not available Table 110.
Functional Block Description Table 112. Register 7, Identification Name Bit # R/W Reset Default FAB[2:0] 11-9 R NONE X Unused 18-12 R PAGE[4:0] 23-19 R/W DIGRESETB Description FAB version Pass 2.4 = 000 0x0 Not available 0x0 SPI Page Table 113.
Functional Block Description Table 118.
Functional Block Description Table 120. Register 15, Power Control 2 Name Bit # R/W Reset Default Description CLK32KDRV[1:0] 18-17 R/W RTCPORB 0x01 CLK32K and CLK32KMCU drive strength (master control bits) Unused 20-19 R 0x00 Not available ON_STBY_LP 21 R/W RESETB 0x0 On Standby Low Power Mode 0 = Low power mode disabled 1 =Low power mode enabled STBYDLY[1:0] 23-22 R/W RESETB 0x01 Standby delay control Table 121.
Functional Block Description Table 127. Register 22, RTC Day Name Bit # R/W DAY[14:0] 14-0 R/W Unused 23-15 R Reset Default Description RTCPORB (79) 0x0000 Day counter 0x000 Not available Notes 79. Reset by RTCPORB but not during a GLBRST (global reset) Table 128. Register 23, RTC Day Alarm Name Bit # R/W DAYA[14:0] 14-0 R/W Unused 23-15 R Reset Default Description RTCPORB (80) 0x7FFF Day alarm 0x000 Not available Notes 80.
Functional Block Description Table 132. Register 27, Regulator 5 Voltage Name Bit # R/W Reset Default SW5[4:0] 4-0 R/WM NONE * SW4 setting in normal mode Unused 9-5 R * Not available * SW5 setting in Standby mode SW5STBY[4:0] Unused 14-10 R/WM 23-15 NONE R 0x000 Description Not available Table 133.
Functional Block Description Table 135. Register 30, Regulator Setting 0 Name Bit # R/W Reset Default VGEN1[2:0] 2-0 R/WM RESETB * Unused 3 R VDAC[1:0] 5-4 R/WM VGEN2[2:0] 8-6 VPLL[1:0] 10-9 VUSB2[1:0] Unused Description VGEN1 setting 0x0 Not available RESETB * VDAC setting R/WM RESETB * VGEN2 setting R/WM RESETB * VPLL setting 12-11 R/WM RESETB * VUSB2 setting 23-13 R 0x000 Not available Table 136.
Functional Block Description Table 137. Register 32, Regulator Mode 0 Name Bit # R/W Reset Default Description VUSB2STBY 19 R/W RESETB 0x0 VUSB2 controlled by standby VUSB2MODE 20 R/W RESETB 0x0 VUSB2 operating mode Unused 23-21 R 0x0 Not available Table 138.
Functional Block Description Table 138. Register 33, GPIOLV0 Control Name Bit # R/W Reset Default Description SRE[1:0] 15-14 R/W RESETB 0x0 Slew rate enable 00: slow (default) 01: normal 10: fast 11: very fast Unused 23-16 R 0x00 Not available Table 139.
Functional Block Description Table 139. Register 34, GPIOLV1 Control Name Bit # R/W Reset Default Description SRE[1:0] 15-14 R/W RESETB 0x0 Slew rate enable 00: slow (default) 01: normal 10: fast 11: very fast Unused 23-16 R 0x00 Not available Table 140.
Functional Block Description Table 140. Register 35, GPIOLV2 Control Name Bit # R/W Reset Default Description SRE[1:0] 15-14 R/W RESETB 0x0 Slew rate enable 00: slow (default) 01: normal 10: fast 11: very fast Unused 23-16 R 0x00 Not available Table 141.
Functional Block Description Table 141. Register 36, GPIOLV3 Control Name Bit # R/W Reset Default Description SRE[1:0] 15-14 R/W RESETB 0x0 Slew rate enable 00: slow (default) 01: normal 10: fast 11: very fast Unused 23-16 R 0x00 Not available Table 142.
Functional Block Description Table 142. Register 37, USB timing Name Bit # R/W Unused 22-20 R READVALID 23 R Reset Default Description 0x0 Not available MUSBRSTB 0x0 Read data valid 0: Data not valid 1: Data valid Table 143.
Functional Block Description Table 144. Register 39, USB Control Name Bit # R/W Reset Default Description SWITCH_OPEN 3 R/W MUSBRSTB 0x1 Switch connection selection 0: Open all switches 1: Switch selection according to the Manual S/W bit. RESET 4 RWM MUSBRSTB 0x0 Soft reset. When written to 1, the IC is reset. Once the reset is complete, the RST bit is set and the RESET bit is cleared automatically.
Functional Block Description Table 145.
Functional Block Description Table 147. Register 43, ADC 0 Name Bit # R/W Reset Default Description TSEN 12 R/W DIGRESETB 0x0 Enable the Touch screen from low power mode. TSSTART 13 R/W DIGRESETB 0x0 Request a start of the ADC Reading Sequencer for Touch screen readings. TSCONT 14 R/W DIGRESETB 0x0 Run ADC reads of Touch screen continuously when high or one time when low.
Functional Block Description Table 149. Register 45, ADC 2 Name Bit # R/W Reset Default Description ADSEL4[3:0] 19-16 R/W DIGRESETB 0x0 Channel Selection to place in ADRESULT4 ADSEL5[3:0] 23-20 R/W DIGRESETB 0x0 Channel Selection to place in ADRESULT5 Table 150.
Functional Block Description Table 153. Register 49, ADC6 Name Bit # R/W Reset Default Unused 1-0 R ADRESULT4[9:0] 11-2 R Unused 13-12 R ADRESULT5[9:0} 23-14 R DIGRESETB 0x000 Reset Default 0x0 DIGRESETB 0x000 0x0 Description Not available ADC Result for ADSEL4 Not available ADC Result for ADSEL5 Table 154.
Functional Block Description Table 157. Register 53, VBUS Monitoring Name Bit # R/W Reset Default Description VBUSTL[2:0] 2-0 R/W RESETB 0x3 VBUS threshold low VBUSTH[2:0] 5-3 R/W RESETB 0x3 VBUS threshold high Reserved 23-6 R/W NONE 0x00000 Reserved Table 158.
Typical Applications 8 Typical Applications Figure 38 presents a typical application diagram of the MC34708 PMIC together with its functional components. For details on component references and additional components such as filters, refer to the individual sections. 8.1 Application Diagram BP C1 10u C2 10u BP VCOREDIG D2 Input/Battery Monitoring ADIN9 General Purpose ADC Inputs: i.e., PA thermistor, Light Sensor, Etc.
Typical Applications 8.2 Bill of Material The following table provides a complete list of the recommended components on a full featured system using the MC34708 Device. Critical components such as inductors, transistors, and diodes are provided with a recommended part number, but equivalent components may be used. Table 161.
Typical Applications Table 161. MC34708 Bill of Material (83) Item Quantity Component Description Vendor Comments SW1 24 2 L2, L3 1.0 H VLS201612ET-1R0N TDK Buck 1 Inductor (IMAX < 1.6 Amps) 1.0 H VLS252010ET-1R0N TDK Optional dual phase Inductor (IMAX 2.0 Amps) 1.0 H BRL3225T1ROM Taiyo Yuden Optional single Phase inductor (IMAX < 1.6 Amps) 1.0 uH LPS4012-102NL Coilcraft Optional single phase inductor (IMAX 2.0 Amps) 25 2 C6, C7 22 F Buck 1 Output Capacitor 26 1 C5 4.
Typical Applications Table 161. MC34708 Bill of Material (83) Item Quantity Component 49 1 D14 Diode BAS3010-03LRH 1 C30 2.2 F VPLL 51 1 C35 100 nF VREFDDR input capacitor 52 1 C57 100 nF VHALF 0.1 uF caps 53 1 C28 1.0 F VREFDDR 1 Q3 Description Vendor Infineon Comments SW5LX diode VPLL 50 VREFDDR VDAC PNP Transistor 54 • NSS12100UW3 • 2SB1733 55 1 C36 56 1 R23 1 Q1 On Semi Rohm VDAC PNP 2.
Typical Applications Table 161. MC34708 Bill of Material (83) Item Quantity Component 66 1 D15 Schottky diode Low voltage Schottky diode 67 1 C58 100 nF LDO input capacitor 68 1 C59 100 nF LDO output capacitor Description Vendor Comments Notes 83. Freescale does not assume liability, endorse, or warrant components from external manufacturers referenced in circuit drawings or tables.
Typical Applications 8.3 MC34708 Layout Guidelines 8.3.1 1. • • • • • • • • General board recommendations It is recommended to use an 8 layer board stack-up arranged as follows: High current signal GND Signal Power Power Signal GND High current signal 2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTING (high current signals), copper-pour the unused area. 3. Use internal layers sandwiched between two GND planes for the SIGNAL routing. 8.3.
Typical Applications Figure 39. Recommended Shielding for Critical Signals. • These signals can be placed on an outer layer of the board to reduce their capacitance in respect to the ground plane. • The crystal connected to the XTAL1 and XTAL2 pins must not have a ground plane directly below. • The following are clock signals: CLK, CLK32K, CLK32KMCU, XTAL1, and XTAL2. These signals must not run parallel to each other, or in the same routing layer.
Typical Applications BP SWxVIN CIN_HF Diver Controller CIN SWx SWxLX L D COUT GNDSWx Compensation SWxFB Figure 40. Generic Buck Regulator Architecture Figure 41. Recommended Layout for Switching Regulators.
Typical Applications 8.4 8.4.1 Thermal Considerations Rating Data The thermal rating data of the packages has been simulated with the results listed in Table 5. Junction to Ambient Thermal Resistance Nomenclature: the JEDEC specification reserves the symbol RθJA or θJA (Theta-JA) strictly for junction-to-ambient thermal resistance on a 1s test board in natural convection environment.
Package Mechanical Dimensions 9 Package Mechanical Dimensions The MC34708 is offered in two pin compatible 206 pin MAPBGA packages, an 8.0x8.0 mm, 0.5 mm pitch package, and a 13x13 mm, 0.8 mm pitch package. Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number. Table 162. Package Drawing Information Package Suffix 206-pin MAPBGA (8 x 8), 0.
Package Mechanical Dimensions 9.1 206-pin MAPBGA (8 x 8), 0.
Package Mechanical Dimensions VK SUFFIX (PB-FREE) 206-PIN 98ASA00312D ISSUE 0 MC34708 153 Analog Integrated Circuit Device Data Freescale Semiconductor
Package Mechanical Dimensions 9.2 206-pin MAPBGA (13 x 13), 0.
Package Mechanical Dimensions VM SUFFIX (PB-FREE) 206-PIN 98ASA00299D ISSUE A MC34708 155 Analog Integrated Circuit Device Data Freescale Semiconductor
Reference Section 10 Reference Section Table 163.
Revision History 11 Revision History . REVISION DATE DESCRIPTION OF CHANGES 6.0 7/2011 • Initial release 7.0 10/2011 • • • • • • • • • • • 8.0 7/2012 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Corrected the two pins SW2PWGD and SDWNB, and associated drawings. Changed LED Driver Electrical Specifications, VPLL Matching from 3.0 to 4.0% Changed VPLL Electrical Specification, tON-VPLL from 100 to 120 s Changed SWBST Electrical Specifications, ILEAK_SWBST from 5.0 to 6.
Revision History REVISION DATE 9.0 10/2012 10 2/2013 DESCRIPTION OF CHANGES • Corrected pins E14, E15, and F7 in Table 3 • Corrected Figure 3, Ball Map. • Update table 3. Pin definition • Pin TRICKLESEL, Function = I, Description = Connect to VCOREDIG • Pin PRETMR, Function = I, Description = Connect to Ground • Pin BPTHERM, Function = I, Description = Connect to Ground • Update Table 4. Maximum rating • Update IC core Reference maximum pin voltages. • Update LDO regulator maximum pin voltage.
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