UM10237 LPC24XX User manual Rev. 02 — 19 December 2008 User manual Document information Info Content Keywords LPC2400, LPC2458, LPC2420, LPC2460, LPC2468, LPC2470, LPC2478, ARM, ARM7, 32-bit, Single-chip, External memory interface, USB 2.
UM10237 NXP Semiconductors LPC24XX User manual Revision history Rev Date Description 02 20081219 LPC24XX user manual release. Modifications: • • • 01 20080718 Added parts LPC2420. Editorial updates. AHB1 and AHB2 configuration registers added. Initial LPC24XX user manual release. Replaces all draft versions UM10237_1.00 to UM10237_1.05. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.
UM10237 Chapter 1: LPC24XX Introductory information Rev. 02 — 19 December 2008 User manual 1. Introduction NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and embedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speed Flash memory.
UM10237 NXP Semiconductors Chapter 1: LPC24XX Introductory information Most features and peripherals are identical for all LPC2400 parts. All differences are listed in Table 1–2. Table 2. Differences between LPC2400 parts Pins/ High-speed GPIO pins Flash EMC LCD LPC2458 180/136 512 kB 16-bit no LPC2460/20 208/160 flashless 32-bit no LPC2468 208/160 512 kB 32-bit no LPC2470 208/160 flashless 32-bit yes LPC2478 208/160 512 kB 32-bit yes 3.
UM10237 NXP Semiconductors Chapter 1: LPC24XX Introductory information – SPI controller. – Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller. – Three I2C-bus interfaces (one with open-drain and two with standard port pins). – I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA. • Other peripherals: – SD/MMC memory card interface.
UM10237 NXP Semiconductors Chapter 1: LPC24XX Introductory information • Boundary scan for simplified board testing. • Versatile pin function selections allow more possibilities for using on-chip peripheral functions. 4. Applications • • • • Industrial control Medical systems Protocol converter Communications 5. Ordering options 5.1 LPC2458 ordering options Table 3.
UM10237 NXP Semiconductors Chapter 1: LPC24XX Introductory information DAC channels LPC2420FBD208 N/A 64 - 16 2 LPC2460FBD208 N/A LPC2460FET208 N/A External bus SD/ GP MMC DMA Temp range 82 Full 32-bit - yes - yes yes 8 1 −40 °C to +85 °C 64 16 16 2 98 Full 32-bit MII/RMII yes 2 yes yes 8 1 −40 °C to +85 °C 64 16 16 2 98 Full 32-bit MII/RMII yes 2 yes yes 8 1 −40 °C to +85 °C CAN channels USB OTG/ OHCI/ DEV + 4 kB FIFO RTC SRAM (kB) GP/USB Flash (kB) Etherne
UM10237 NXP Semiconductors Chapter 1: LPC24XX Introductory information Table 10.
UM10237 NXP Semiconductors Chapter 1: LPC24XX Introductory information The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1.
UM10237 NXP Semiconductors Chapter 1: LPC24XX Introductory information 8. On-chip SRAM The LPC2400 includes a SRAM memory of 64 kB reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits. A 16 kB SRAM block serving as a buffer for the Ethernet controller and a 16 kB SRAM associated with the second AHB bus can be used both for data and code storage, too.
UM10237 NXP Semiconductors Chapter 1: LPC24XX Introductory information 9.
UM10237 NXP Semiconductors Chapter 1: LPC24XX Introductory information 10.
UM10237 NXP Semiconductors Chapter 1: LPC24XX Introductory information 11.
UM10237 NXP Semiconductors Chapter 1: LPC24XX Introductory information 12.
UM10237 NXP Semiconductors Chapter 1: LPC24XX Introductory information 13.
UM10237 Chapter 2: LPC24XX Memory mapping Rev. 02 — 19 December 2008 User manual 1. How to read this chapter The memory addressing and mapping for different LPC2400 parts depends on flash size, EMC size, and the LCD peripheral, see Table 2–13. Table 13.
UM10237 NXP Semiconductors Chapter 2: LPC24XX Memory mapping Table 15.
UM10237 NXP Semiconductors Chapter 2: LPC24XX Memory mapping Table 16.
UM10237 NXP Semiconductors Chapter 2: LPC24XX Memory mapping 4.0 GB 0xFFFF FFFF AHB PERIPHERALS 3.75 GB 0xF000 0000 APB PERIPHERALS 3.5 GB 0xE000 0000 EXTERNAL STATIC AND DYNAMIC MEMORY 2.0 GB BOOT ROM AND BOOT FLASH 0x8000 0000 0x7FFF FFFF RESERVED ADDRESS SPACE 1.0 GB ON-CHIP STATIC RAM SPECIAL REGISTERS 0x4000 0000 0x3FFF FFFF 0x3FFF 8000 RESERVED ADDRESS SPACE ON-CHIP NON-VOLATILE MEMORY OR RESERVED 0.0 GB Fig 6. 0x0000 0000 LPC2400 system memory map UM10237_2 User manual © NXP B.
UM10237 NXP Semiconductors Chapter 2: LPC24XX Memory mapping 4.0 GB 0xFFFF FFFF AHB PERIPHERALS 0xFFE0 0000 0xFFDF FFFF 4.0 GB - 2 MB RESERVED 0xF000 0000 0xEFFF FFFF 3.75 GB RESERVED 0xE020 0000 0xE01F FFFF 3.5 GB + 2 MB APB PERIPHERALS 0xE000 0000 3.5 GB Fig 7. Peripheral memory map Figure 8 and Table 2–17 show different views of the peripheral address space. Both the AHB and APB peripheral areas are 2 megabyte spaces which are divided up into 128 peripherals.
UM10237 NXP Semiconductors Chapter 2: LPC24XX Memory mapping All peripheral register addresses are word aligned (to 32 bit boundaries) regardless of their size. This eliminates the need for byte lane mapping hardware that would be required to allow byte (8 bit) or half-word (16 bit) accesses to occur at smaller boundaries. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately.
UM10237 NXP Semiconductors Chapter 2: LPC24XX Memory mapping 4. APB peripheral addresses The following table shows the APB address map. No APB peripheral uses all of the 16 kB space allocated to it. Typically each device’s registers are "aliased" or repeated at multiple locations within each 16 kB range. Table 17.
UM10237 NXP Semiconductors Chapter 2: LPC24XX Memory mapping 5. LPC2400 memory re-mapping and boot ROM 5.1 Memory map concepts and operating modes The basic concept on the LPC2400 is that each memory area has a "natural" location in the memory map. This is the address range for which code residing in that area is written. The bulk of each memory space remains permanently fixed in the same location, eliminating the need to have portions of the code designed to run in different address ranges.
UM10237 NXP Semiconductors Chapter 2: LPC24XX Memory mapping Table 19. LPC2400 Memory mapping modes Mode Activation Usage Boot Loader mode Hardware activation by any Reset The Boot Loader always executes after any reset. The Boot ROM interrupt vectors are mapped to the bottom of memory to allow handling exceptions and using interrupts during the Boot Loading process. A sector of the flash memory (the Boot flash) is available to hold part of the Boot Code.
UM10237 NXP Semiconductors Chapter 2: LPC24XX Memory mapping Re-mapped memory areas, including the Boot ROM and interrupt vectors, continue to appear in their original location in addition to the re-mapped address. Details on re-mapping and examples can be found in Section 2–6 “Memory mapping control” on page 25. 6. Memory mapping control The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000.
UM10237 NXP Semiconductors Chapter 2: LPC24XX Memory mapping read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. In case of MEMMAP[1:0] = 00 (Boot Loader Mode), read/fetch from 0x0000 0008 will provide data available also at 0x7FFF E008 (Boot ROM remapped from on-chip Bootloader). 2.0 GB EXTERNAL MEMORY INTERRUPT VECTORS 8 kB BOOT ROM 2.0 GB - 8 kB (BOOT ROM INTERRUPT VECTORS) 2.0 GB - 64 kB 2.
UM10237 NXP Semiconductors Chapter 2: LPC24XX Memory mapping 7. Prefetch abort and data abort exceptions The LPC2400 generates the appropriate bus cycle abort exception if an access is attempted for an address that is in a reserved or unassigned address region. The regions are: • Areas of the memory map that are not implemented for a specific ARM derivative. For the LPC2400, these are: – Address space between On-Chip Non-Volatile Memory and the Special Register space.
UM10237 Chapter 3: LPC24XX System control Rev. 02 — 19 December 2008 User manual 1. Summary of system control block functions The System Control Block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include: • • • • • Reset Brown-Out Detection External Interrupt Inputs Miscellaneous System Controls and Status Code Security vs.
UM10237 NXP Semiconductors Chapter 3: LPC24XX System control Table 23.
UM10237 NXP Semiconductors Chapter 3: LPC24XX System control Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise event that was just triggered by activity on the EINT pin will not be recognized in future. Important: whenever a change of external interrupt operating mode (i.e.
UM10237 NXP Semiconductors Chapter 3: LPC24XX System control 3.1.3 External Interrupt Mode register (EXTMODE - 0xE01F C148) The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins that are selected for the EINT function (see Section 9–5.5) and enabled in the VICIntEnable register (Section 7–3.
UM10237 NXP Semiconductors Chapter 3: LPC24XX System control Table 27. External Interrupt Polarity register (EXTPOLAR - address 0xE01F C14C) bit description Bit Symbol 0 1 2 3 Value Description Reset value EXTPOLAR0 0 EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0). 1 EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0). EXTPOLAR1 0 EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1).
UM10237 NXP Semiconductors Chapter 3: LPC24XX System control external reset Reset to the on-chip circuitry C watchdog reset Q Reset to PCON.PD S POR BOD WAKEUP TIMER START power down EINT0 wakeup EINT1 wakeup COUNT 2 n C Q internal RC oscillator S write “1” from APB EINT2 wakeup EINT3 wakeup RTC wakeup BOD wakeup Ethernet MAC wakeup reset APB read of PDBIT in PCON USB need_clk wakeup CAN wakeup GPIO0 port wakeup GPIO2 port wakeup FOSC to other blocks Fig 10.
UM10237 NXP Semiconductors Chapter 3: LPC24XX System control IRC starts IRC stable IRC status RESET VDD(3V3) valid threshold GND 30 μs 1 μs; IRC stability count boot time supply ramp-up time 8 μs user code 160 μs 170 μs processor status flash read starts flash read finishes boot code execution finishes; user code starts 002aad482 Fig 11. Example of start-up after reset The various Resets have some small differences.
UM10237 NXP Semiconductors Chapter 3: LPC24XX System control Table 28. Reset Source Identification register (RSID - address 0xE01F C180) bit description Bit Symbol Description Reset value 0 POR Assertion of the POR signal sets this bit, and clears all of the other bits in See text this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset.
UM10237 NXP Semiconductors Chapter 3: LPC24XX System control Table 29. System Controls and Status register (SCS - address 0xE01F C1A0) bit description Bit Symbol Value Description Access Reset value 2 - - Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA NA 3 MCIPWR Active Level[1] MCIPWR pin control. R/W 0 R/W 0 R/W 0 RO 0 - NA 4 5 6 The MCIPWR pin is low. 1 The MCIPWR pin is high.
UM10237 NXP Semiconductors Chapter 3: LPC24XX System control Table 31. Bit Symbol Value Description Reset value 0 scheduler 0 Priority scheduling. 1 1 Uniform (round-robin) scheduling. 00 Break all defined length bursts (the CPU does not create defined bursts). 01 Break all defined length bursts greater than four-beat. 10 Break all defined length bursts greater than eight-beat. 11 Never break defined length bursts. 0 A quantum is an AHB clock. 1 A quantum is an AHB bus cycle.
UM10237 NXP Semiconductors Chapter 3: LPC24XX System control Table 32. Priority sequence (bit 0 = 0): LCD, CPU, GPDMA, AHB1, USB Bit Symbol Description Priority value nnn Priority sequence 14:12 EP1 18:16 EP2 CPU 100 (4) 2 GPDMA 011 (3) 3 22:20 EP3 AHB1 010 (2) 4 26:24 EP4 USB 001 (1) 5 30:28 EP5 LCD 101 (5) 1 Table 33.
UM10237 NXP Semiconductors Chapter 3: LPC24XX System control Table 36. Bit Symbol Value Description Reset value 0 scheduler 0 Priority scheduling. 1 1 Uniform (round-robin) scheduling. 00 Break all defined length bursts (the CPU does not create defined bursts). 01 Break all defined length bursts greater than four-beat. 10 Break all defined length bursts greater than eight-beat. 11 Never break defined length bursts. 0 A quantum is an AHB clock. 1 A quantum is an AHB bus cycle.
UM10237 NXP Semiconductors Chapter 3: LPC24XX System control Table 38. Priority sequence (bit 0 = 0): Ethernet, CPU Bit Symbol Description Priority value nn Priority sequence 13:12 EP1 CPU 00 2[1] 18:16 EP2 Ethernet 00 1[1] [1] Sequence based on round-robin. 4. Brown-out detection The LPC2400 includes 2-stage monitoring of the voltage on the VDD(3V3) pins. If this voltage falls below 2.95 V, the Brown-Out Detector (BOD) asserts an interrupt signal to the Vectored Interrupt Controller.
UM10237 Chapter 4: LPC24XX Clocking and power control Rev. 02 — 19 December 2008 User manual 1. Summary of clocking and power control functions This section describes the generation of the various clocks needed by the LPC2400 and options of clock source selection, as well as power control and wakeup from reduced power modes.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control EXTERNAL ETHERNET PHY usbclk (48 MHz) USB CLOCK DIVIDER MAIN OSCILLATOR PLL INTERNAL RC OSCILLATOR BYPASS SYNCHRONIZER 25 or 50 MHz USB clock config (USBCLKCFG) pllclk system clock select (CLKSRCSEL) USB BLOCK cclk CPU CLOCK DIVIDER CPU clock config (CCLKCFG) ARM7 TDMI-S ETHERNET BLOCK EMC, LCD, DMA, FAST I/O VIC WATCHDOG TIMER WDT clock select (WDTCLKSEL) CCLK/8 PERIPHERAL CLOCK GENERATOR CCLK/6 CCLK/4 CCLK/2 other
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control 2. Oscillators The LPC2400 includes three independent oscillators. These are the Main Oscillator, the Internal RC Oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following Reset, the LPC2400 will operate from the Internal RC Oscillator until switched by software.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control LPC24xx XTAL1 LPC24xx XTAL2 XTAL1 XTAL2 L <=> CC CL CP Xtal Clock CX1 a) CX2 RS b) c) Fig 13. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external crystal model used for CX1/X2 evaluation Table 39.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control register) so that software can determine when the oscillator is running and stable. At that point, software can control switching to the main oscillator as a clock source. Prior to starting the main oscillator, a frequency range must be selected by configuring the OSCRANGE bit in the SCS register. 2.3 RTC oscillator The RTC oscillator can be used as the clock source for the RTC, and/or the watchdog timer.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control • The IRC oscillator cannot be used as clock source for the USB block. • The IRC oscillator cannot be used as clock source for the CAN controllers if the CAN baud rate is larger than 100 kbit/s. 3.1.1 Clock Source Select register (CLKSRCSEL - 0xE01F C10C) The PCLKSRCSEL register contains the bits that select the clock source for the PLL. Table 42.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control USBSEL[3:0] PLLC PLLE refclk = 1.152 MHz pd pllclkin = 18.432 MHz NSEL[23:16] N-DIVIDER /16 PLOCK PHASEFREQUENCY DETECTOR FILTER 144 MHz 1.152 MHz M-DIVIDER /125 CCO 288 MHz 288 MHz pllclk = 288 MHz USB CLOCK DIVIDER /6 CPU CLOCK DIVIDER /4 usbclk = 48 MHz cclk = 72 MHz /2 MSEL[14:0] CCLKSEL[7:0] Fig 14.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control Table 43. PLL registers Name Description PLLCON PLL Control Register. Holding register for R/W updating PLL control bits. Values written to this register do not take effect until a valid PLL feed sequence has taken place. 0 0xE01F C080 PLLCFG PLL Configuration Register. Holding register for R/W updating PLL configuration values.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control disconnect the PLL if lock is lost during operation. In the event of loss of PLL lock, it is likely that the oscillator clock has become unstable and disconnecting the PLL will not remedy the situation. 3.2.5 PLL Configuration register (PLLCFG - 0xE01F C084) The PLLCFG register contains the PLL multiplier and divider values.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control Table 46. Multiplier values for a 32 kHz oscillator Multiplier (M) Pre-divide (N) FCCO 6836 1 448.0041 6866 1 449.9702 6958 1 455.9995 7050 1 462.0288 7324 1 479.9857 7425 1 486.6048 7690 1 503.9718 7813 1 512.0328 7935 1 520.0282 8057 1 528.0236 8100 1 530.8416 8545 2 280.0026 8789 2 287.9980 9155 2 299.9910 9613 2 314.9988 10254 2 336.0031 10376 2 340.0008 10986 2 359.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control Table 46. Multiplier values for a 32 kHz oscillator Multiplier (M) Pre-divide (N) FCCO 18311 3 400.0099 19226 3 419.9984 19775 3 431.9915 20508 3 448.0041 20599 3 449.9920 20874 3 455.9995 21149 3 462.0070 21973 3 480.0075 23071 3 503.9937 23438 3 512.0109 23804 3 520.0063 24170 3 528.0017 3.2.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control connected for use. The value of PLOCK may not be stable when the PLL reference frequency (FREF, the frequency of REFCLK, which is equal to the PLL input frequency divided by the pre-divider value) is less than 100 kHz or greater than 20 MHz. In these cases, the PLL may be assumed to be stable after a start-up time has passed.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control 3.2.11 PLL frequency calculation The PLL equations use the following parameters: Table 50. PLL frequency parameter Parameter Description FIN the frequency of pllclkin from the Clock Source Selection Multiplexer. FCCO the frequency of the pllclk (output of the PLL Current Controlled Oscillator) N PLL Pre-divider value from the NSEL bits in the PLLCFG register (PLLCFG NSEL field + 1). N is an integer from 1 through 32.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control Table 51. Additional Multiplier Values for use with a Low Frequency Clock Input Low Frequency PLL Multipliers 16479 17578 18127 18311 19226 19775 20508 20599 20874 21149 21973 23071 23438 23804 24170 3.2.12 Procedure for determining PLL settings PLL parameter determination can be simplified by using a spreadsheet available from NXP. To determine PLL parameters by hand, the following general procedure may be used: 1.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control M = (FCCO × N) / (2 × FIN) Start by assuming N = 1, since this produces the smallest multiplier needed for the PLL. So, M = 288 × 106 / (2 × 4 × 106) = 36. Since the result is an integer, there is no need to look further for a good set of PLL configuration values. The value written to PLLCFG would be 0x23 (N - 1 = 0; M - 1 = 35 = 0x23).
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control In general, larger vlaues of FREF result in a more stable PLL when the input clock is a low frequency. Even the first table entry shows a very small error of just over 1 hundredth of a percent, or 107 parts per million (ppm). If that is not accurate enough in the application, the second case gives a much smaller error of 7 ppm.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control 3.3.1 CPU Clock Configuration register (CCLKCFG - 0xE01F C104) The CCLKCFG register controls the division of the PLL output before it is used by the CPU. When the PLL is bypassed, the division may be by 1. When the PLL is running, the output must be divided in order to bring the CPU clock frequency (cclk) within operating limits.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control Table 55. IRC Trim register (IRCTRIM - address 0xE01F C1A4) bit description Bit Symbol Description Reset value 7:0 IRCtrim IRC trim value. It controls the on-chip 4 MHz IRC frequency. 0xA0 15:8 - Reserved. Software must write 0 into these bits. NA 3.3.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control Table 57. Peripheral Clock Selection register 1 (PCLKSEL1 - address 0xE01F C1AC) bit description Bit Symbol Description Reset value 13:12 PCLK_TIMER2 Peripheral clock selection for TIMER2. 00 15:14 PCLK_TIMER3 Peripheral clock selection for TIMER3. 00 17:16 PCLK_UART2 Peripheral clock selection for UART2. 00 19:18 PCLK_UART3 Peripheral clock selection for UART3.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 3.4.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control 3.4.5 Power control register description The Power Control function uses registers shown in Table 4–59. More detailed descriptions follow. Table 59. Power Control registers Name Description Access Reset value[1] Address PCON Power Control Register. This register contains control bits that enable the two reduced power operating modes of the LPC2400. See Table 4–60.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control Table 60. Power Mode Control register (PCON - address 0xE01F C0C0) bit description Bit Symbol Description Reset value 4 BORD Brown-Out Reset Disable. When BORD is 1, the second stage of low voltage detection (2.6 V) will not cause a chip reset. 0 When BORD is 0, the reset is enabled. The first stage of low voltage detection (2.9 V) Brown-Out interrupt is not affected.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control Table 62. Interrupt Wakeup register (INTWAKE - address 0xE01F C144) bit description Bit Symbol Description Reset value 0 EXTWAKE0 When one, assertion of EINT0 will wake up the processor from 0 Power-down mode. 1 EXTWAKE1 When one, assertion of EINT1 will wake up the processor from 0 Power-down mode. 2 EXTWAKE2 When one, assertion of EINT2 will wake up the processor from 0 Power-down mode.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control Some peripherals, particularly those that include analog functions, may consume power that is not clock dependent. These peripherals may contain a separate disable control that turns off additional circuitry to reduce power. Information on peripheral specific power saving features may be found in the chapter describing that peripheral. Each bit in PCONP controls one peripheral as shown in Table 4–63.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control Table 63. Power Control for Peripherals register (PCONP - address 0xE01F C0C4) bit description Bit Symbol Description 27 PCI2S I2S interface power/clock control bit. 0 28 PCSDC SD card interface power/clock control bit. 0 29 PCGPDMA GP DMA function power/clock control bit. 0 30 PCENET Ethernet block power/clock control bit. 0 31 PCUSB USB interface power/clock control bit. 0 [1] Reset value LPC247x only.
UM10237 NXP Semiconductors Chapter 4: LPC24XX Clocking and power control whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wakeup of the processor from Power-down mode makes use of the Wakeup Timer. The Wakeup Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution.
UM10237 Chapter 5: LPC24XX External Memory Controller (EMC) Rev. 02 — 19 December 2008 User manual 1. How to read this chapter This chapter describes the external memory controller for all LPC2400 parts. For EMC configurations that are specific to LPC2458 and LPC2420/60/68/70/78, see Table 5–64. Table 64.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) 3. Pins: Select data, address, and control pins and their modes in PINSEL6/8/9 and PINMODE6/8/9 (see Section 9–5). 4. Configuration: see Table 5–68 to Table 5–71. 3. Introduction The LPC2400 External Memory Controller (EMC) is an ARM PrimeCell™ MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM and Flash, as well as dynamic memories such as Single Data Rate SDRAM.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) EMC A[23:0] D[31:0] shared signals WE AHB Bus AHB SLAVE MEMORY INTERFACE DATA BUFFERS MEMORY CONTROLLER STATE MACHINE PAD INTERFACE OE AHB SLAVE REGISTER INTERFACE BLS[3:0] static memory signals CS[3:0] DYCS[3:0] CAS RAS CLKOUT[1:0] dynamic memory signals CKEOUT[3:0] DQMOUT[3:0] Fig 15.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) 5.2 AHB slave memory interface The AHB slave memory interface allows access to external memories. 5.2.1 Memory transaction endianness The endianness of the data transfers to and from the external memories is determined by the Endian mode (N) bit in the EMCConfig register.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) • If the buffers are enabled, an AHB write operation writes into the Least Recently Used (LRU) buffer, if empty. If the LRU buffer is not empty, the contents of the buffer are flushed to memory to make space for the AHB write data. • If a buffer contains write data it is marked as dirty, and its contents are written to memory before the buffer can be reallocated.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Self-refresh mode can be entered by software by setting the SREFREQ bit in the EMCDynamicControl Register and polling the SREFACK bit in the EMCStatus Register. Any transactions to memory that are generated while the memory controller is in self-refresh mode are rejected and an error response is generated to the AHB bus. Clearing the SREFREQ bit in the EMCDynamicControl Register returns the memory to normal operation.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) 8. Reset The EMC receives two reset signals. One is Power-On Reset (POR), asserted when chip power is applied, and when a brown-out condition is detected (see the System Control Block chapter for details of Brown-Out Detect). The other reset is from the external Reset pin and the Watchdog Timer. A configuration bit in the SCS register, called EMC_Reset_Disable, allows control of how the EMC is reset.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 66. Pad interface and control signal descriptions Name Type Value on POR Value during Description reset self-refresh CLKOUT[1:0] Output Follows CCLK Follows CCLK SDRAM clocks. Used for SDRAM devices. CKEOUT[3:0] Output 0xF 0x0 SDRAM clock enables. Used for SDRAM devices. One is allocated for each Chip Select. DQMOUT[3:0] Output 0xF 0xF Data mask output to SDRAMs. Used for SDRAM devices and static memories.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 67. Summary of EMC registers …continued Address Register Name Description Warm POR Type Reset Reset Value Value [1] [1] 0xFFE0 8124 EMCDynamic RasCas1 Selects the RAS and CAS latencies for dynamic memory chip select 1. 0x303 R/W 0xFFE0 8140 EMCDynamic Config2 Selects the configuration information for dynamic memory chip select 2.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 67. Summary of EMC registers …continued Address Register Name Description Warm POR Type Reset Reset Value Value [1] [1] Selects the delay from chip select 3 or address change, whichever is later, to output enable. - 0x0 R/W 0xFFE0 826C EMCStatic WaitRd3 Selects the delay from chip select 3 to a read access.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 68. EMC Control register (EMCControl - address 0xFFE0 8000) bit description Bit Symbol Value Description 2 Low-power mode (L) Reset Value Indicates normal, or low-power mode: 0 Normal mode (warm reset value). 1 Low-power mode. 0 Entering low-power mode reduces memory controller power consumption. Dynamic memory is refreshed as necessary.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) 10.3 EMC Configuration register (EMCConfig - 0xFFE0 8008) The EMCConfig register configures the operation of the memory controller. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode. This register is accessed with one wait state.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 71. Dynamic Control register (EMCDynamicControl - address 0xFFE0 8020) bit description Bit Symbol Value Description 2 Self-refresh 0 request, 1 EMCSREFREQ (SR) Reset Value Normal mode. 1 Enter self-refresh mode (POR reset value). By writing 1 to this bit self-refresh can be entered under software control. Writing 0 to this bit returns the EMC to normal mode.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) 10.5 Dynamic Memory Refresh Timer register (EMCDynamicRefresh 0xFFE0 8024) The EMCDynamicRefresh register configures dynamic memory operation. It is recommended that this register is modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) 10.6 Dynamic Memory Read Configuration register (EMCDynamicReadConfig - 0xFFE0 8028) The EMCDynamicReadConfig register configures the dynamic memory read strategy. This register must only be modified during system initialization. This register is accessed with one wait state. Note: This register is used for all four dynamic memory chip selects. Therefore the worst case value for all of the chip selects must be programmed.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 74. Dynamic Memory Percentage Command Period register (EMCDynamictRP address 0xFFE0 8030) bit description Bit Symbol Value Description Reset Value 3:0 Precharge command period (tRP) 0x0 0xE n + 1 clock cycles. The delay is in EMCCLK cycles. 0x0F 0xF 16 clock cycles (POR reset value). 31:4 - - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 76. Dynamic Memory Self-refresh Exit Time register (EMCDynamictSREX - address 0xFFE0 8038) bit description Bit Symbol Value Description Reset Value 3:0 Self-refresh exit time (tSREX) 0x0 0xE n + 1 clock cycles. The delay is in CCLK cycles. 0xF 0xF 16 clock cycles (POR reset value). 31:4 - - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 78. Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL address 0xFFE0 8040) bit description Bit Symbol Value Description 3:0 Data-in to active 0x0 command 0xE (tDAL) 0xF n clock cycles. The delay is in CCLK cycles. 31:4 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - Reset Value 0xF 15 clock cycles (POR reset value).
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 80. Dynamic Mempry Active to Active Command Period register (EMCDynamictRC address 0xFFE0 8048) bit description Bit Symbol Value Description Reset Value 4:0 Active to active command period (tRC) 0x0 0x1E n + 1 clock cycles. The delay is in CCLK cycles. 0x1F 0xF 32 clock cycles (POR reset value). 31:5 - - Reserved, user software should not write ones to reserved bits.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 82. Dynamic Memory Exit Self-refresh register (EMCDynamictXSR - address 0xFFE0 8050) bit description Bit Symbol Value Description Reset Value 4:0 Exit self-refresh to active command time (tXSR) 0x0 0x1E n + 1 clock cycles. The delay is in CCLK cycles. 0x1F 0xF 32 clock cycles (POR reset value). - Reserved, user software should not write ones to reserved bits.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 84. Dynamic Memory Load Mode register to Active Command Time (EMCDynamictMRD - address 0xFFE0 8058) bit description Bit Symbol 3:0 0x0 Load mode register to active 0xE command time 0xF (tMRD) 31:4 - Value Description - Reset Value n + 1 clock cycles. The delay is in CCLK cycles. 0xF 16 clock cycles (POR reset value). Reserved, user software should not write ones to reserved bits.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 86. Dynamic Memory Configuration registers (EMCDynamicConfig0-3 - address 0xFFE0 8100, 0xFFE0 8120, 0xFFE0 8140, 0xFFE0 8160) bit description Bit Symbol Value Description Reset Value 2:0 - - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 4:3 Memory device (MD) 00 SDRAM (POR reset value). 00 01 Low-power SDRAM. 10 Micron SyncFlash.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 87.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 87. Address mapping 14 12 11:9 8:7 Description 1 1 011 10 256 MB (8Mx32), 4 banks, row length = 13, column length = 8 1 1 100 00 512 MB (64Mx8), 4 banks, row length = 13, column length = 11 1 1 100 01 512 MB (32Mx16), 4 banks, row length = 13, column length = 10 A chip select can be connected to a single memory device, in this case the chip select data bus width is the same as the device width.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) 10.21 Static Memory Configuration registers (EMCStaticConfig0-3 0xFFE0 8200, 220, 240, 260) The EMCStaticConfig0-3 registers configure the static memory configuration. It is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 89. Static Memory Configuration registers (EMCStaticConfig0-3 - address 0xFFE0 8200, 0xFFE0 8220, 0xFFE0 8240, 0xFFE0 8260) bit description Bit Symbol 7 Byte lane state (PB) Value Description Reset Value The byte lane state bit, PB, enables different types of 0 memory to be connected. For byte-wide static memories the BLSn[3:0] signal from the EMC is usually connected to WE (write enable).
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 5–90 shows the bit assignments for the EMCStaticWaitWen0-3 registers. Table 90. Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3 - address 0xFFE0 8204,0xFFE0 8224, 0xFFE0 8244, 0xFFE0 8264) bit description Bit Symbol 3:0 Wait write enable (WAITWEN) Value 0x0 Description Reset Value Delay from chip select assertion to write enable.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 92. Static Memory Read Delay registers (EMCStaticWaitRd0-3 - address 0xFFE0 820C, 0xFFE0 822C, 0xFFE0 824C, 0xFFE0 826C) bit description Bit Symbol 4:0 Non-page mode read wait states or asynchronous 0x0 page mode 0x1E readfirst access wait state 0x1F (WAITRD) 31:5 - Value Description - Reset Value Non-page mode read or asynchronous page mode read, 0x1F first read only: (n + 1) CCLK cycles for read accesses.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Table 94. Static Memory Write Delay registers0-3 (EMCStaticWaitWr - address 0xFFE0 8214, 0xFFE0 8234, 0xFFE0 8254, 0xFFE0 8274) bit description Bit Symbol 4:0 Write wait states (WAITWR) 31:5 Value Description - Reset Value SRAM wait state time for write accesses after the first read: 0x0 0x1E (n + 2) CCLK cycle write access time. The wait state time for write accesses after the first read is WAITWR (n + 2) x tCCLK.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) Symbol "a_b" in the following figures refers to the highest order address line in the data bus. Symbol "a_m" refers to the highest order address line of the memory chip used in the external memory interface. If the external memory is used as external boot memory for flashless devices, refer to Section 8–6 on how to connect the EMC.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) CS OE WE BLS[3] BLS[2] BLS[1] BLS[0] D[31:0] CE OE WE B3 B2 B1 B0 IO[31:0] A[a_m:0] A[a_b:2] c. 32 bit wide memory bank interfaced to one 8 bit memory chip Fig 16. 32 bit bank external memory interfaces ( bits MW = 10) 11.2 16-bit wide memory bank connection CS OE CE OE WE BLS[1] BLS[0] IO[7:0] A[a_m:0] D[15:8] D[7:0] CE OE WE IO[7:0] A[a_m:0] A[a_b:1] a.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) 11.3 8-bit wide memory bank connection CS OE BLS[0] D[7:0] CE OE WE IO[7:0] A[a_m:0] A[a_b:0] Fig 18. 8 bit bank external memory interface (bits MW = 00) UM10237_2 User manual © NXP B.V. 2008. All rights reserved. Rev.
UM10237 NXP Semiconductors Chapter 5: LPC24XX External Memory Controller (EMC) 11.
UM10237 Chapter 6: LPC24XX Memory Accelerator Module (MAM) Rev. 02 — 19 December 2008 User manual 1. How to read this chapter The Memory Accelerator Module operates in combination with the flash controller and is available in parts LPC2458/68/78. 2. Introduction The MAM block in the LPC2400 maximizes the performance of the ARM processor when it is running code in Flash memory using a single Flash bank. 3.
UM10237 NXP Semiconductors Chapter 6: LPC24XX Memory Accelerator Module (MAM) Branches and other program flow changes cause a break in the sequential flow of instruction fetches described above. The Branch Trail buffer captures the line to which such a non-sequential break occurs. If the same branch is taken again, the next instruction is taken from the Branch Trail buffer.
UM10237 NXP Semiconductors Chapter 6: LPC24XX Memory Accelerator Module (MAM) MEMORY ADDRESS FLASH MEMORY BANK ARM LOCAL BUS BUS INTERFACE BUFFERS Fig 20. Simplified block diagram of the Memory Accelerator Module 4.2 Instruction latches and data latches Code and Data accesses are treated separately by the Memory Accelerator Module. There is a 128 bit Latch, a 15 bit Address Latch, and a 15 bit comparator associated with each buffer (prefetch, branch trail, and data).
UM10237 NXP Semiconductors Chapter 6: LPC24XX Memory Accelerator Module (MAM) Mode 1: MAM partially enabled. Sequential instruction accesses are fulfilled from the holding latches if the data is present. Instruction prefetch is enabled. Non-sequential instruction accesses initiate Flash read operations (see Table note 6–2). This means that all branches cause memory fetches. All data operations cause a Flash read because buffered data access timing is hard to predict and is very situation dependent.
UM10237 NXP Semiconductors Chapter 6: LPC24XX Memory Accelerator Module (MAM) 7. Register description The MAM is controlled by the registers shown in Table 6–98. More detailed descriptions follow. Writes to any unused bits are ignored. A read of any unused bits will return a logic zero. Table 98. Name Summary of Memory Acceleration Module registers Description Access Reset Address value[1] MAMCR Memory Accelerator Module Control Register.
UM10237 NXP Semiconductors Chapter 6: LPC24XX Memory Accelerator Module (MAM) Table 100. MAM Timing register (MAMTIM - address 0xE01F C004) bit description Bit Symbol 2:0 MAM_fetch_ cycle_timing Value Description Reset value These bits set the duration of MAM fetch operations.
UM10237 NXP Semiconductors Chapter 6: LPC24XX Memory Accelerator Module (MAM) xFFE0 xFFE4 xFFE8 xFFEC 30000 30004 30008 3000C 20000 20004 20008 2000C 10000 0FFF0 10004 0FFF4 10008 0FFF8 1000C 0FFFC 00020 00010 00000 00024 00014 00004 00028 00018 00008 0002C 0001C 0000C INCREMENTOR MUX D ENAL0 ADDR Q EN cclk [18:4] = EQA0 128 ENP ADDR ENBT PREFETCH LATCH = ADDR END BT LATCH = 128 EQPREF PREFETCH MUX 128 EQD BT MUX 32 DATA LATCH = 128 EQBT LA[3:2] ADDR 32 DATA M
UM10237 NXP Semiconductors Chapter 6: LPC24XX Memory Accelerator Module (MAM) Table 101. Suggestions for MAM timing selection system clock Number of MAM fetch cycles in MAMTIM (see Table 6–100) < 20 MHz 1 CCLK 20 MHz to 40 MHz 2 CCLK 40 MHz to 60 MHz 3 CCLK > 60 MHz 4 CCLK UM10237_2 User manual © NXP B.V. 2008. All rights reserved. Rev.
UM10237 Chapter 7: LPC24XX Vectored Interrupt Controller (VIC) Rev. 02 — 19 December 2008 User manual 1. Features • • • • • • • • ARM PrimeCell Vectored Interrupt Controller Mapped to AHB address space for fast access Supports 32 vectored IRQ interrupts 16 programmable interrupt priority levels Fixed hardware priority within each programmable priority level Hardware priority level masking Any input can be assigned as an FIQ interrupt Software interrupt generation 2.
UM10237 NXP Semiconductors Chapter 7: LPC24XX Vectored Interrupt Controller (VIC) Table 102. Summary of VIC registers Name Description Access Reset Address value[1] VICIRQStatus IRQ Status Register. This register reads out the state of those interrupt requests that are enabled and classified as IRQ. RO 0 0xFFFF F000 VICFIQStatus FIQ Status Requests. This register reads out the state of those interrupt requests that are enabled and classified as FIQ.
UM10237 NXP Semiconductors Chapter 7: LPC24XX Vectored Interrupt Controller (VIC) Table 102. Summary of VIC registers Name Description Access Reset Address value[1] VICVectAddr19 Vector address 19 register. R/W 0 0xFFFF F14C VICVectAddr20 Vector address 20 register. R/W 0 0xFFFF F150 VICVectAddr21 Vector address 21 register. R/W 0 0xFFFF F154 VICVectAddr22 Vector address 22 register. R/W 0 0xFFFF F158 VICVectAddr23 Vector address 23 register.
UM10237 NXP Semiconductors Chapter 7: LPC24XX Vectored Interrupt Controller (VIC) Table 102. Summary of VIC registers Name Description Access Reset Address value[1] VICVectPriority26 Vector priority 26 register. R/W 0xF 0xFFFF F268 VICVectPriority27 Vector priority 27 register. R/W 0xF 0xFFFF F26C VICVectPriority28 Vector priority 28 register. R/W 0xF 0xFFFF F270 VICVectPriority29 Vector priority 29 register. R/W 0xF 0xFFFF F274 VICVectPriority30 Vector priority 30 register.
UM10237 NXP Semiconductors Chapter 7: LPC24XX Vectored Interrupt Controller (VIC) Table 105. Raw Interrupt Status register (VICRawIntr - address 0xFFFF F008) bit description Bit Symbol 31:0 See Table 7–117 “Interrupt sources bit allocation table”. Value Description Reset value 0 Neither the hardware nor software interrupt request with this bit number are asserted. 1 The hardware or software interrupt request with this bit number is asserted. 3.
UM10237 NXP Semiconductors Chapter 7: LPC24XX Vectored Interrupt Controller (VIC) Table 108. Interrupt Select register (VICIntSelect - address 0xFFFF F00C) bit description Bit Symbol Value Description Reset value 31:0 See Table 7–117 “Interrupt sources bit allocation table”. 0 The interrupt request with this bit number is assigned to the 0 IRQ category. 1 The interrupt request with this bit number is assigned to the FIQ category. 3.
UM10237 NXP Semiconductors Chapter 7: LPC24XX Vectored Interrupt Controller (VIC) Table 111. Vector Address registers 0-31 (VICVectAddr0-31 - addresses 0xFFFF F100 to 0xFFFF F17C) bit description Bit Symbol Description Reset value 31:0 VICVectAddr The VIC provides the contents of one of these registers in 0x0000 0000 response to a read of the Vector Address register (VICAddress see Section 7–3.9).
UM10237 NXP Semiconductors Chapter 7: LPC24XX Vectored Interrupt Controller (VIC) Table 114. Software Priority Mask register (VICSWPriorityMask - address 0xFFFF F024) bit description Bit Symbol Value Description 15:0 VICSWPriorityMask 0 31:16 - Reset value Interrupt priority level is masked. 0xFFFF 1 Interrupt priority level is not masked. - Reserved, user software should not write ones to NA reserved bits. The value read from a reserved bit is not defined. 3.
UM10237 NXP Semiconductors Chapter 7: LPC24XX Vectored Interrupt Controller (VIC) Table 116.
UM10237 NXP Semiconductors Chapter 7: LPC24XX Vectored Interrupt Controller (VIC) Table 116.
UM10237 NXP Semiconductors Chapter 7: LPC24XX Vectored Interrupt Controller (VIC) interrupt request, masking, and selection SoftIntClear [31:0] IntEnableClear [31:0] SoftInt [31:0] IntEnable [31:0] status registers and FIQ generation FIQStatus [31:0] VICINT SOURCE [31:0] IRQStatus [31:0] RawIntr [31:0] FIQ FIQStatus [31:0] IRQStatus [31:0] IntSelect [31:0] prioritization and vector generation vectored interrupt 0 IRQStatus [0] SWPriorityMask [31:0] D Q D Q SWPriorityMask [0] HWPriorityMas
UM10237 Chapter 8: LPC24XX Pin configuration Rev. 02 — 19 December 2008 User manual 1. How to read this chapter For information about the individual LPC2400 parts, refer to table Table 8–118. Parts LPC2460 and LPC2470 are flashless and use pins P3[15] and P3[14] for boot control. Table 118.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration 157 208 2.2 LPC2400 208-pin packages 1 156 LPC2400FBD208 105 53 104 52 Fig 24. LPC2400 pinning LQFP208 package ball A1 index area 2 1 4 3 6 5 8 7 9 10 12 14 16 11 13 15 17 A B C D E F G H LPC2400FET208 J K L M N P R T U Transparent top view Fig 25. LPC2400 pinning TFBGA208 package 3. LPC2458 pinning information Table 119.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 119.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 119.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 119.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 120. Pin description …continued Symbol Ball Type Description P0[6]/ I2SRX_SDA/ SSEL1/MAT2[0] D11[1] I/O P0[6] — General purpose digital input/output pin. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I/O SSEL1 — Slave Select for SSP1. O MAT2[0] — Match output for Timer 2, channel 0.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 120. Pin description …continued Symbol Ball Type Description P0[14]/ USB_HSTEN2/ USB_CONNECT2/ SSEL1 M5[1] I/O P0[14] — General purpose digital input/output pin. O USB_HSTEN2 — Host Enabled status for USB port 2. O USB_CONNECT2 — SoftConnect control for USB port 2. Signal used to switch an external 1.5 kΩ resistor under software control. Used with the SoftConnect USB feature. I/O SSEL1 — Slave Select for SSP1.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 120. Pin description …continued Symbol Ball Type Description P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0] F5[2] I/O P0[23] — General purpose digital input/output pin. I AD0[0] — A/D converter 0, input 0. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I CAP3[0] — Capture input for Timer 3, channel 0.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 120. Pin description …continued Symbol Ball Type Description P1[3]/ ENET_TXD3/ MCICMD/ PWM0[2] A9[1] I/O P1[3] — General purpose digital input/output pin. O ENET_TXD3 — Ethernet transmit data 3 (MII interface).
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 120. Pin description …continued Symbol Ball Type Description P1[16]/ ENET_MDC B8[1] I/O P1[16] — General purpose digital input/output pin. O ENET_MDC — Ethernet MIIM clock. P1[17]/ ENET_MDIO C9[1] I/O P1[17] — General purpose digital input/output pin. I/O ENET_MDIO — Ethernet MI data input and output. P1[18]/ USB_UP_LED1/ PWM1[1]/ CAP1[0] L5[1] I/O P1[18] — General purpose digital input/output pin.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 120. Pin description …continued Symbol Ball Type Description P1[26]/ USB_SSPND1/ PWM1[6]/ CAP0[0] P8[1] I/O P1[26] — General purpose digital input/output pin. O USB_SSPND1 — USB port 1 Bus Suspend status (OTG transceiver). O PWM1[6] — Pulse Width Modulator 1, channel 6 output. I CAP0[0] — Capture input for Timer 0, channel 0. I/O P1[27] — General purpose digital input/output pin.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 120. Pin description …continued Symbol Ball Type Description P2[3]/PWM1[4]/ DCD1/ PIPESTAT2 E13[1] I/O P2[3] — General purpose digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I DCD1 — Data Carrier Detect input for UART1. O PIPESTAT2 — Pipeline Status, bit 2. I/O P2[4] — General purpose digital input/output pin. O PWM1[5] — Pulse Width Modulator 1, channel 5 output.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 120. Pin description …continued Symbol Ball Type Description P2[12]/EINT2/ MCIDAT2/ I2STX_WS N14[6] I/O P2[12] — General purpose digital input/output pin. I EINT2 — External interrupt 2 input. I/O MCIDAT2 — Data line 2 for SD/MMC interface. I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 120. Pin description …continued Symbol Ball Type Description P3[4]/D4 D3[1] I/O P3[4] — General purpose digital input/output pin. I/O D4 — External memory data line 4. P3[5]/D5 E3[1] I/O P3[5] — General purpose digital input/output pin. I/O D5 — External memory data line 5. I/O P3[6] — General purpose digital input/output pin. I/O D6 — External memory data line 6.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 120. Pin description …continued Symbol Ball Type Description P4[0]/A0 L6[1] I/O P4[0] — General purpose digital input/output pin. I/O A0 — External memory address line 0. P4[1]/A1 M7[1] I/O P4[1] — General purpose digital input/output pin. I/O A1 — External memory address line 1. I/O P4[2] — General purpose digital input/output pin. I/O A2 — External memory address line 2.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 120. Pin description …continued Symbol Ball Type Description P4[24]/OE C8[1] I/O P4[24] — General purpose digital input/output pin. O OE — LOW active Output Enable signal. P4[25]/WE D9[1] I/O P4[25] — General purpose digital input/output pin. O WE — LOW active Write Enable signal. I/O P4[26] — General purpose digital input/output pin. O BLS0 — LOW active Byte Lane select signal 0.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 120. Pin description …continued Symbol Ball Type Description VSSIO H4, P4, L9, L13, G13, D13, C11, B4[9] I ground: 0 V reference for the digital IO pins. VSSCORE H3, L8, A10[9] I ground: 0 V reference for the core. VSSA F3[10] I analog ground: 0 V reference. This should nominally be the same voltage as VSSIO/VSSCORE, but should be isolated to minimize noise and error.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration 4. LPC2460/68 pinning information Table 121. LPC2420/60/68 pin allocation table CAN and Ethernet pins for LPC2460/68 only.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 121. LPC2420/60/68 pin allocation table …continued CAN and Ethernet pins for LPC2460/68 only.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 121. LPC2420/60/68 pin allocation table …continued CAN and Ethernet pins for LPC2460/68 only.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 122.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 122. LPC2420/60/68 pin description …continued Symbol Pin Ball Type Description P0[9]/ I2STX_SDA/ MOSI1/MAT2[3] 158[1] C14[1] I/O P0[9] — General purpose digital input/output pin. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. I/O MOSI1 — Master Out Slave In for SSP1. O MAT2[3] — Match output for Timer 2, channel 3.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 122. LPC2420/60/68 pin description …continued Symbol Pin Ball Type Description P0[18]/DCD1/ MOSI0/MOSI 124[1] K15[1] I/O P0[18] — General purpose digital input/output pin. I DCD1 — Data Carrier Detect input for UART1.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 122. LPC2420/60/68 pin description …continued Symbol Pin Ball Type Description P0[27]/SDA0 50[4] T1[4] I/O P0[27] — General purpose digital input/output pin. I/O SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance). I/O P0[28] — General purpose digital input/output pin. I/O SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus compliance).
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 122. LPC2420/60/68 pin description …continued Symbol Pin Ball Type Description P1[7]/ ENET_COL/ MCIDAT1/ PWM0[5] 153[1] D14[1] I/O P1[7] — General purpose digital input/output pin. I ENET_COL — Ethernet Collision detect (MII interface) (LPC2460 only). I/O MCIDAT1 — Data line 1 for SD/MMC interface. O PWM0[5] — Pulse Width Modulator 0, output 5. I/O P1[8] — General purpose digital input/output pin.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 122. LPC2420/60/68 pin description …continued Symbol Pin Ball Type Description P1[19]/ USB_TX_E1/ USB_PPWR1/ CAP1[1] 68[1] U6[1] I/O P1[19] — General purpose digital input/output pin. O USB_TX_E1 — Transmit Enable signal for USB port 1 (OTG transceiver). O USB_PPWR1 — Port Power enable signal for USB port 1. I CAP1[1] — Capture input for Timer 1, channel 1. I/O P1[20] — General purpose digital input/output pin.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 122. LPC2420/60/68 pin description …continued Symbol Pin Ball Type Description P1[29]/ USB_SDA1/ PCAP1[1]/ MAT0[1] 92[1] U14[1] I/O P1[29] — General purpose digital input/output pin. I/O USB_SDA1 — USB port 1 I2C serial data (OTG transceiver). P1[30]/ USB_PWRD2/ VBUS/AD0[4] 42[2] P2[2] I PCAP1[1] — Capture input for PWM1, channel 1. O MAT0[1] — Match output for Timer 0, channel 0.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 122. LPC2420/60/68 pin description …continued Symbol Pin Ball Type Description P2[6]/PCAP1[0]/ RI1/TRACEPKT1 138[1] E17[1] I/O P2[6] — General purpose digital input/output pin. I PCAP1[0] — Capture input for PWM1, channel 0.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 122. LPC2420/60/68 pin description …continued Symbol Pin Ball Type Description P2[15]/CS3/ CAP2[1]/SCL1 99[6] P13[6] I/O P2[15] — General purpose digital input/output pin. O CS3 — LOW active Chip Select 3 signal. I CAP2[1] — Capture input for Timer 2, channel 1. I/O SCL1 — I2C1 clock input/output (this is not an open-drain pin). I/O P2[16] — General purpose digital input/output pin.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 122. LPC2420/60/68 pin description …continued Symbol Pin Ball Type Description P2[30]/ DQMOUT2/ MAT3[2]/SDA2 31[1] L4[1] I/O P2[30] — General purpose digital input/output pin. O DQMOUT2 — Data mask 2 used with SDRAM and static devices.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 122. LPC2420/60/68 pin description …continued Symbol Pin Ball Type Description P3[15]/D15 28[1] M1[1] I/O P3[15] — General purpose digital input/output pin. I/O D15 — External memory data line 15. On POR, this pin serves as the BOOT1 pin (flashless parts only). BOOT[1:0] = 00 selects 8-bit external memory on CS1. BOOT[1:0] = 01 is reserved. Do not use. BOOT[1:0] = 10 selects 32-bit external memory on CS1.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 122. LPC2420/60/68 pin description …continued Symbol Pin Ball Type Description P3[24]/D24/ CAP0[1]/ PWM1[1] 58[1] R5[1] I/O P3[24] — General purpose digital input/output pin. I/O D24 — External memory data line 24. I CAP0[1] — Capture input for Timer 0, channel 1. O PWM1[1] — Pulse Width Modulator 1, output 1. I/O P3[25] — General purpose digital input/output pin. I/O D25 — External memory data line 25.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 122. LPC2420/60/68 pin description …continued Symbol Pin Ball Type Description P4[3]/A3 97[1] U16[1] I/O P4[3] — General purpose digital input/output pin. I/O A3 — External memory address line 3. P4[4]/A4 103[1] R15[1] I/O P4[4] — General purpose digital input/output pin. I/O A4 — External memory address line 4. I/O P4[5] — General purpose digital input/output pin. I/O A5 — External memory address line 5.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 122. LPC2420/60/68 pin description …continued Symbol Pin Ball Type Description P4[21]/A21/ SCL2/SSEL1 115[1] M15[1] I/O P4[21] — General purpose digital input/output pin. I/O A21 — External memory address line 21. I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin). I/O SSEL1 — Slave Select for SSP1. I/O P4[22] — General purpose digital input/output pin. I/O A22 — External memory address line 22.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 122. LPC2420/60/68 pin description …continued Symbol Pin Ball Type Description TCK 10[1] E2[1] I TCK — Test Clock for JTAG interface. This clock must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG interface to operate. RTCK 206[1] C3[1] I/O RTCK — JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as Trace port after reset.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration [2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled. [3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 123.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 123.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 123.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 124. LPC2470/78 pin description …continued Symbol Pin Ball Type Description P0[4]/I2SRX_CLK/ LCDVD[0]/RD2/ CAP2[0] 168[1] B12[1] I/O P0[4] — General purpose digital input/output pin. I/O I2SRX_CLK — I2S Receive clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification.[15] O LCDVD[0] — LCD data.[15] I RD2 — CAN2 receiver input.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 124. LPC2470/78 pin description …continued Symbol Pin Ball Type Description P0[10]/TXD2/ SDA2/MAT3[0] 98[1] T15[1] I/O P0[10] — General purpose digital input/output pin. O TXD2 — Transmitter output for UART2. I/O SDA2 — I2C2 data input/output (this is not an open-drain pin). O MAT3[0] — Match output for Timer 3, channel 0. I/O P0[11] — General purpose digital input/output pin. I RXD2 — Receiver input for UART2.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 124. LPC2470/78 pin description …continued Symbol Pin Ball Type Description P0[19]/DSR1/ MCICLK/SDA1 122[1] L17[1] I/O P0[19] — General purpose digital input/output pin. I DSR1 — Data Set Ready input for UART1.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 124. LPC2470/78 pin description …continued Symbol Pin Ball Type Description P0[29]/USB_D+1 61[5] U4[5] I/O P0[29] — General purpose digital input/output pin. I/O USB_D+1 — USB port 1 bidirectional D+ line.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 124. LPC2470/78 pin description …continued Symbol Pin Ball Type Description P1[11]/ ENET_RXD2/ MCIDAT2/ PWM0[6] 163[1] A14[1] I/O P1[11] — General purpose digital input/output pin. I ENET_RXD2 — Ethernet Receive Data 2 (MII interface).
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 124. LPC2470/78 pin description …continued Symbol Pin Ball Type Description P1[22]/USB_RCV1/ LCDVD[8]/ LCDVD[12]/ USB_PWRD1/ MAT1[0] 74[1] U8[1] I/O P1[22] — General purpose digital input/output pin. I USB_RCV1 — Differential receive data for USB port 1 (OTG transceiver).[16] O LCDVD[8]/LCDVD[12] — LCD data.[16] I USB_PWRD1 — Power Status for USB port 1 (host power switch).
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 124. LPC2470/78 pin description …continued Symbol Pin Ball Type Description P1[29]/USB_SDA1/ LCDVD[15]/ LCDVD[23]/ PCAP1[1]/MAT0[1] 92[1] U14[1] I/O P1[29] — General purpose digital input/output pin. I/O USB_SDA1 — USB port 1 I2C serial data (OTG transceiver).[16] O LCDVD[15]/LCDVD[23] — LCD data.[16] I PCAP1[1] — Capture input for PWM1, channel 1. O MAT0[1] — Match output for Timer 0, channel 0.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 124. LPC2470/78 pin description …continued Symbol Pin Ball Type Description P2[0]/PWM1[1]/ TXD1/TRACECLK/ LCDPWR 154[1] B17[1] I/O P2[0] — General purpose digital input/output pin. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. O TXD1 — Transmitter output for UART1. O TRACECLK — Trace clock.[17] O LCDPWR — LCD panel power enable.[17] I/O P2[1] — General purpose digital input/output pin.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 124. LPC2470/78 pin description …continued Symbol Pin Ball Type Description P2[8]/TD2/TXD2/ TRACEPKT3/ LCDVD[2]/ LCDVD[6] 134[1] H15[1] I/O P2[8] — General purpose digital input/output pin. O TD2 — CAN2 transmitter output. O TXD2 — Transmitter output for UART2. O TRACEPKT3 — Trace packet, bit 3.[17] O LCDVD[2]/LCDVD[6] — LCD data.[17] I/O P2[9] — General purpose digital input/output pin.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 124. LPC2470/78 pin description …continued Symbol Pin Ball Type Description P2[16]/CAS 87[1] R11[1] I/O P2[16] — General purpose digital input/output pin. O CAS — LOW active SDRAM Column Address Strobe.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 124. LPC2470/78 pin description …continued Symbol Pin Ball Type Description P2[31]/ DQMOUT3/ MAT3[3]/SCL2 39[1] N2[1] I/O P2[31] — General purpose digital input/output pin. O DQMOUT3 — Data mask 3 used with SDRAM and static devices. O MAT3[3] — Match output for Timer 3, channel 3. I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin).
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 124. LPC2470/78 pin description …continued Symbol Pin Ball Type Description P3[15]/D15 28[1] M1[1] I/O P3[15] — General purpose digital input/output pin. I/O D15 — External memory data line 15. On POR, this pin serves as the BOOT1 pin (flashless parts only). BOOT[1:0] = 00 selects 8-bit external memory on CS1. BOOT[1:0] = 01 is reserved. Do not use. BOOT[1:0] = 10 selects 32-bit external memory on CS1.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 124. LPC2470/78 pin description …continued Symbol Pin Ball Type Description P3[24]/D24/ CAP0[1]/ PWM1[1] 58[1] R5[1] I/O P3[24] — General purpose digital input/output pin. I/O D24 — External memory data line 24.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 124. LPC2470/78 pin description …continued Symbol Pin Ball Type Description P4[3]/A3 97[1] U16[1] I/O P4[3] — General purpose digital input/output pin. I/O A3 — External memory address line 3.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 124. LPC2470/78 pin description …continued Symbol Pin Ball Type Description P4[21]/A21/ SCL2/SSEL1 115[1] M15[1] I/O P4[21] — General purpose digital input/output pin. I/O A21 — External memory address line 21. I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin). I/O SSEL1 — Slave Select for SSP1. I/O P4[22] — General purpose digital input/output pin. I/O A22 — External memory address line 22.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration Table 124. LPC2470/78 pin description …continued Symbol Pin Ball Type Description TMS 6[1] E3[1] I TMS — Test Mode Select for JTAG interface. TRST 8[1] D1[1] I TRST — Test Reset for JTAG interface. TCK 10[1] E2[1] I TCK — Test Clock for JTAG interface. This clock must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG interface to operate. RTCK 206[1] C3[1] I/O RTCK — JTAG interface control signal.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration [1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. [2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled. [3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled.
UM10237 NXP Semiconductors Chapter 8: LPC24XX Pin configuration the address mirror bit is set in the EMCControl register during POR, see Table 5–68. Therefore, the user code residing in the external boot memory must be linked to execute from address location 0x8000 0000 (EMC bank 0 address). Remark: The external boot option is supported only for flashless devices LPC2460 and LPC2470. UM10237_2 User manual © NXP B.V. 2008. All rights reserved. Rev.
UM10237 Chapter 9: LPC24XX Pin connect Rev. 02 — 19 December 2008 User manual 1. How to read this chapter The LPC2400 parts have different pin configurations depending on the number of pins. See Table 9–126 for the PINSEL registers needed to configure the different LPC2400 parts: • Only LPC2470 and LPC2478 have an LCD controller. • LPC2420/60 and LPC2470 are flashless and requite boot pins (see Table 9–138).
UM10237 NXP Semiconductors Chapter 9: LPC24XX Pin connect 3. Pin function select register values The PINSEL registers control the functions of device pins as shown below. Pairs of bits in these registers correspond to specific device pins. Table 127.
UM10237 NXP Semiconductors Chapter 9: LPC24XX Pin connect Table 129.
UM10237 NXP Semiconductors Chapter 9: LPC24XX Pin connect Table 130. Pin function select register 0 (PINSEL0 - address 0xE002 C000) bit description PINSEL0 Pin name Function when Function when 01 00 Function when 10 Function when 11 Reset value 7:6 P0[3] GPIO Port 0.3 RXD0 Reserved Reserved 00 9:8 P0[4] GPIO Port 0.4 I2SRX_CLK/ LCDVD[0] RD2 CAP2[0] 00 11:10 P0[5] GPIO Port 0.5 I2SRX_WS/ LCDVD[1] TD2 CAP2[1] 00 13:12 P0[6] GPIO Port 0.
UM10237 NXP Semiconductors Chapter 9: LPC24XX Pin connect Table 131. Pin function select register 1 (PINSEL1 - address 0xE002 C004) bit description PINSEL1 Pin name Function when Function 00 when 01 Function when 10 Function when 11 Reset value 27:26 P0[29] GPIO Port 0.29 USB_D+1 Reserved Reserved 00 29:28 P0[30] GPIO Port 0.30 USB_D−1 Reserved Reserved 00 31:30 P0[31] GPIO Port 0.
UM10237 NXP Semiconductors Chapter 9: LPC24XX Pin connect Table 133. Pin function select register 3 (PINSEL3 - address 0xE002 C00C) bit description PINSEL3 Pin name Function when Function when Function 00 01 when 10 Function when 11 Reset value 1:0 P1[16] GPIO Port 1.16 ENET_MDC Reserved Reserved 00 3:2 P1[17] GPIO Port 1.17 ENET_MDIO Reserved Reserved 00 5:4 P1[18] GPIO Port 1.18 USB_UP_LED1 PWM1[1] CAP1[0] 00 7:6 P1[19] GPIO Port 1.
UM10237 NXP Semiconductors Chapter 9: LPC24XX Pin connect Table 134. LPC2458 pin function select register 4 (PINSEL4 - address 0xE002 C010) bit description PINSEL4 Pin name Function when Function 00 when 01 Function when 10 Function when 11 Reset value 1:0 GPIO Port 2.0 TXD1 TRACECLK[1] 00 RXD1 PIPESTAT0[1] 00 00 P2[0] 3:2 P2[1] GPIO Port 2.1 PWM1[1] PWM1[2] 5:4 P2[2] GPIO Port 2.2 PWM1[3] CTS1 PIPESTAT1[1] 7:6 P2[3] GPIO Port 2.
UM10237 NXP Semiconductors Chapter 9: LPC24XX Pin connect Table 135. LPC2420/60/68/70/78 pin function select register 4 (PINSEL4 - address 0xE002 C010) bit description PINSEL4 Pin name Function when Function 00 when 01 Function when 10 Function when 11 Reset value 11:10 P2[5] GPIO Port 2.5 PWM1[6] DTR1 TRACEPKT0[1]/ LCDLP 00 13:12 P2[6] GPIO Port 2.6 PCAP1[0] RI1 TRACEPKT1[1]/ LCDVD[0]/ LCDVD[4] 00 15:14 P2[7] GPIO Port 2.
UM10237 NXP Semiconductors Chapter 9: LPC24XX Pin connect Table 136. LPC2458 pin function select register 5 (PINSEL5 - address 0xE002 C014) bit description PINSEL5 Pin name Function when Function 00 when 01 Function when 10 Function when 11 Reset value 1:0 P2[16] GPIO Port 2.16 CAS Reserved Reserved 00 3:2 P2[17] GPIO Port 2.17 RAS Reserved Reserved 00 5:4 P2[18] GPIO Port 2.18 CLKOUT0 Reserved Reserved 00 7:6 P2[19] GPIO Port 2.
UM10237 NXP Semiconductors Chapter 9: LPC24XX Pin connect 5.7 Pin Function Select Register 6 (PINSEL6 - 0xE002 C018) The PINSEL6 register controls the functions of the pins as per the settings listed in Table 9–138. The direction control bit in the FIO3DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Table 138.
UM10237 NXP Semiconductors Chapter 9: LPC24XX Pin connect Table 139. LPC2458 pin function select register 7 (PINSEL7 - address 0xE002 C01C) bit description PINSEL7 Pin name Function when 00 Function when 01 Function when 10 Function when 11 Reset value 9:8 P3[20] Reserved Reserved Reserved Reserved 00 11:10 P3[21] Reserved Reserved Reserved Reserved 00 13:12 P3[22] Reserved Reserved Reserved Reserved 00 15:14 P3[23] GPIO Port 3.
UM10237 NXP Semiconductors Chapter 9: LPC24XX Pin connect Table 141. Pin function select register 8 (PINSEL8 - address 0xE002 C020) bit description PINSEL8 Pin name Function when 00 Function when 01 Function when 10 Function when 11 Reset value 1:0 P4[0] GPIO Port 4.0 A0 Reserved Reserved 00 3:2 P4[1] GPIO Port 4.1 A1 Reserved Reserved 00 5:4 P4[2] GPIO Port 4.2 A2 Reserved Reserved 00 7:6 P4[3] GPIO Port 4.3 A3 Reserved Reserved 00 9:8 P4[4] GPIO Port 4.
UM10237 NXP Semiconductors Chapter 9: LPC24XX Pin connect Table 142. LPC2458 pin function select register 9 (PINSEL9 - address 0xE002 C024) bit description PINSEL9 Pin name Function when Function 00 when 01 Function when 10 Function when 11 Reset value 21:20 P4[26] GPIO Port 4.26 BLS0 Reserved Reserved 00 23:22 P4[27] GPIO Port 4.27 BLS1 Reserved Reserved 00 25:24 P4[28] GPIO Port 4.28 Reserved MAT2[0] TXD3 00 27:26 P4[29] GPIO Port 4.
UM10237 NXP Semiconductors Chapter 9: LPC24XX Pin connect Table 144. Pin function select register 10 (PINSEL10 - address 0xE002 C028) bit description Bit Symbol Value Description 2:0 - - 3 GPIO/TRACE 31:4 - Reset value Reserved. Software should not write 1 to these bits. NA ETM interface pins control. RTCK, see the text above 0 ETM interface is disabled. 1 ETM interface is enabled. ETM signals are available on the pins hosting them regardless of the PINSEL4 content. - Reserved.
UM10237 NXP Semiconductors Chapter 9: LPC24XX Pin connect 5.14 Pin Mode select register 1 (PINMODE1 - 0xE002 C044) This register controls pull-up/pull-down resistor configuration for PORT0 pins 16 to 26. For details see Section 9–4 “Pin mode select register values”. Table 147. Pin Mode select register 1 (PINMODE1 - address 0xE002 C044) bit description PINMODE1 Symbol Description Reset value 1:0 PORT0 pin 16 on-chip pull-up/down resistor control. 00 00 P0.16MODE ... 21:20 P0.
UM10237 NXP Semiconductors Chapter 9: LPC24XX Pin connect Table 150. Pin Mode select register 4 (PINMODE4 - address 0xE002 C050) bit description PINMODE4 Symbol Description Reset value 1:0 P2.00MODE PORT2 pin 0 on-chip pull-up/down resistor control. 00 P2.15MODE PORT2 pin 15 on-chip pull-up/down resistor control. 00 ... 31:30 5.18 Pin Mode select register 5 (PINMODE5 - 0xE002 C054) This register controls pull-up/pull-down resistor configuration for PORT2 pins 16 to 31.
UM10237 NXP Semiconductors Chapter 9: LPC24XX Pin connect Table 154. Pin Mode select register 8 (PINMODE8 - address 0xE002 C060) bit description PINMODE8 Symbol Description Reset value 1:0 P4.00MODE PORT4 pin 0 on-chip pull-up/down resistor control. 00 P4.15MODE PORT4 pin 15 on-chip pull-up/down resistor control. 00 ... 31:30 5.22 Pin Mode select register 9 (PINMODE9 - 0xE002 C064) This register controls pull-up/pull-down resistor configuration for PORT4 pins 16 to 31.
UM10237 Chapter 10: LPC24XX General Purpose Input/Output (GPIO) Rev. 02 — 19 December 2008 User manual 1. How to read this chapter The number of GPIO pins on each port is different for LPC2458 and LPC2460/68/70/78 parts. The available pins are listed in Table 10–156 for each part. Bits corresponding to unavailable pins are reserved in all GPIO related registers. Table 156.
UM10237 NXP Semiconductors Chapter 10: LPC24XX General Purpose Input/Output (GPIO) – Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. – All GPIO registers are byte and half-word addressable. – Entire port value can be written in one instruction. • Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. • Direction control of individual bits. • All I/O default to inputs after reset.
UM10237 NXP Semiconductors Chapter 10: LPC24XX General Purpose Input/Output (GPIO) 5. Pin description Table 157. GPIO pin description Pin Name Type Description P0[31:0] P1[31:0] P2[31:0] P3[31:0] P4[31:0] Input/ Output General purpose input/output. These are typically shared with other peripherals functions and will therefore not all be available in an application. Packaging options may affect the number of GPIOs available in a particular device.
UM10237 NXP Semiconductors Chapter 10: LPC24XX General Purpose Input/Output (GPIO) Table 158. Summary of GPIO registers (legacy APB accessible registers) Generic Description Name Access Reset value[1] PORTn Register Address & Name IOPIN GPIO Port Pin value register. The current state of the GPIO R/W configured port pins can always be read from this register, regardless of pin direction. By writing to this register port’s pins will be set to the desired level instantaneously.
UM10237 NXP Semiconductors Chapter 10: LPC24XX General Purpose Input/Output (GPIO) Table 159. Summary of GPIO registers (local bus accessible registers - enhanced GPIO features) Generic Name Description Access Reset PORTn Register value[1] Address & Name FIODIR Fast GPIO Port Direction control register. This register individually controls the direction of each port pin.
UM10237 NXP Semiconductors Chapter 10: LPC24XX General Purpose Input/Output (GPIO) Table 160. GPIO interrupt register map Generic Name Description Access Reset value[1] PORTn Register Address & Name IntEnR GPIO Interrupt Enable for Rising edge. R/W 0x0 IO0IntEnR - 0xE002 8090 IO2IntEnR - 0xE002 80B0 IntEnF GPIO Interrupt Enable for Falling edge. R/W 0x0 IO0IntEnR - 0xE002 8094 IO2IntEnR - 0xE002 80B4 IntStatR GPIO Interrupt Status for Rising edge.
UM10237 NXP Semiconductors Chapter 10: LPC24XX General Purpose Input/Output (GPIO) Aside from the 32-bit long and word only accessible FIODIR register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 10–163, too. Next to providing the same functions as the FIODIR register, these additional registers allow easier and faster access to the physical port pins. Table 163.
UM10237 NXP Semiconductors Chapter 10: LPC24XX General Purpose Input/Output (GPIO) Legacy registers are the IO0SET and IO1SET while the enhanced GPIOs are supported via the FIO0SET, FIO1SET, FIO2SET, FIO3SET, and FIO4SET registers. Access to a port pin via the FIOSET register is conditioned by the corresponding bit of the FIOMASK register (see Section 10–6.5 “Fast GPIO port Mask register FIOMASK(FIO[0/1/2/3/4]MASK - 0x3FFF C0[1/3/5/7/9]0)”). Table 164.
UM10237 NXP Semiconductors Chapter 10: LPC24XX General Purpose Input/Output (GPIO) Table 166. Fast GPIO port output Set byte and half-word accessible register description Generic Register name Description Register length (bits) & access Reset value PORTn Register Address & Name FIOxSET3 Fast GPIO Port x output Set register 3. Bit 0 in FIOxSET3 register corresponds to pin Px.24 ... bit 7 to pin Px.31.
UM10237 NXP Semiconductors Chapter 10: LPC24XX General Purpose Input/Output (GPIO) Aside from the 32-bit long and word only accessible FIOCLR register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 10–169, too. Next to providing the same functions as the FIOCLR register, these additional registers allow easier and faster access to the physical port pins. Table 169.
UM10237 NXP Semiconductors Chapter 10: LPC24XX General Purpose Input/Output (GPIO) Writing to the IOPIN register stores the value in the port output register, bypassing the need to use both the IOSET and IOCLR registers to obtain the entire written value. This feature should be used carefully in an application since it affects the entire port. Legacy registers are the IO0PIN and IO1PIN while the enhanced GPIOs are supported via the FIO0PIN, FIO1PIN, FIO2PIN, FIO3PIN and FIO4PIN registers.
UM10237 NXP Semiconductors Chapter 10: LPC24XX General Purpose Input/Output (GPIO) Table 172. Fast GPIO port Pin value byte and half-word accessible register description Generic Register name Description Register length (bits) & access Reset value PORTn Register Address & Name FIOxPIN0 Fast GPIO Port x Pin value register 0. Bit 0 in FIOxPIN0 register corresponds to pin Px.0 ... bit 7 to pin Px.7.
UM10237 NXP Semiconductors Chapter 10: LPC24XX General Purpose Input/Output (GPIO) Table 173. Fast GPIO port Mask register (FIO[0/1/2/3/4]MASK - address 0x3FFF C0[1/3/5/7/9]0) bit description Bit Symbol Value Description 31:0 FP0xMASK, FP1xMASK, FP2xMASK, FP3xMASK FP4xMASK Reset value Fast GPIO physical pin access control. 0x0 0 Controlled pin is affected by writes to the port’s FIOSET, FIOCLR, and FIOPIN register(s). Current state of the pin can be read from the FIOPIN register.
UM10237 NXP Semiconductors Chapter 10: LPC24XX General Purpose Input/Output (GPIO) 6.6 GPIO interrupt registers The following registers configure the pins of port 0 and port 2 to generate interrupts. 6.6.1 GPIO overall Interrupt Status register (IOIntStatus - 0xE002 8080) This read-only register indicates the presence of interrupt pending on all of the GPIO ports that support GPIO interrupts. Only one bit per port is used. Table 175.
UM10237 NXP Semiconductors Chapter 10: LPC24XX General Purpose Input/Output (GPIO) 6.6.4 GPIO Interrupt Status for Rising edge register (IO0IntStatR - 0xE002 8084 and IO2IntStatR - 0xE002 80A4) Each bit in these read-only registers indicates the rising edge interrupt status for the corresponding port. Table 178.
UM10237 NXP Semiconductors Chapter 10: LPC24XX General Purpose Input/Output (GPIO) 7. GPIO usage notes 7.1 Example 1: sequential accesses to IOSET and IOCLR affecting the same GPIO pin/bit State of the output configured GPIO pin is determined by writes into the pin’s port IOSET and IOCLR registers. Last of these accesses to the IOSET/IOCLR register will determine the final output of a pin.
UM10237 NXP Semiconductors Chapter 10: LPC24XX General Purpose Input/Output (GPIO) 7.3 Writing to IOSET/IOCLR vs. IOPIN Write to the IOSET/IOCLR register allows easy change of the port’s selected output pin(s) to high/low level at a time. Only pin/bit(s) in the IOSET/IOCLR written with 1 will be set to high/low level, while those written as 0 will remain unaffected.
UM10237 Chapter 11: LPC24XX Ethernet Rev. 02 — 19 December 2008 User manual 1. How to read this chapter The Ethernet controller is avialable in parts LPC2458 and LPC2460/68/70/78. 2. Basic configuration The Ethernet controller is configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bit PCENET. Remark: On reset, the Ethernet block is disabled (PCENET = 0). 2. Clock: see Section 4–3.3.1. 3.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 181. Ethernet acronyms, abbreviations, and definitions Acronym or Abbreviation Definition AHB Advanced High-performance bus CRC Cyclic Redundancy Check DMA Direct Memory Access Double-word 64 bit entity FCS Frame Check Sequence (CRC) Fragment A (part of an) Ethernet frame; one or multiple fragments can add up to a single Ethernet frame.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet – Memory traffic optimized by buffering and pre-fetching. • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic FCS insertion (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision backoff and frame retransmission.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet • The host registers module containing the registers in the software view and handling AHB accesses to the Ethernet block. The host registers connect to the transmit and receive datapath as well as the MAC. • The DMA to AHB interface. This provides an AHB master connection that allows the Ethernet block to access the Ethernet SRAM for reading of descriptors, writing of status, and reading and writing data buffers.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet A receive filter block is used to identify received frames that are not addressed to this Ethernet station, so that they can be discarded. The Rx filters include a perfect address filter and a hash filter. Wake-on-LAN power management support makes it possible to wake the system up from a power-down state -a state in which some of the clocks are switched off -when wake-up frames are received over the LAN.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Descriptors, which are stored in memory, contain information about fragments of incoming or outgoing Ethernet frames. A fragment may be an entire frame or a much smaller amount of data. Each descriptor contains a pointer to a memory buffer that holds data associated with a fragment, the size of the fragment buffer, and details of how the fragment will be transmitted or received.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet ethernet packet PREAMBLE 7 bytes ETHERNET FRAME start-of-frame delimiter 1 byte DESTINATION ADDRESS SOURCE ADDRESS OPTIONAL VLAN LEN TYPE PAYLOAD DesA oct6 DesA oct5 DesA oct4 DesA oct3 DesA oct2 DesA oct1 SrcA oct6 SrcA oct5 LSB oct(0) oct(1) oct(2) oct(3) oct(4) oct(5) oct(6) MSB oct(7) SrcA oct4 SrcA oct3 FCS SrcA oct2 SrcA oct1 time Fig 27.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 183. Ethernet MII pin descriptions Pin Name Type Pin Description ENET_RX_DV Input Receive data valid. ENET_RXD[3:0] Input Receive data. ENET_RX_ER Input Receive error. ENET_RX_CLK Input Receive clock ENET_COL Input Collision detect. ENET_CRS Input Carrier sense. Table 184.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 186. Summary of Ethernet registers Symbol Address R/W Description MAC1 0xFFE0 0000 R/W MAC configuration register 1. MAC2 0xFFE0 0004 R/W MAC configuration register 2. IPGT 0xFFE0 0008 R/W Back-to-Back Inter-Packet-Gap register. IPGR 0xFFE0 000C R/W Non Back-to-Back Inter-Packet-Gap register. CLRT 0xFFE0 0010 R/W Collision window / Retry register. MAXF 0xFFE0 0014 R/W Maximum Frame register.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 186. Summary of Ethernet registers Symbol Address R/W Description RSV 0xFFE0 0160 RO - 0xFFE0 0164 to 0xFFE0 016C FlowControlCounter 0xFFE0 0170 R/W Flow control counter register. FlowControlStatus 0xFFE0 0174 RO - 0xFFE0 0178 to 0xFFE0 01FC Receive status vector register. Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Flow control status register.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet 7.1.1 MAC Configuration Register 1 (MAC1 - 0xFFE0 0000) The MAC configuration register 1 (MAC1) has an address of 0xFFE0 0000. Its bit definition is shown in Table 11–187. Table 187. MAC Configuration register 1 (MAC1 - address 0xFFE0 0000) bit description Bit Symbol Function Reset value 0 RECEIVE ENABLE Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 188. MAC Configuration register 2 (MAC2 - address 0xFFE0 0004) bit description Bit Symbol Function Reset value 3 DELAYED CRC This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet 7.1.3 Back-to-Back Inter-Packet-Gap Register (IPGT - 0xFFE0 0008) The Back-to-Back Inter-Packet-Gap register (IPGT) has an address of 0xFFE0 0008. Its bit definition is shown in Table 11–190. Table 190.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 192. Collision Window / Retry register (CLRT - address 0xFFE0 0010) bit description Bit Symbol Function Reset value 3:0 RETRANSMISSION MAXIMUM This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5. 0xF 7:4 - Reserved.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 195. Test register (TEST - address 0xFFE0 ) bit description Bit Symbol Function Reset value 0 SHORTCUT PAUSE QUANTA This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time. 0 1 TEST PAUSE This bit causes the MAC Control sublayer to inhibit transmissions, just as if a 0 PAUSE Receive Control frame with a nonzero pause time parameter was received.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 198. MII Mgmt Command register (MCMD - address 0xFFE0 0024) bit description Bit Symbol Function Reset value 0 READ This bit causes the MII Management hardware to perform a single Read cycle. The Read data is 0 returned in Register MRDD (MII Mgmt Read Data). 1 SCAN This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example. 0 31:2 - Unused 0x0 7.1.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 202. MII Mgmt Indicators register (MIND - address 0xFFE0 0034) bit description Bit Symbol Function Reset value 0 BUSY When ’1’ is returned - indicates MII Mgmt is currently performing an 0 MII Mgmt Read or Write cycle. 1 SCANNING When ’1’ is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 204. Station Address register (SA1 - address 0xFFE0 0044) bit description Bit Symbol Function Reset value 7:0 STATION ADDRESS, This field holds the fourth octet of the station address. 4th octet 0x0 15:8 STATION ADDRESS, This field holds the third octet of the station address. 3rd octet 0x0 31:16 - 0x0 Unused The station address is used for perfect address filtering and for sending pause control frames.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 206. Command register (Command - address 0xFFE0 0100) bit description Bit Symbol Function Reset value 8 TxFlowControl Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex. 0 9 RMII When set to ’1’, RMII mode is selected; if ’0’, MII mode is selected. 0 10 FullDuplex When set to ’1’, indicates full duplex operation.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet The receive descriptor base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to ’00’. The register contains the lowest address in the array of descriptors. 7.2.4 Receive Status Base Address Register (RxStatus - 0xFFE0 010C) The receive descriptor base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to ’00’. The register contains the lowest address in the array of descriptors. Table 209.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet The receive produce index register defines the descriptor that is going to be filled next by the hardware receive process. After a frame has been received, hardware increments the index. The value is wrapped to 0 once the value of RxDescriptorNumber has been reached. If the RxProduceIndex equals RxConsumeIndex - 1, the array is full and any further frames being received will cause a buffer overrun error. 7.2.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 214. Transmit Status Base Address register (TxStatus - address 0xFFE0 0120) bit description Bit Symbol Function Reset value 1:0 - Fixed to ’00’ - 31:2 TxStatus MSBs of transmit status base address. 0x0 The transmit status base address is a byte address aligned to a word boundary i.e. LSB 1:0 are fixed to ’00’. The register contains the lowest address in the array of statuses. 7.2.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet 7.2.12 Transmit Consume Index Register (TxConsumeIndex - 0xFFE0 012C) The Transmit Consume Index register (TxConsumeIndex) is a Read Only register with an address of 0xFFE0 012C. Its bit definition is shown in Table 11–217. Table 217.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 218. Transmit Status Vector 0 register (TSV0 - address 0xFFE0 0158) bit description Bit Symbol Function Reset value 10 Giant Byte count in frame was greater than can be represented in the transmit byte count field in TSV1. 0 11 Underrun Host side caused buffer underrun. 0 27:12 Total bytes The total number of bytes transferred including collided attempts. 0x0 28 Control frame The frame was a control frame.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 11–220 lists the bit definitions of the RSV register. Table 220. Receive Status Vector register (RSV - address 0xFFE0 0160) bit description Bit Symbol Function Reset value 15:0 Received byte count Indicates length of received frame. 0x0 16 Packet previously ignored Indicates that a packet was dropped. 0 17 RXDV event previously seen Indicates that the last receive event seen was not long enough to be a valid packet.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 221. Flow Control Counter register (FlowControlCounter - address 0xFFE0 0170) bit description Bit Symbol Function Reset value 15:0 MirrorCounter In full duplex mode the MirrorCounter specifies the number 0x0 of cycles before re-issuing the Pause control frame. 31:16 PauseTimer In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 223. Receive Filter Control register (RxFilterCtrl - address 0xFFE0 0200) bit description Bit Symbol Function 12 MagicPacketEnWoL When set to ’1’, the result of the magic packet filter will 0 generate a WoL interrupt when there is a match. 13 RxFilterEnWoL When set to ’1’, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 225. Receive Filter WoL Clear register (RxFilterWoLClear - address 0xFFE0 0208) bit description Bit Symbol Function Reset value 0 AcceptUnicastWoLClr 0 1 AcceptBroadcastWoLClr When a ’1’ is written to one of these bits (0 to 5), the corresponding status bit in the RxFilterWoLStatus register is cleared.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 228. Interrupt Status register (IntStatus - address 0xFFE0 0FE0) bit description Bit Symbol Function Reset value 0 RxOverrunInt Interrupt set on a fatal overrun error in the receive queue. The 0 fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 229. Interrupt Enable register (intEnable - address 0xFFE0 0FE4) bit description Bit Symbol Function Reset value 4 TxUnderrunIntEn Enable for interrupt trigger on transmit buffer or descriptor underrun situations. 0 5 TxErrorIntEn Enable for interrupt trigger on transmit errors. 0 6 TxFinishedIntEn Enable for interrupt triggered when all transmit descriptors have been processed i.e.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 231. Interrupt Set register (IntSet - address 0xFFE0 0FEC) bit description Bit Symbol Function Reset value 0 RxOverrunIntSet 0 1 RxErrorIntSet 2 RxFinishedIntSet Writing a ’1’ to one of these bits (0 to 7) sets the corresponding status bit in interrupt status register IntStatus.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet RxDescriptor RxStatus PACKET 1 DATA BUFFER CONTROL PACKET 2 StatusHashCRC DATA BUFFER CONTROL PACKET 3 PACKET DATA BUFFER PACKET DATA BUFFER PACKET StatusInfo StatusHashCRC DATA BUFFER CONTROL RxDescriptorNumber StatusInfo StatusHashCRC CONTROL 5 StatusInfo StatusHashCRC CONTROL 4 StatusInfo StatusInfo StatusHashCRC DATA BUFFER CONTROL StatusInfo StatusHashCRC Fig 28.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Each receive descriptor takes two word locations (8 bytes) in memory. Likewise each status field takes two words (8 bytes) in memory. Each receive descriptor consists of a pointer to the data buffer for storing receive data (Packet) and a control word (Control). The Packet field has a zero address offset, the control field has a 4 byte address offset with respect to the descriptor address as defined in Table 11–233. Table 233.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet The StatusInfo word contains flags returned by the MAC and flags generated by the receive datapath reflecting the status of the reception. Table 11–237 lists the bit definitions in the StatusInfo word. Table 237. Receive status information word Bit Symbol Description 10:0 RxSize The size in bytes of the actual data transferred into one fragment buffer.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet 8.2 Transmit descriptors and statuses Figure 11–29 depicts the layout of the transmit descriptors in memory. TxDescriptor TxStatus PACKET 1 DATA BUFFER StatusInfo CONTROL PACKET 2 DATA BUFFER StatusInfo CONTROL PACKET 3 DATA BUFFER StatusInfo CONTROL PACKET 4 DATA BUFFER StatusInfo CONTROL PACKET 5 DATA BUFFER StatusInfo CONTROL TxDescriptorNumber PACKET DATA BUFFER StatusInfo CONTROL Fig 29.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Each transmit descriptor takes two word locations (8 bytes) in memory. Likewise each status field takes one word (4 bytes) in memory. Each transmit descriptor consists of a pointer to the data buffer containing transmit data (Packet) and a control word (Control). The Packet field has a zero address offset, whereas the control field has a 4 byte address offset, see Table 11–238. Table 238.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Table 241. Transmit status information word Bit Symbol Description 20:0 - Unused 24:21 CollisionCount The number of collisions this packet incurred, up to the Retransmission Maximum. 25 Defer This packet incurred deferral, because the medium was occupied. This is not an error unless excessive deferral occurs. 26 ExcessiveDefer This packet incurred deferral beyond the maximum deferral limit and was aborted.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet data buffer and receive status is returned in the receive descriptor status word. Optionally an interrupt can be generated to notify software that a packet has been received. Note that the DMA manager will prefetch and buffer up to three descriptors. 9.2 AHB interface The registers of the Ethernet block connect to an AHB slave interface to allow access to the registers from the CPU.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet The DMA managers work with arrays of frame descriptors and statuses that are stored in memory. The descriptors and statuses act as an interface between the Ethernet hardware and the device driver software. There is one descriptor array for receive frames and one descriptor array for transmit frames. Using buffering for frame descriptors, the memory traffic and memory bandwidth utilization of descriptors can be kept small.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Ethernet block has finished reading/writing the last descriptor/status of the array (with the highest memory address), the next descriptor/status it reads/writes is the first descriptor/status of the array at the base address of the array. Full and Empty state of descriptor arrays The descriptor arrays can be empty, partially full or full. A descriptor array is empty when all descriptors are owned by the producer.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet to a fragment of a frame. By using fragments, scatter/gather DMA can be done: transmit frames are gathered from multiple fragments in memory and receive frames can be scattered to multiple fragments in memory. By stringing together fragments it is possible to create large frames from small memory areas.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet be written to the TxDescriptorNumber/RxDescriptorNumber registers using a -1 encoding i.e. the value in the registers is the number of descriptors minus one e.g. if the descriptor array has 4 descriptors the value of the number of descriptors register should be 3. After setting up the descriptor arrays, frame buffers need to be allocated for the receive descriptors before enabling the receive datapath.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet When there is a multi-fragment transmission for fragments other than the last, the Last bit in the descriptor must be set to 0; for the last fragment the Last bit must be set to 1. To trigger an interrupt when the frame has been transmitted and transmission status has been committed to memory, set the Interrupt bit in the descriptor Control field to 1.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Each time the Tx DMA manager commits a status word to memory it completes the transmission of a descriptor and it increments the TxConsumeIndex (taking wrap around into account) to hand the descriptor back to the device driver software. Software can re-use the descriptor for new transmissions after hardware has handed it back.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet IntStatus register is set in the case of a LateCollision, ExcessiveCollision, ExcessiveDefer, or NoDescriptor error; Underrun errors are reported in the TxUnderrun bit of the IntStatus register. Underrun errors can have three causes: • The next fragment in a multi-fragment transmission is not available. This is a nonfatal error. A NoDescriptor status will be returned on the previous fragment and the TxError bit in IntStatus will be set.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet All of the above interrupts can be enabled and disabled by setting or resetting the corresponding bits in the IntEnable register. Enabling or disabling does not affect the IntStatus register contents, only the propagation of the interrupt status to the CPU (via the Vectored Interrupt Controller).
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet (0x7FE0 11F8) to the TxStatus register. The device driver writes the number of descriptors and statuses minus 1(3) to the TxDescriptorNumber register. The descriptors and statuses in the arrays need not be initialized, yet. At this point, the transmit datapath may be enabled by setting the TxEnable bit in the Command register. If the transmit datapath is enabled while there are no further frames to send the TxFinishedInt interrupt flag will be set.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Since the Interrupt bit in the descriptor of the last fragment is set, after committing the status of the last fragment to memory the Ethernet block will trigger a TxDoneInt interrupt, which triggers the device driver to inspect the status information.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet descriptors to be read is determined by the total number of descriptors owned by the hardware: RxConsumeIndex - RxProduceIndex - 1. Block transferring of descriptors minimizes memory load. Read data returned from memory is buffered and consumed as needed. RX DMA manager receives data After reading the descriptor, the receive DMA engine waits for the MAC to return receive data from the (R)MII interface that passes the receive filter.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet addresses of a packet are calculated once for all the fragments belonging to the same packet and then stored in every StatusHashCRC word of the statuses associated with the corresponding fragments. If the reception reports an error, any remaining data in the receive frame is discarded and the LastFrag bit will be set in the receive status field, so the error flags in all but the last fragment of a frame will always be 0.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet The receive datapath can generate four different interrupt types: • If the Interrupt bit in the descriptor Control field is set, the Rx DMA will set the RxDoneInt bit in the IntStatus register after receiving a fragment and committing the associated data and status to memory. Even if a descriptor (fragment) is not the last in a multi-fragment frame, the Interrupt bit in the descriptor can be used to generate an interrupt.
UM10237 NXP Semiconductors Status 0 Status 1 1 CONTROL 7 0x7FE01418 0x7FE010F0 0x7FE01411 FRAGMENT 0 BUFFER(8 bytes) PACKET 0x7FE01409 Descriptor 0 0x7FE010EC RxStatus 0x7FE011F8 StatusInfo 7 0x7FE011F8 StatusHashCRC StatusInfo 7 0x7FE01200 StatusHashCRC Status 2 Status 3 0x7FE0141B 0x7FE010F8 1 CONTROL 7 0x7FE01419 PACKET 0x7FE01411 0x7FE01100 1 CONTROL 7 0x7FE01325 PACKET 0x7FE01419 StatusInfo 2 0x7FE01208 StatusHashCRC StatusInfo 7 0x7FE01210 StatusHashCRC 0x7FE0132C FRA
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet continuous memory space; even when a frame is distributed over multiple fragments it will typically be in a linear, continuous memory space; when the descriptors wrap at the end of the descriptor array the frame will not be in a continuous memory space.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Each pair of nibbles transferred on the MII interface (or four pairs of bits for RMII) is transferred as a byte on the data write interface after being delayed by 128 or 136 cycles for filtering by the receive filter and buffer modules. The Ethernet block removes preamble, frame start delimiter, and CRC from the data and checks the CRC. To limit the buffer NoDescriptor error probability, three descriptors are buffered.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet The destination address and source address hash CRCs being written in the StatusHashCRC word are the nine most significant bits of the 32 bit CRCs as calculated by the CRC calculator. 9.10 Duplex modes The Ethernet block can operate in full duplex and half duplex mode. Half or full duplex mode needs to be configured by the device driver software during initialization.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Transmit flow control is activated by writing 1 to the TxFlowControl bit of the Command register. When the Ethernet block operates in full duplex mode, this will result in transmission of IEEE 802.3/31 pause frames. The flow control continues until a 0 is written to TxFlowControl bit of the Command register. If the MAC is operating in full-duplex mode, then setting the TxFlowControl bit of the Command register will start a pause frame transmission.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Transmit flow control is enabled via the ‘TX FLOW CONTROL’ bit in the MAC1 configuration register. If the ‘TX FLOW CONTROL’ bit is zero, then the MAC will not transmit pause control frames, software must not initiate pause frame transmissions, and the TxFlowControl bit in the Command register should be zero. Transmit flow control example Figure 11–32 illustrates the transmit flow control.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet In half duplex mode, when the TxFlowControl bit goes high, continuous preamble is sent until TxFlowControl is deasserted. If the medium is idle, the Ethernet block begins transmitting preamble, which raises carrier sense causing all other stations to defer. In the event the transmitting of preamble causes a collision, the backpressure ‘rides through’ the collision. The colliding station backs off and then defers to the backpressure.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet Ethernet MAC will stop writing further data in the frame to memory; the FailFilter bit in the status word of the frame will be set to indicate that the software device driver can discard the frame immediately.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet An imperfect filter is available, based on a hash mechanism. This filter applies a hash function to the destination address and uses the hash to access a table that indicates if the frame should be accepted. The advantage of this type of filter is that a small table can cover any possible address. The disadvantage is that the filtering is imperfect, i.e. sometimes frames are accepted that should have been discarded.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet 9.15 Wake-up on LAN Overview The Ethernet block supports power management with remote wake-up over LAN. The host system can be powered down, even including part of the Ethernet block itself, while the Ethernet block continues to listen to packets on the LAN. Appropriately formed packets can be received and recognized by the Ethernet block and used to trigger the host system to wake up from its power-down state.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet The magic packet detection unit analyzes the Ethernet packets, extracts the packet address and checks the payload for the Magic Packet pattern. The address from the packet is used for matching the pattern (not the address in the SA0/1/2 registers.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet ACTIVE RxStatus = 1 xxxxxxxxxxxxxxxxxx RxEnable = 0 and not busy receiving OR RxProduceIndex = RxConsumeIndex - 1 RxEnable = 1 INACTIVE RxStatus = 0 reset Fig 34. Receive Active/Inactive state machine After a reset, the state machine is in the INACTIVE state. As soon as the RxEnable bit is set in the Command register, the state machine transitions to the ACTIVE state.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet ACTIVE TxStatus = 1 xxxxxxxxxxxxxxxxxxxxxx TxEnable = 1 AND TxProduceIndex <> TxConsumeIndex TxEnable = 0 and not busy transmitting OR TxProduceIndex = TxConsumeIndex INACTIVE TxStatus = 0 reset Fig 35. Transmit Active/Inactive state machine After reset, the state machine is in the INACTIVE state.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet If EPADEN is 1, then small frames will be padded and a CRC will always be added to the padded frames.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet 9.21 Reset The Ethernet block has a hard reset input which is connected to the chip reset, as well as several soft resets which can be activated by setting the appropriate bit(s) in registers. All registers in the Ethernet block have a value of 0 after a hard reset, unless otherwise specified. Hard reset After a hard reset, all registers will be set to their default value.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet • RegReset: Resets all of the datapaths and registers in the host registers module, excluding the registers in the MAC. A soft reset of the registers will also abort all AHB transactions of the transmit and receive datapath. The reset bit will be cleared autonomously by the Ethernet block. To do a full soft reset of the Ethernet block, device driver software must: • • • • Set the ‘SOFT RESET’ bit in the MAC1 register to 1.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet The flexibility of the descriptors used in the Ethernet block allows the possibility of defining memory buffers in a range of sizes. In order to analyze bus bandwidth requirements, some assumptions must be made about these buffers. The "worst case" is not addressed since that would involve all descriptors pointing to single byte buffers, with most of the memory occupied in holding descriptors and very little data.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet – Data to be received in an Ethernet frame, the size is variable. – Basic Ethernet rate = 12.5 Mbps. This gives a total rate of 30.5 Mbps for the traffic generated by the Ethernet DMA function. 9.23.
UM10237 NXP Semiconductors Chapter 11: LPC24XX Ethernet int crc_calc(char frame_no_fcs[], int frame_len) { int i; // iterator int j; // another iterator char byte; // current byte int crc; // CRC result int q0, q1, q2, q3; // temporary variables crc = 0xFFFFFFFF; for (i = 0; i < frame_len; i++) { byte = *frame_no_fcs++; for (j = 0; j < 2; j++) { if (((crc >> 28) ^ (byte >> 3)) & 0x00000001) q3 = 0x04C11DB7; } else { q3 = 0x00000000; } if (((crc >> 29) ^ (byte >> 2)) & 0x00000001) q2 = 0x09823B6E; } else
UM10237 Chapter 12: LPC24XX LCD controller Rev. 02 — 19 December 2008 User manual 1. How to read this chapter The LCD controller is available on parts LPC2470 and LPC2478 only. 2. Basic configuration The LCD controller is configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bit PCLCD. Remark: The LCD is disabled on reset (PCLCD = 0). Also see Section 12–6.12 for power-up procedure. 2. Clock: see Table 4–53, Table 12–263, and Table 12–260. 3.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller • • • • • 256 entry, 16-bit palette RAM, arranged as a 128x32-bit RAM. Frame, line, and pixel clock signals. AC bias signal for STN, data enable signal for TFT panels. Supports little and big-endian, and Windows CE data formats. LCD panel clock may be generated from the peripheral clock, or from a clock input pin. 4.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller The hardware cursor removes the requirement for this management by providing a completely separate image buffer for the cursor, and superimposing the cursor image on the LCD output stream at the current cursor (X,Y) coordinate. To move the hardware cursor, the software driver supplies a new cursor coordinate. The frame buffer requires no modification. This significantly reduces software overhead.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller • 16 bpp, direct 4:4:4 RGB, with 4 bpp not being used. 4.6 Monochrome STN panels Monochrome STN panels support one or more of the following modes: • 1 bpp, palettized, 2 gray scales selected from 15. • 2 bpp, palettized, 4 gray scales selected from 15. • 4 bpp, palettized, 16 gray scales selected from 15.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 243. Pins used for single panel STN displays Pin name 4-bit Monochrome (10 pins) 8-bit Monochrome (14 pins) Color (14 pins) LCDLE Y Y Y LCDLP Y Y Y LCDVD[3:0] UD[3:0] UD[3:0] UD[3:0] LCDVD[7:4] - UD[7:4] UD[7:4] LCDVD[23:8] - - - 5.1.2 Signals used for dual panel STN displays The signals used for dual panel STN displays are shown in Table 12–244. UD refers to upper panel data, and LD refers to lower panel data.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 245.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller • Bus error. There is also a single combined interrupt that is asserted when any of the individual interrupts become active. Figure 12–36 shows a simplified block diagram of the LCD controller.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller 6.1.2 AMBA AHB master interface The AHB master interface transfers display data from a selected slave (memory) to the LCD controller DMA FIFOs. It can be configured to obtain data from the 16 kB, on-chip SRAM on AHB1, various types of off-chip static memory, or off-chip SDRAM. In dual panel mode, the DMA FIFOs are filled up in an alternating fashion via a single DMA request.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 12–246 through Table 12–248 show the structure of the data in each DMA FIFO word corresponding to the endianness and bpp combinations. For each of the three supported data formats, the required data for each panel display pixel must be extracted from the data word. Table 246.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 247.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 248.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 249.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Pixel data values can be written and verified through the AHB slave interface. For information on the supported colors, refer to the section on the related panel type earlier in this chapter. The palette RAM is a dual port RAM with independent controls and addresses for each port. Port1 is used as a read/write port and is connected to the AHB slave interface. The palette entries can be written and verified through this port.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 251. Palette data storage for STN color modes. Bit(s) Name Description Name Description (RGB format) (RGB format) (BGR format) (BGR format) 5 G[0] Unused G[0] Unused 4:1 R[4:1] Red palette data B[4:1] Blue palette data 0 R[0] Unused B[0] Unused For monochrome STN mode, only the red palette field bits [4:1] are used. However, in STN color mode the green and blue [4:1] are also used.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller When the display point is inside the bounds of the cursor image, the cursor replaces frame buffer pixels with cursor pixels. When the last cursor pixel is displayed, an interrupt is generated that software can use as an indication that it is safe to modify the cursor image. This enables software controlled animations to be performed without flickering for frame synchronized cursors. 6.5.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller With FrameSync inactive, the cursor responds immediately to any change in the programmed CRSR_XY value. Some transient smearing effects may be visible if the cursor is moved across the LCD scan line. With FrameSync active, the cursor only updates its position after a vertical synchronization has occurred. This provides clean cursor movement, but the cursor position only updates once a frame. 6.5.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller 6.5.6 Cursor image format The LCD frame buffer supports three packing formats, but the hardware cursor image requirement has been simplified to support only LBBP. This is little-endian byte, big-endian pixel for Windows CE mode. The Image RAM start address is offset by 0x800 from the LCD base address, as shown in the register description in this chapter. The displayed cursor coordinate system is expressed in terms of (X,Y).
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 12–255 shows the buffer to pixel mapping for Cursor 0. Table 255.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 256.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 258. Color display driven with 2 2/3 pixel data Byte CLD[7] CLD[6] CLD[5] CLD[4] CLD[3] CLD[2] CLD[1] CLD[0] 0 P2[Green] P2[Red] P1[Blue] P1[Green] P1[Red] P0[Blue] P0[Green] P0[Red] 1 P5[Red] P4q[Blue] P4[Green] P4[Red] P3[Blue] P3[Green] P3[Red] P2[Blue] 2 P7[Blue] P7[Green] P7[Red] P6[Blue] P6[Green] P6[Red] P5[Blue] P5[Green] Each formatter consists of three 3-bit (RGB) shift left registers.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller • Next base address update interrupt. • FIFO underflow interrupt. Each of the four individual maskable interrupts is enabled or disabled by changing the mask bits in the LCD_INT_MSK register. These interrupts are also combined into a single overall interrupt, which is asserted if any of the individual interrupts are both asserted and unmasked.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller 6.12 LCD power up and power down sequence The LCD controller requires the following power-up sequence to be performed: 1. When power is applied, the following signals are held LOW: • • • • • • LCDLP LCDDCLK LCDFP LCDENAB/ LCDM LCDVD[23:0] LCDLE 2. When LCD power is stabilized, a 1 is written to the LcdEn bit in the LCD_CTRL register.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller LCD on sequence LCD off sequence Minimum 0 ms Minimum 0 ms LCD Power Minimum 0 ms Minimum 0 ms LCDLP, LCDCP, LCDFP, LCDAC, LCDLE Contrast Voltage LCDPWR, LCD[23:0] Display specific delay Display specific delay Fig 40. Power up and power down sequences 7. Register description Table 12–259 shows the registers associated with the LCD controller and a summary of their functions. Following the table are details for each register. Table 259.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 259.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 261. Horizontal Timing register (LCD_TIMH, RW - 0xFFE1 0000) Bits Function Description Reset value 31:24 HBP Horizontal back porch. 0x0 The 8-bit HBP field is used to specify the number of pixel clock periods inserted at the beginning of each line or row of pixels. After the line clock for the previous line has been deasserted, the value in HBP counts the number of pixel clocks to wait before starting the next display line.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller • PCD = 5 (LCDCLK / 7) If enough time is given at the start of the line, for example, setting HSW = 6, HBP = 10, data does not corrupt for PCD = 4, the minimum value. 7.3 Vertical Timing register (LCD_TIMV, RW - 0xFFE1 0004) The LCD_TIMV register controls the Vertical Synchronization pulse Width (VSW), the Vertical Front Porch (VFP) period, the Vertical Back Porch (VBP) period, and the Lines-Per-Panel (LPP).
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 262. Vertical Timing register (LCD_TIMV, RW - 0xFFE1 0004) Bits Function 23:16 VFP Description Reset value Vertical front porch. 0x0 This is the number of inactive lines at the end of a frame, before the vertical synchronization period. The 8-bit VFP field specifies the number of line clocks to insert at the end of each frame.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 263. Clock and Signal Polarity register (LCD_POL, RW - 0xFFE1 0008) Bits Function Description Reset value 15 reserved Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 14 IOE Invert output enable. 0x0 This bit selects the active polarity of the output enable signal in TFT mode.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 263. Clock and Signal Polarity register (LCD_POL, RW - 0xFFE1 0008) Bits Function Description Reset value 10:6 ACB AC bias pin frequency. 0x0 The AC bias pin frequency is only applicable to STN displays. These require the pixel voltage polarity to periodically reverse to prevent damage caused by DC charge accumulation.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 264. Line End Control register (LCD_LE, RW - 0xFFE1 000C) Bits Function Description Reset value 31:17 reserved Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 16 LEE LCD Line end enable. 0x0 0 = LCDLE disabled (held LOW). 1 = LCDLE signal active. 15:7 reserved Reserved, user software should not write ones to reserved bits.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Optionally, the value may be changed mid-frame to create double-buffered video displays. These registers are copied to the corresponding current registers at each LCD vertical synchronization. This event causes the LNBU bit and an optional interrupt to be generated. The interrupt can be used to reprogram the base address when generating double-buffered video. The contents of the LCD_LPBASE register are described in Table 12–266. Table 266.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 267. LCD Control register (LCD_CTRL, RW - 0xFFE1 0018) Bits Function 10 BEPO Description Reset value Big-Endian Pixel Ordering. 0x0 Controls pixel ordering within a byte: 0 = little-endian ordering within a byte. 1 = big-endian pixel ordering within a byte. The BEPO bit selects between little and big-endian pixel packing for 1, 2, and 4 bpp display modes, it has no effect on 8 or 16 bpp pixel formats.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 267. LCD Control register (LCD_CTRL, RW - 0xFFE1 0018) Bits Function 4 LcdBW Description Reset value STN LCD monochrome/color selection. 0x0 0 = STN LCD is color. 1 = STN LCD is monochrome. This bit has no meaning in TFT mode. 3:1 LcdBpp 0x0 LCD bits per pixel: Selects the number of bits per LCD pixel: 000 = 1 bpp. 001 = 2 bpp. 010 = 4 bpp. 011 = 8 bpp. 100 = 16 bpp. 101 = 24 bpp (TFT panel only). 110 = 16 bpp, 5:6:5 mode.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 268. Interrupt Mask register (LCD_INTMSK, RW - 0xFFE1 001C) Bits Function Description Reset value 2 LNBUIM LCD next base address update interrupt enable. 0x0 0: The base address update interrupt is disabled. 1: Interrupt will be generated when the LCD base address registers have been updated from the next address registers. 1 FUFIM FIFO underflow interrupt enable. 0x0 0: The FIFO underflow interrupt is disabled.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller 7.11 Masked Interrupt Status register (LCD_INTSTAT, RW - 0xFFE1 0024) The LCD_INTSTAT register is Read-Only, and contains a bit-by-bit logical AND of the LCD_INTRAW register and the LCD_INTMASK register. A logical OR of all interrupts is provided to the system interrupt controller. The contents of LCD_INTSTAT register are described in Table 12–270. Table 270.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 271. Interrupt Clear register (LCD_INTCLR, RW - 0xFFE1 0028) Bits Function Description Reset value 2 LNBUIC LCD next address base update interrupt clear. 0x0 Writing a 1 to this bit clears the LCD next address base update interrupt. 1 FUFIC FIFO underflow interrupt clear. 0x0 Writing a 1 to this bit clears the FIFO underflow interrupt. 0 reserved Reserved, user software should not write ones to reserved bits.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Each word location contains two palette entries. This means that 128 word locations are used for the palette. When configured for little-endian byte ordering, bits [15:0] are the lower numbered palette entry and [31:16] are the higher numbered palette entry. When configured for big-endian byte ordering this is reversed, because bits [31:16] are the low numbered palette entry and [15:0] are the high numbered entry.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 275. Cursor Image registers (CRSR_IMG, RW - 0xFFE1 0800 to 0xFFE1 0BFC) Bits Function Description Reset value 31:0 CRSR_IMG Cursor Image data. 0x0 The 256 words of the cursor image registers define the appearance of either one 64x64 cursor, or 4 32x32 cursors. 7.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 277. Cursor Configuration register (CRSR_CFG, RW - 0xFFE1 0C04) Bits Function Description Reset value 31:2 reserved Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 1 FrameSync Cursor frame synchronization type. 0x0 0 = Cursor coordinates are asynchronous. 1 = Cursor coordinates are synchronized to the frame synchronization pulse.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 279. Cursor Palette register 1 (CRSR_PAL1, RW - 0xFFE1 0C0C) Bits Function Description Reset value 31:24 reserved Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 23:16 Blue Blue color component. 0x0 15:8 Green Green color component 0x0 7:0 Red Red color component 0x0 7.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 281. Cursor Clip Position register (CRSR_CLIP, RW - 0xFFE1 0C14) Bits Function Description Reset value 31:14 reserved Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. - 13:8 CrsrClipY Cursor clip position for Y direction. 0x0 Distance from the top of the cursor image to the first displayed pixel in the cursor.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller 7.25 Cursor Raw Interrupt Status register (CRSR_INTRAW, RW - 0xFFE1 0C28) The CRSR_INTRAW register is set to indicate a cursor interrupt. When enabled via the CrsrIM bit in the CRSR_INTMSK register, provides the interrupt to the system interrupt controller. The contents of the CRSR_INTRAW register are described in Table 12–284. Table 284.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller 8.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller one frame LCDDCLK (panel clock) panel data clock active LCD_TIMV (VSW) LCDFP (vertical synch pulse) LCD_TIMV (VBP) LCD_TIMV(LPP) LCD_TIMV (VFP) back porch (defined in line clocks) all horizontal lines for one frame front porch (defined in line clocks) pixel data and horizontal controls for one frame see horizontal timing for STN displays (1) Signal polarities may vary for some displays. Fig 42.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller one frame LCDDCLK (panel clock) panel data clock active LCDENA (data enable) data enable LCD_TIMV (VSW) LCDFP (vertical synch pulse) LCD_TIMV (VBP) LCD_TIMV(LPP) LCD_TIMV (VFP) back porch (defined in line clocks) all horizontal lines for one frame front porch (defined in line clocks) pixel data and horizontal control signals for one frame see horizontal timing for TFT displays (1) Polarities may vary for some displays. Fig 44.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 286.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 287.
UM10237 NXP Semiconductors Chapter 12: LPC24XX LCD controller Table 288.
UM10237 Chapter 13: LPC24XX USB device controller Rev. 02 — 19 December 2008 User manual 1. Basic configuration The USB controller is configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bit PCUSB. Remark: On reset, the USB block is disabled (PCUSB = 0). 2. Clock: see Table 4–54. 3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to PINMODE5 (Section 9–5). 4.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 289.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 290.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller VBUS BUS MASTER INTERFACE DMA ENGINE USB_CONNECT1, USB_CONNECT2 REGISTER INTERFACE EP_RAM ACCESS CONTROL SERIAL INTERFACE ENGINE USB ATX AHB BUS DMA interface (AHB master) USB_D+1, USB_D+2 USB_D-1, USB_D-2 USB_UP_LED1, USB_UP_LED2 register interface (AHB slave) EP_RAM (4K) USB DEVICE BLOCK Fig 45. USB device controller block diagram 5.1 Analog transceiver The USB Device Controller has a built-in analog transceiver (ATX).
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller 5.5 DMA engine and bus master interface When enabled for an endpoint, the DMA Engine transfers data between RAM on the AHB bus and the endpoint’s buffer in EP_RAM. A single DMA channel is shared between all endpoints. When transferring data, the DMA Engine functions as a master on the AHB bus through the bus master interface. 5.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Once data has been received or sent, the endpoint buffer can be read or written. How this is accomplished depends on the endpoint’s type and operating mode. The two operating modes for each endpoint are Slave (CPU-controlled) mode, and DMA mode. In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the Register Interface. See Section 13–13 “Slave mode operation” for a detailed description of this mode.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller 8.1 Power requirements The USB protocol insists on power management by the device. This becomes very critical if the device draws power from the bus (bus-powered device). The following constraints should be met by a bus-powered device: 1. A device in the non-configured state should draw a maximum of 100 mA from the bus. 2. A configured device can draw only up to what is specified in the Max Power field of the configuration descriptor.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller After entering the suspend state with DEV_CLK_EN and AHB_CLK_EN cleared, the DEV_CLK_ON and AHB_CLK_ON will be cleared when the corresponding clock turns off. When both bits are zero, USB_NEED_CLK will be low, indicating that the chip can be put into Power-down mode by writing to the PCON register. The status of USB_NEED_CLK can be read from the USBIntSt register.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 293.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 294. USB Port Select register (USBPortSel - address 0xFFE0 C110) bit description Bit Symbol Value Description Reset value 1:0 PORTSEL 0x0 The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D−1.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 296. USB Clock Status register (USBClkSt - 0xFFE0 CFF8) bit description Bit Symbol Description Reset value 0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 1 DEV_CLK_ON Device clock on. The usbclk input to the device controller is active. 0 2 - Reserved, user software should not write ones to reserved bits.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 297. USB Interrupt Status register (USBIntSt - address 0xE01F C1C0) bit description Bit Symbol Description Reset value 8 USB_NEED_CLK 0 USB need clock indicator. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 299. USB Device Interrupt Status register (USBDevIntSt - address 0xFFE0 C200) bit description Bit Symbol Description 6 RxENDPKT The current packet in the endpoint buffer is transferred to the CPU. 0 7 TxENDPKT The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). 0 8 EP_RLZED Endpoints realized.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 302.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller 9.3.6 USB Device Interrupt Priority register (USBDevIntPri - 0xFFE0 C22C) Writing one to a bit in this register causes the corresponding interrupt to be routed to the USB_INT_REQ_HP interrupt line. Writing zero causes the interrupt to be routed to the USB_INT_REQ_LP interrupt line. Either the EP_FAST or FRAME interrupt can be routed to USB_INT_REQ_HP, but not both.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 308. USB Endpoint Interrupt Status register (USBEpIntSt - address 0xFFE0 C230) bit description Bit Symbol Description Reset value 0 EP0RX Endpoint 0, Data Received Interrupt bit. 0 1 EP0TX Endpoint 0, Data Transmitted Interrupt bit or sent a NAK. 0 2 EP1RX Endpoint 1, Data Received Interrupt bit. 0 3 EP1TX Endpoint 1, Data Transmitted Interrupt bit or sent a NAK.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 309.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Bit Symbol Bit Symbol 15 14 13 12 11 10 9 8 EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX 7 6 5 4 3 2 1 0 EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX Table 312. USB Endpoint Interrupt Clear register (USBEpIntClr - address 0xFFE0 C238) bit description Bit Symbol Value Description Reset value 31:0 See USBEpIntClr bit allocation table above 0 No effect.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 315.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Since all the realized endpoints occupy EP_RAM space, the total EP_RAM requirement is N ∑ TotalEPRAMspace = 32 + EPRAMspace ( n ) n=0 where N is the number of realized endpoints. Total EP_RAM space should not exceed 4096 bytes (4 kB, 1 kwords). 9.5.2 USB Realize Endpoint register (USBReEp - 0xFFE0 C244) Writing one to a bit in this register causes the corresponding endpoint to be realized. Writing zeros causes it to be unrealized.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller USBReEp |= (UInt32) ((0x1 << endpt)); /* Load Endpoint index Reg with physical endpoint no.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller MPS_EP0 ENDPOINT INDEX MPS_EP31 The Endpoint Index is set via the USBEpIn register. MPS_EP0 to MPS_EP31 are accessed via the USBMaxPSize register. Fig 46. USB MaxPacketSize register array indexing 9.6 USB transfer registers The registers in this group are used for transferring data between endpoint buffers and RAM in Slave mode operation. See Section 13–13 “Slave mode operation”. 9.6.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 322. USB Receive Packet Length register (USBRxPlen - address 0xFFE0 C220) bit description Bit Symbol 9:0 10 11 Description Reset value PKT_LNGTH - The remaining number of bytes to be read from the currently selected endpoint’s buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt. 0 DV Data valid. This bit is useful for isochronous endpoints.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 324. USB Transmit Packet Length register (USBTxPLen - address 0xFFE0 C224) bit description Bit Symbol 9:0 PKT_LNGTH - 31:10 - Value Description Reset value The remaining number of bytes to be written to the 0x000 selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 326. USB Command Code register (USBCmdCode - address 0xFFE0 C210) bit description Bit Symbol Value Description 7:0 - - Reserved, user software should not write ones to reserved NA bits. The value read from a reserved bit is not defined. 15:8 CMD_PHASE The command phase: 0x01 Read 0x02 Write 0x05 Command 23:16 CMD_CODE/ CMD_WDATA 31:24 - Reset value 0x00 This is a multi-purpose field.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Bit Symbol Bit Symbol 15 14 13 12 11 10 9 8 EP15 EP14 EP13 EP12 EP11 EP10 EP9 EP8 7 6 5 4 3 2 1 0 EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 Table 329. USB DMA Request Status register (USBDMARSt - address 0xFFE0 C250) bit description Bit Symbol Value Description Reset value 0 EP0 0 Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0).
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Software can also use this register to initiate a DMA transfer to proactively fill an IN endpoint buffer before an IN token packet is received from the host. USBDMARSet is a write only register. The USBDMARSet bit allocation is identical to the USBDMARSt register (Table 13–328). Table 331.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller 9.8.6 USB EP DMA Enable register (USBEpDMAEn - 0xFFE0 C288) Writing one to a bit to this register will enable the DMA operation for the corresponding endpoint. Writing zero has no effect.The DMA cannot be enabled for control endpoints EP0 and EP1. USBEpDMAEn is a write only register. Table 334.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 336. USB DMA Interrupt Status register (USBDMAIntSt - address 0xFFE0 C290) bit description Bit Symbol 0 EOT Value Description End of Transfer Interrupt bit. 0 2 At least one bit in the USBEoTIntSt is set. NDDR New DD Request Interrupt bit. 0 0 All bits in the USBNDDRIntSt register are 0. 1 At least one bit in the USBNDDRIntSt is set. 0 All bits in the USBSysErrIntSt register are 0.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 338. USB End of Transfer Interrupt Status register (USBEoTIntSt - address 0xFFE0 C2A0s) bit description Bit Symbol 31:0 EPxx Value Description Reset value Endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request. 0 0 There is no End of Transfer interrupt request for endpoint xx. 1 There is an End of Transfer Interrupt request for endpoint xx. 9.8.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller 9.8.14 USB New DD Request Interrupt Clear register (USBNDDRIntClr - 0xFFE0 C2B0) Writing one to a bit in this register clears the corresponding bit in the USBNDDRIntSt register. Writing zero has no effect. USBNDDRIntClr is a write only register. Table 342.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 345. USB System Error Interrupt Clear register (USBSysErrIntClr - address 0xFFE0 C2BC) bit description Bit Symbol 31:0 EPxx Value Description Reset value Clear endpoint xx (2 ≤ xx ≤ 31) System Error Interrupt request. 0 0 No effect. 1 Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register. 9.8.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller register to request low priority interrupt handling. However, the USBDevIntPri register can route either the FRAME or the EP_FAST bit to the USB_INT_REQ_HP bit in the USBIntSt register. Only one of the EP_FAST and FRAME interrupt events can be routed to the USB_INT_REQ_HP bit. If routing both bits to USB_INT_REQ_HP is attempted, both interrupt events are routed to USB_INT_REQ_LP.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller interrupt event on EPn Slave mode USBEpIntSt from other Endpoints . . . . FRAME EP_FAST EP_SLOW . . . . n USBEpIntEn[n] USBDevIntSt USBDevIntPri[0] . . . . . . . . . USBEpIntPri[n] .. . . . . . USBDevIntPri[1] ERR_INT USBIntSt USBDMARSt USB_INT_REQ_HP USB_INT_REQ_LP USB_INT_REQ_DMA to DMA engine n to VIC channel #22 EN_USB_INTS USBEoTIntST DMA Mode 0 . . . . 31 USBNDDRIntSt 0 USBDMAIntSt . . . .
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller 11. Serial interface engine command description The functions and registers of the Serial Interface Engine (SIE) are accessed using commands, which consist of a command code followed by optional data bytes (read or write action). The USBCmdCode (Table 13–326) and USBCmdData (Table 13–327) registers are used for these accesses. A complete access consists of two phases: 1.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 347.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 349. Configure Device Register bit description Bit Symbol Description Reset value 0 CONF_DEVICE Device is configured. All enabled non-control endpoints will respond. This bit is cleared by hardware when a bus reset occurs. When set, the UP_LED signal is driven LOW if the device is not in the suspended state (SUS=0). 7:1 - Reserved, user software should not write ones to reserved bits.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller 11.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2 bytes) Returns the frame number of the last successfully received SOF. The frame number is eleven bits wide. The frame number returns least significant byte first. In case the user is only interested in the lower 8 bits of the frame number, only the first byte needs to be read.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 351. Set Device Status Register bit description Bit Symbol 3 SUS_CH Value Description Reset value Suspend (SUS) bit change indicator. The SUS bit can toggle because: • • • 0 The device goes into the suspended state. The device is disconnected. The device receives resume signalling on its upstream port. This bit is cleared when read. 4 0 SUS bit not changed. 1 SUS bit changed.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 352. Get Error Code Register bit description Bit Symbol Value Description Reset value 3:0 EC Error Code. 0x0 4 EA 7:5 - 0000 No Error. 0001 PID Encoding Error. 0010 Unknown PID. 0011 Unexpected Packet - any packet sequence violation from the specification. 0100 Error in Token CRC. 0101 Error in Data CRC. 0110 Time Out Error. 0111 Babble. 1000 Error in End of Packet. 1001 Sent/Received NAK.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller 11.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional)) The Select Endpoint command initializes an internal pointer to the start of the selected buffer in EP_RAM. Optionally, this command can be followed by a data read, which returns some additional information on the packet(s) in the endpoint buffer(s). The command code of the Select Endpoint command is equal to the physical endpoint number.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 354. Select Endpoint Register bit description Bit Symbol 6 7 Value Description B_2_FULL Reset value The buffer 2 status. - 0 0 Buffer 2 is empty. 1 Buffer 2 is full. - Reserved, user software should not write ones to reserved bits. NA The value read from a reserved bit is not defined. 11.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 355. Set Endpoint Status Register bit description Bit Symbol 5 DA 6 7 Value Description Reset value Disabled endpoint bit. 0 0 The endpoint is enabled. 1 The endpoint is disabled. RF_MO Rate Feedback Mode. 0 0 Interrupt endpoint is in the Toggle mode. 1 Interrupt endpoint is in the Rate Feedback mode. This means that transfer takes place without data toggle bit. CND_ST Conditional Stall bit.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Internally, there is a hardware FIFO status flag called Buffer_Full. This flag is set by the Validate Buffer command and cleared when the data has been sent on the USB bus and the buffer is empty. A control IN buffer cannot be validated when its corresponding OUT buffer has the Packet Over-written (PO) bit (see the Clear Buffer Register) set or contains a pending SETUP packet.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller – Clear all DMA interrupts using USBEoTIntClr, USBNDDRIntClr, and USBSysErrIntClr. – Prepare the UDCA in system memory. – Write the desired address for the UDCA to USBUDCAH (for example 0x7FD0 0000). – Enable the desired endpoints for DMA operation using USBEpDMAEn. – Set EOT, DDR, and ERR bits in USBDMAIntEn. 10.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller endpoints, the next packet will be received irrespective of whether the buffer has been cleared. Any data not read from the buffer before the end of the frame is lost. See Section 13–15 “Double buffered endpoint operation” for more details. If the software clears RD_EN before the entire packet is read, reading is terminated, and the data remains in the endpoint’s buffer.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller 14.2 USB device communication area The CPU and DMA controller communicate through a common area of memory, called the USB Device Communication Area, or UDCA. The UDCA is a 32-word array of DMA Descriptor Pointers (DDPs), each of which corresponds to a physical endpoint. Each DDP points to the start address of a DMA Descriptor, if one is defined for the endpoint.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller In DMA mode, the bits corresponding to Interrupt on NAK for Bulk OUT and Interrupt OUT endpoints (INAK_BO and INAK_IO) should be set to 0 using the SIE Set Mode command (Section 13–11.3). 14.4 The DMA descriptor DMA transfers are described by a data structure called the DMA Descriptor (DD). DDs are placed in the USB RAM. These descriptors can be located anywhere in the USB RAM at word-aligned addresses.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Table 357.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller 14.4.6 DMA_buffer_length This indicates the depth of the DMA buffer allocated for transferring the data. The DMA engine will stop using this descriptor when this limit is reached and will look for the next descriptor. In Normal mode operation, software sets this value for both IN and OUT endpoints. In ATLE mode operation, software sets this value for IN endpoints only.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller 14.4.11 LS_byte_extracted Used in ATLE mode. When set, this bit indicates that the Least Significant Byte (LSB) of the transfer length has been extracted. The extracted size is reflected in the DMA_buffer_length field, bits 23:16. 14.4.12 MS_byte_extracted Used in ATLE mode. When set, this bit indicates that the Most Significant Byte (MSB) of the transfer size has been extracted.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller If a new descriptor has to be read, the DMA engine will calculate the location of the DDP for this endpoint and will fetch the start address of the DD from this location. A DD start address at location zero is considered invalid. In this case the NDDR interrupt is raised. All other word-aligned addresses are considered valid.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller USB transfer end completion - If the current packet is fully transferred and its size is less than the Max_packet_size field, and the end of the DMA buffer is still not reached, the USB transfer end completion occurs. The DD will be written back to the memory with DD_retired set and DD_Status set to the DataUnderrun completion code. The EOT interrupt is raised for this endpoint.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller The isochronous packet size is stored in memory as shown in figure 32. Each word in the packet size memory shown is divided into fields: Frame_number (bits 31 to 17), Packet_valid (bit 16), and Packet_length (bits 15 to 0). The space allocated for the packet size memory for a given DD should be DMA_buffer_length words in size – one word for each packet to transfer.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller Next_DD_Pointer W0 NULL DMA_buffer_length W1 Max_packet_size 0x000A Isochronous_endpoint 0x0 Next_DD_Valid 1 DMA_mode 0 0 DMA_buffer_start_addr W2 0x80000000 Present_DMA_Count ATLE settings Packet_Valid DD_Status 0x0 NA NA 0x0 DD_Retired W3 0 Isocronous_packetsize_memory_address W4 0x60000000 after 4 packets W0 0x0 W1 0x000A0010 FULL 0x80000035 W2 W3 0x4 - - 0x1 0 frame_ number Packet_Valid Packet_Lengt
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller data to be sent data in packets data to be stored in USB by host driver as seen on USB RAM by DMA engine 160 bytes 64 bytes DMA_buffer_start_addr of DD1 160 bytes 64 bytes 32 bytes 32 bytes 100 bytes 100 bytes 64 bytes DMA_buffer_start_addr of DD2 4 bytes Fig 50.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller In ATLE mode, the last buffer length to be transferred always ends with a short or empty packet indicating the end of the USB transfer. If the concatenated transfer lengths are such that the USB transfer ends on a MaxPacketSize packet boundary, the (NDIS) host will send an empty packet to mark the end of the USB transfer.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller 14.7.4 Ending the packet transfer The DMA engine proceeds with the transfer until the number of bytes specified in the field DMA_buffer_length is transferred to or from the USB RAM. Then the EOT interrupt will be generated. If this happens in the middle of the packet, the linked DD will get loaded and the remaining part of the packet gets transferred to or from the address pointed by the new DD.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller 5. Software sends the SIE Select Endpoint command to read the Select Endpoint Register and test the FE bit. Software finds that the active buffer (B_2) has data (FE=1). Software clears the endpoint interrupt and begins reading the contents of B_2. 6. The host resends the third packet which device hardware places in B_1. An endpoint interrupt is generated. 7.
UM10237 NXP Semiconductors Chapter 13: LPC24XX USB device controller 11. Both B_1 and B_2 are empty, and the active buffer is B_2. The next packet written by software will go into B_2. In DMA mode, switching of the active buffer is handled automatically in hardware. For Bulk IN endpoints, proactively filling an endpoint buffer to take advantage of the double buffering can be accomplished by manually starting a packet transfer using the USBDMARSet register. 15.
UM10237 Chapter 14: LPC24XX USB Host controller Rev. 02 — 19 December 2008 User manual 1. Basic configuration The USB controller is configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bit PCUSB. Remark: On reset, the USB block is disabled (PCUSB = 0). 2. Clock: see Table 4–54. 3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to PINMODE5 (Section 9–5). 4.
UM10237 NXP Semiconductors Chapter 14: LPC24XX USB Host controller • OpenHCI specifies the operation and interface of the USB Host Controller and SW Driver – USBOperational: Process Lists and generate SOF Tokens. – USBReset: Forces reset signaling on the bus, SOF disabled. – USBSuspend: Monitor USB for wakeup activity. – USBResume: Forces resume signaling on the bus. • The Host Controller has four USB states visible to the SW Driver. • HCCA register points to Interrupt and Isochronous Descriptors List.
UM10237 NXP Semiconductors Chapter 14: LPC24XX USB Host controller Table 359.
UM10237 NXP Semiconductors Chapter 14: LPC24XX USB Host controller Table 360. USB Host register address definitions Name Address R/W[1] Function Reset value HcRevision 0xFFE0 C000 R BCD representation of the version of the HCI specification that is implemented by the Host Controller. 0x10 HcControl 0xFFE0 C004 R/W Defines the operating modes of the HC. 0x0 HcCommandStatus 0xFFE0 C008 R/W This register is used to receive the commands from the 0x0 Host Controller Driver (HCD).
UM10237 NXP Semiconductors Chapter 14: LPC24XX USB Host controller Table 360. USB Host register address definitions …continued Name Address R/W[1] Function Reset value HcRhStatus 0xFFE0 C050 R/W This register is divided into two parts. The lower D-word represents the hub status field and the upper word represents the hub status change field. 0x0 HcRhPortStatus[1] 0xFFE0 C054 R/W Controls and reports the port events on a per-port basis.
UM10237 Chapter 15: LPC24XX USB OTG controller Rev. 02 — 19 December 2008 User manual 1. Basic configuration The USB controller is configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bit PCUSB. Remark: On reset, the USB block is disabled (PCUSB = 0). 2. Clock: see Table 4–54. 3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to PINMODE5 (Section 9–5). 4.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller support an OTG connection. The communication between the register interface and an external OTG transceiver is handled through an I2C interface and through the external OTG transceiver interrupt signal. For USB connections that use the device or host controller only (not OTG), the ports use an embedded USB Analog Transceiver (ATX).
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller Table 361. USB OTG port 1 pins Pin name Direction Description Pin category VBUS I VBUS status input. When this function is not enabled via its corresponding PINSEL register, it is driven HIGH internally.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller 1. Use the internal USB transceiver for USB signalling and use the external OTG transceiver for OTG functionality only (see Figure 15–53). This option uses the internal transceiver in VP/VM mode. 2. Use the external OTG transceiver in VP/VM mode for OTG functionality and USB signalling (see Figure 15–54). In both cases port U2 is connected as a host. Solution one uses fewer pins.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller VDD RSTOUT RESET_N OE_N/INT_N USB_TX_E1 USB_TX_DP1 DAT_VP USB_TX_DM1 SE0_VM RCV USB_RCV1 USB_RX_DP1 VP VBUS USB_RX_DM1 VM ID VDD ISP1301 LPC24XX ADR/PSW DP 33 Ω DM 33 Ω USB MINI-AB connector VSS SPEED SUSPEND USB_SCL1 SCL USB_SDA1 SDA INT_N USB_INT1 VDD USB_UP_LED1 002aac711 Fig 54. USB OTG port configuration: VP_VM mode UM10237_2 User manual © NXP B.V. 2008. All rights reserved. Rev.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller 6.2 Connecting USB as a two-port host Both ports U1 and U2 are connected as hosts using an embedded USB transceiver. There is no OTG functionality on either port.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller VDD USB_UP_LED1 USB_D+1 33 Ω D+ USB_D−1 33 Ω D− 15 kΩ 15 kΩ USB-A connector VDD VBUS USB_PWRD1 USB_OVRCR1 VSS USB_PPWR1 FLAGA ENA 5V LM3526-L IN OUTA LPC24XX VDD USB_UP_LED2 VDD USB_CONNECT2 USB_D+2 33 Ω D+ USB_D−2 33 Ω D− VBUS USB-B connector VBUS VSS 002aac710 Fig 56. USB OTG port configuration: port U1 host, port U2 device 7.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller Table 362.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller 7.2 OTG Interrupt Status Register (OTGIntSt - 0xE01F C100) Bits is this register are set by hardware when the interrupt event occurs during the HNP handoff sequence. See Section 15–8 for more information on when these bits are set. Table 364. OTG Interrupt Status register (OTGIntSt - address 0xE01F C100) bit description Bit Symbol Description Reset Value 0 TMR Timer time-out. 0 1 REMOVE_PU Remove pull-up.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller 2. Free running mode: an interrupt is generated at the end of TIMEOUT_CNT (see Section 15–7.7 “OTG Timer Register (OTGTmr - 0xFFE0 C114)”), the TMR bit is set, and the timer value is reloaded into the counter. The timer is not disabled in this mode. Table 365. OTG Status Control register (OTGStCtrl - address 0xFFE0 C110) bit description Bit Symbol Description Reset Value 1:0 PORT_FUNC Controls the function of ports U1 and U2.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller OTGStCtrl PORT_FUNC[0] = 0 DEVICE CONTROLLER PORT_FUNC[1] = 0 port1 U1 U2 port1 HOST CONTROLLER port2 Fig 57. Port selection for PORT_FUNC bit 0 = 0 and PORT_FUNC bit 1 = 0. Table 366. Port function truth table PORT_FUNC[1] = 0 PORT_FUNC[1] = 1 PORT_FUNC[0] = 0 PORT_FUNC[0] = 1 U1 = device (OTG) U1 = host (OTG) U2 = host U2 = host reserved U1 = host U2 = device 7.7 OTG Timer Register (OTGTmr - 0xFFE0 C114) Table 367.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller Table 368. OTG_clock_control register (OTG_clock_control - address 0xFFE0 CFF4) bit description Bit Symbol 1 DEV_CLK_EN 2 3 Value Device clock enable 0 Disable the Device clock. 1 Enable the Device clock. I2C_CLK_EN I2C clock enable I2C 0 Disable the 1 Enable the I2C clock. OTG_CLK_EN AHB_CLK_EN 0 Disable the OTG clock. Enable the OTG clock. AHB master clock enable - 0 clock.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller Table 369. OTG_clock_status register (OTGClkSt - address 0xFFE0 CFF8) bit description Bit Symbol 4 AHB_CLK_ON 31:5 Value - Description Reset Value AHB master clock status. 0 0 AHB clock is not available. 1 AHB clock is available. NA Reserved, user software should not write ones NA to reserved bits. The value read from a reserved bit is not defined. 7.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller Table 372. I2C status register (I2C_STS - address 0xFFE0 C304) bit description Bit Symbol Value Description Reset Value 0 TDI 0 1 2 3 4 Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions. 0 Transaction has not completed. 1 Transaction completed. AFI Arbitration Failure Interrupt.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller Table 372. I2C status register (I2C_STS - address 0xFFE0 C304) bit description Bit Symbol Value Description 8 RFF 9 10 11 Receive FIFO Full (RFF). This bit is set when the RX FIFO is full 0 and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller Table 373. I2C Control register (I2C_CTL - address 0xFFE0 C308) bit description Bit Symbol 3 DRMIE 4 5 6 7 8 Value Description Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which 0 signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low. 0 Disable the DRMI interrupt. 1 Enable the DRMI interrupt.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller 7.15 I2C Clock Low Register (I2C_CLKLO - 0xFFE0 C310) The CLK register holds a terminal count for counting 48 MHz clock cycles to create the low period of the slower I2C serial clock, SCL. Table 375. I2C_CLKLO register (I2C_CLKLO - address 0xFFE0 C310) bit description Bit Symbol Description Reset Value 7:0 CDLO Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low. 0xB9 7.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller 8. HNP support This section describes the hardware support for the Host Negotiation Protocol (HNP) provided by the OTG controller. When two dual-role OTG devices are connected to each other, the plug inserted into the mini-AB receptacle determines the default role of each device.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller OHCI STACK HOST CONTROLLER OTG CONTROLLER OTG STACK USB BUS MUX DEVICE CONTROLLER DEVICE STACK I2C CONTROLLER ISP1301 Fig 59. USB OTG controller with software stack 8.1 B-device: peripheral to host switching In this case, the default role of the OTG controller is peripheral (B-device), and it switches roles from Peripheral to Host.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller idle B_HNP_TRACK = 0 no B_HNP_TRACK = 1 ? set HNP_FAILURE, clear B_HNP_TRACK, clear PU_REMOVED no bus suspended ? no disconnect device controller from U1 set REMOVE_PU yes PU_REMOVED set? PU_REMOVED set? reconnect port U1 to the device controller bus reset/resume detected? yes no reconnect port U1 to the device controller wait 25 μs for bus to settle yes yes bus reset/resume detected? connect from A-device detected? no s
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller b_peripheral when host sends SET_FEATURE with b_hnp_enable, set B_HNP_TRACK no REMOVE_PU set? yes remove D+ pull-up, set PU_REMOVED go to go to b_wait_acon b_peripheral HNP_FAILURE set? yes add D+ pull-up no no HNP_SUCCESS set? yes go to b_host Fig 61.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; Add D+ pull-up /* Add D+ pull-up through ISP1301 */ OTG_I2C_TX = 0x15A; // Send ISP1301 address, R/W=0 OTG_I2C_TX = 0x006; // Send OTG Control (Set) register address OTG_I2C_TX = 0x201; // Set DP_PULLUP bit, send STOP condition /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; 8.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller idle A_HNP_TRACK = 0 no A_HNP_TRACK = 1 ? set HNP_FAILURE, clear A_HNP_TRACK disconnect host controller from U1 no no bus suspended ? resume detected ? yes yes connnect host controller back to U1 yes yes bus reset detected? resume detected? no no no OTG timer expired? (TMR =1 ) yes clear A_HNP_TRACK set HNP_SUCCESS connect device to U1 by clearing PORT_FUNC[0] Fig 62.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller a_host when host sends SET_FEATURE with a_hnp_enable, set A_HNP_TRACK set BDIS_ACON_EN in external OTG transceiver load and enable OTG timer suspend host on port 1 go to a_suspend no no no TMR set? HNP_SUCCESS set? yes HNP_FAILURE set? yes yes clear BDIS_ACON_EN bit in external OTG transceiver discharge VBUS stop the OTG timer stop OTG timer go to a_peripheral clear BDIS_ACON_EN bit in external OTG transceiver go to go to
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller Set BDIS_ACON_EN in external OTG transceiver /* Set BDIS_ACON_EN OTG_I2C_TX = 0x15A; OTG_I2C_TX = 0x004; OTG_I2C_TX = 0x210; in // // // ISP1301 */ Send ISP1301 address, R/W=0 Send Mode Control 1 (Set) register address Set BDIS_ACON_EN bit, send STOP condition /* Wait for TDI to be set */ while (!(OTG_I2C_STS & TDI)); /* Clear TDI */ OTG_I2C_STS = TDI; Clear BDIS_ACON_EN in external OTG transceiver /* Set BDIS_ACON_EN OTG_I2C_TX = 0x15A
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller Load and enable OTG timer /* The following assumes that the OTG timer has previously been */ /* configured for a time scale of 1 ms (TMR_SCALE = “10”) /* and monoshot mode (TMR_MODE = 0) */ */ /* Load the timeout value to implement the a_aidl_bdis_tmr timer */ /* the minimum value is 200 ms */ OTG_TIMER = 200; /* Enable the timer */ OTG_STAT_CTRL |= TMR_EN; Stop OTG timer /* Disable the timer – causes TMR_CNT to be reset to 0 */ OTG_STAT
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller ahb_slave_clk cclk PCUSB REGISTER INTERFACE ahb_master_clk CLOCK SWITCH EN AHB_CLK_ON ahb_need_clk AHB_CLK_EN USB CLOCK DIVIDER usbclk (48 MHz) CLOCK SWITCH EN DEV_CLK_ON DEVICE CONTROLLER dev_dma_need_clk dev_need_clk DEV_CLK_EN CLOCK SWITCH EN host_dma_need_clk HOST_CLK_ON HOST CONTROLLER host_need_clk HOST_CLK_EN CLOCK SWITCH EN OTG_CLK_ON OTG CONTROLLER USB_NEED_CLK OTG_CLK_EN CLOCK SWITCH EN I2C_CLK_ON I2C CONT
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller The dev_dma_need_clk signal is asserted on any Device controller DMA access to memory. Once asserted, it remains active for 2 ms (2 frames), to help assure that DMA throughput is not affected by any latency associated with re-enabling ahb_master_clk. 2 ms after the last DMA access, dev_dma_need_clk is de-asserted to help conserve power. This signal allows AHB_CLK_EN to be cleared during normal operation. 9.1.
UM10237 NXP Semiconductors Chapter 15: LPC24XX USB OTG controller 4. Enable the desired USB pin functions by writing to the corresponding PINSEL registers. 5. Follow the appropriate steps in Section 13–12 “USB device controller initialization” to initialize the device controller. 6. Follow the guidelines given in the OpenHCI specification for initializing the host controller. UM10237_2 User manual © NXP B.V. 2008. All rights reserved. Rev.
UM10237 Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter (UART) 0/2/3 Rev. 02 — 19 December 2008 User manual 1. Basic configuration The UART0/2/3 peripherals are configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bits PCUART0/2/3. Remark: On reset, UART0 is enabled (PCUART0 = 1), and UART2/3 are disabled (PCUART2/3 = 0). 2.
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter 4. Register description Each UART contains registers as shown in Table 16–377. The Divisor Latch Access Bit (DLAB) is contained in UnLCR7 and enables access to the Divisor Latches. UM10237_2 User manual © NXP B.V. 2008. All rights reserved. Rev.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors UM10237_2 User manual Table 377.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Generic Description Name Line Status Register SCR Scratch Pad Register ACR Auto-baud Control Register
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter 16.4.1 UARTn Receiver Buffer Register (U0RBR - 0xE000 C000, U2RBR 0xE007 8000, U3RBR - 0xE007 C000 when DLAB = 0, Read Only) The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit.
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed. The Divisor Latch Access Bit (DLAB) in UnLCR must be one in order to access the UARTn Divisor Latches.
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter 4.5 UARTn Interrupt Identification Register (U0IIR - 0xE000 C008, U2IIR 0xE007 8008, U3IIR - 0x7008 C008, Read Only) The UnIIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an UnIIR access. If an interrupt occurs during an UnIIR access, the interrupt is recorded for the next UnIIR access.
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter The UARTn RDA interrupt (UnIIR[3:1] = 010) shares the second level priority with the CTI interrupt (UnIIR[3:1] = 110). The RDA is activated when the UARTn Rx FIFO reaches the trigger level defined in UnFCR[7:6] and is reset when the UARTn Rx FIFO depth falls below the trigger level. When the RDA interrupt goes active, the CPU can read a block of data defined by the trigger level.
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter THRE = 1 and there have not been at least two characters in the UnTHR at one time since the last THRE = 1 event. This delay is provided to give the CPU time to write data to UnTHR without a THRE interrupt to decode and service. A THRE interrupt is set immediately if the UARTn THR FIFO has held two or more characters at one time and currently, the UnTHR is empty.
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter Table 386: UARTn Line Control Register (U0LCR - address 0xE000 C00C, U2LCR - 0xE007 800C, U3LCR - 0xE007 C00C) bit description Bit Symbol 1:0 Word Length Select 2 3 Stop Bit Select Parity Enable 5:4 Parity Select 6 7 Break Control Divisor Latch Access Bit (DLAB) Value Description Reset Value 00 5 bit character length 0 01 6 bit character length 10 7 bit character length 11 8 bit character length
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter Table 387: UARTn Line Status Register (U0LSR - address 0xE000 C014, U2LSR - 0xE007 8014, U3LSR - 0xE007 C014, Read Only) bit description Bit Symbol 2 Value Description Parity Error (PE) Reset Value 0 When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0].
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter 4.9 UARTn Scratch Pad Register (U0SCR - 0xE000 C01C, U2SCR 0xE007 801C U3SCR - 0xE007 C01C) The UnSCR has no effect on the UARTn operation. This register can be written and/or read at user’s discretion. There is no provision in the interrupt interface that would indicate to the host that a read or write of the UnSCR has occurred.
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter 16.4.10.1 Auto-baud The UARTn auto-baud function can be used to measure the incoming baud-rate based on the ”AT" protocol (Hayes command). If enabled the auto-baud feature will measure the bit time of the receive data stream and set the divisor latch registers UnDLM and UnDLL accordingly. Auto-baud is started by setting the UnACR Start bit. Auto-baud can be stopped by clearing the UnACR Start bit.
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter 1. On UnACR Start bit setting, the baud-rate measurement counter is reset and the UARTn UnRSR is reset. The UnRSR baud rate is switch to the highest rate. 2. A falling edge on UARTn Rx pin triggers the beginning of the start bit. The rate measuring counter will start counting pclk cycles optionally pre-scaled by the fractional baud-rate generator. 3.
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop UARTn RX start bit LSB of 'A' or 'a' U1ACR start rate counter 16xbaud_rate 16 cycles b. Mode 1 (only start bit is used for auto-baud) Fig 65. Autobaud a) mode 0 and b) mode 1 waveform 4.
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter Table 391: IrDA Pulse Width FixPulseEn PulseDiv IrDA Transmitter Pulse width (µs) 1 2 8 × TPCLK 1 3 16 × TPCLK 1 4 32 × TPCLK 1 5 64 × TPCLK 1 6 128 × TPCLK 1 7 256 × TPCLK 4.
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter The value of MULVAL and DIVADDVAL should comply to the following conditions: 1. 0 < MULVAL ≤ 15 2. 0 ≤ DIVADDVAL < 15 3. DIVADDVAL
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter Calculating UART baudrate (BR) PCLK, BR DL est = PCLK/(16 x BR) DL est is an integer? True False DIVADDVAL = 0 MULVAL = 1 FR est = 1.5 Pick another FR est from the range [1.1, 1.9] DL est = Int(PCLK/(16 x BR x FR est)) FR est = PCLK/(16 x BR x DL est) False 1.1 < FR est < 1.9? True DIVADDVAL = table(FR est ) MULVAL = table(FR est ) DLM = DL est [15:8] DLL = DLest [7:0] End Fig 66.
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter Table 393. Fractional Divider setting look-up table 4.12.1.1 FR DivAddVal/ MulVal FR DivAddVal/ MulVal FR DivAddVal/ MulVal FR DivAddVal/ MulVal 1.000 0/1 1.250 1/4 1.500 1/2 1.750 3/4 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778 7/9 1.077 1/13 1.286 2/7 1.545 6/11 1.786 11/14 1.083 1/12 1.300 3/10 1.556 5/9 1.800 4/5 1.
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter Table 16–394 describes how to use TXEn bit in order to achieve software flow control. Table 394: UARTn Transmit Enable Register (U0TER - address 0xE000 C030, U2TER - 0xE007 8030, U3TER - 0xE007 C030) bit description Bit Symbol Description Reset Value 6:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
UM10237 NXP Semiconductors Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter UnTX UnTHR NTXRDY UnTSR TXDn UnBRG UnDLL NBAUDOUT UnDLM RCLK UnRX NRXRDY INTERRUPT UnRBR UnINTR UnRSR RXDn UnIER UnIIR UnFCR UnLSR UnSCR UnLCR PA[2:0] PSEL PSTB PWRITE PD[7:0] APB INTERFACE DDIS AR MR PCLK Fig 67. UART0, 2 and 3 block diagram UM10237_2 User manual © NXP B.V. 2008. All rights reserved. Rev.
UM10237 Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter (UART) 1 Rev. 02 — 19 December 2008 User manual 1. Basic configuration The UART1 peripheral is configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bits PCUART1. Remark: On reset, UART1 is enabled (PCUART1 = 1). 2. Peripheral clock: In the PCLK_SEL0 register (Table 4–56), select PCLK_UART1. 3. Baud rate: In register U1LCR (Table 17–405), set bit DLAB =1.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter 3. Pin description Table 395: UART1 Pin Description Pin Type RXD1 Input Description Serial Input. Serial receive data. TXD1 Output Serial Output. Serial transmit data. CTS1 Input Clear To Send. Active low signal indicates if the external modem is ready to accept transmitted data via TXD1 from the UART1.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors UM10237_2 User manual Table 396: UART1 register map Name Description Bit functions
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Name Description Bit functions and addresses MSB U1ACR U1FDR U1TER Reserved [31:10] Reserved [7:3] Fr
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter 4.1 UART1 Receiver Buffer Register (U1RBR - 0xE001 0000, when DLAB = 0 Read Only) The U1RBR is the top byte of the UART1 RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the “oldest” received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter (3) pclk UART1 baudrate = -------------------------------------------------------------------------------16 × ( 256 × U1DLM + U1DLL ) Table 399: UART1 Divisor Latch LSB Register (U1DLL - address 0xE001 0000 when DLAB = 1) bit description Bit Symbol Description Reset Value 7:0 DLLSB The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter Table 401: UART1 Interrupt Enable Register (U1IER - address 0xE001 0004 when DLAB = 0) bit description Bit Symbol 7 CTS Interrupt Enable Value Description Reset Value If auto-cts mode is enabled this bit enables/disables the 0 modem status interrupt generation on a CTS1 signal transition.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter Table 402: UART1 Interrupt Identification Register (U1IIR - address 0xE001 0008, Read Only) bit description Bit Symbol 3:1 IntId Value Description Reset Value Interrupt identification. U1IER[3:1] identifies an interrupt corresponding to the UART1 Rx FIFO. All other combinations of U1IER[3:1] not listed above are reserved (100,101,111). 011 1 - Receive Line Status (RLS).
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter wished to send a 105 character message and the trigger level was 10 characters, the CPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI interrupts (depending on the service routine) resulting in the transfer of the remaining 5 characters.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter It is the lowest priority interrupt and is activated whenever there is any state change on modem inputs pins, DCD, DSR or CTS. In addition, a low to high transition on modem input RI will generate a modem interrupt. The source of the modem interrupt can be determined by examining U1MSR[3:0]. A U1MSR read will clear the modem interrupt. 4.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter Table 405: UART1 Line Control Register (U1LCR - address 0xE001 000C) bit description Bit Symbol Value Description Reset Value 5:4 Parity Select 0 6 7 00 Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 01 Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 10 Forced "1" stick parity. 11 Forced "0" stick parity.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter Table 406: UART1 Modem Control Register (U1MCR - address 0xE001 0010) bit description Bit Symbol Value Description Reset value 6 RTSen 0 0 1 Enable auto-rts flow control. 7 CTSen 0 Disable auto-cts flow control. 1 Enable auto-cts flow control. Disable auto-rts flow control. 0 4.9 Auto-flow control If auto-RTS mode is enabled the UART1‘s receiver FIFO hardware controls the RTS1 output of the UART1.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter 17.4.9.2 Auto-CTS The Auto-CTS function is enabled by setting the CTSen bit. If Auto-CTS is enabled the transmitter circuitry in the U1TSR module checks CTS1 input before sending the next data byte. When CTS1 is active (low), the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS1 must be released before the middle of the last stop bit that is currently being sent.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter 4.10 UART1 Line Status Register (U1LSR - 0xE001 0014, Read Only) The U1LSR is a read-only register that provides status information on the UART1 TX and RX blocks.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter Table 408: UART1 Line Status Register (U1LSR - address 0xE001 0014, Read Only) bit description Bit Symbol 5 6 7 Value Description Transmitte r Holding Register Empty (THRE) Reset Value THRE is set immediately upon detection of an empty UART1 THR and is cleared on a U1THR write. Transmitte r Empty (TEMT) 0 U1THR contains valid data. 1 U1THR is empty.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter Table 409: UART1 Modem Status Register (U1MSR - address 0xE001 0018) bit description Bit Symbol Value Description Reset Value 5 DSR Data Set Ready State. Complement of input signal DSR. This bit is connected to U1MCR[0] in modem loopback mode. 0 6 RI Ring Indicator State. Complement of input RI. This bit is connected to U1MCR[2] in modem loopback mode. 0 7 DCD Data Carrier Detect State.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter Table 411: Auto-baud Control Register (U1ACR - address 0xE001 0020) bit description Bit Symbol 9 ABTOIntClr 31:10 - Value Description Reset value Auto-baud time-out interrupt clear bit (write only accessible). 0 0 Writing a 0 has no impact. 1 Writing a 1 will clear the corresponding interrupt in the U1IIR. NA 0 Reserved, user software should not write ones to reserved bits.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter 2 × P CLK PCLK ratemin = ------------------------- ≤ UART 1 baudrate ≤ ------------------------------------------------------------------------------------------------------------ = ratemax 16 × 2 15 16 × ( 2 + databits + paritybits + stopbits ) 4.15 Auto-baud modes When the software is expecting an ”AT" command, it configures the UART1 with the expected character format and sets the U1ACR Start bit.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop UARTn RX start bit LSB of 'A' or 'a' U0ACR start rate counter 16xbaud_rate 16 cycles 16 cycles a.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter Table 412: UART1 Fractional Divider Register (U1FDR - address 0xE001 0028) bit description Bit Function Value Description Reset value 3:0 DIVADDVAL 0 Baud-rate generation pre-scaler divisor value. If this field is 0 0, fractional baud-rate generator will not impact the UARTn baudrate. 7:4 MULVAL 1 Baud-rate pre-scaler multiplier value.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter Calculating UART baudrate (BR) PCLK, BR DL est = PCLK/(16 x BR) DL est is an integer? True False DIVADDVAL = 0 MULVAL = 1 FR est = 1.5 Pick another FR est from the range [1.1, 1.9] DL est = Int(PCLK/(16 x BR x FR est)) FR est = PCLK/(16 x BR x DL est) False 1.1 < FR est < 1.9? True DIVADDVAL = table(FR est ) MULVAL = table(FR est ) DLM = DL est [15:8] DLL = DLest [7:0] End Fig 71.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter Table 413. Fractional Divider setting look-up table 4.16.1.1 FR DivAddVal/ MulVal FR DivAddVal/ MulVal FR DivAddVal/ MulVal FR DivAddVal/ MulVal 1.000 0/1 1.250 1/4 1.500 1/2 1.750 3/4 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778 7/9 1.077 1/13 1.286 2/7 1.545 6/11 1.786 11/14 1.083 1/12 1.300 3/10 1.556 5/9 1.800 4/5 1.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter Although Table 17–414 describes how to use TxEn bit in order to achieve hardware flow control, it is strongly suggested to let UART1 hardware implemented auto flow control features take care of this, and limit the scope of TxEn to software flow control. LPC2400’s U1TER enables implementation of software and hardware flow control. When TXEn=1, UART1 transmitter will keep sending data as long as they are available.
UM10237 NXP Semiconductors Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter Status information from the U1TX and U1RX is stored in the U1LSR. Control information for the U1TX and U1RX is stored in the U1LCR. MODEM U1TX U1THR CTS DSR NTXRDY U1TSR TXD1 U1MSR RI U1BRG DCD DTR RTS U1DLL NBAUDOUT U1DLM RCLK U1MCR U1RX NRXRDY INTERRUPT U1RBR U1INTR U1RSR RXD1 U1IER U1IIR U1FCR U1LSR U1SCR U1LCR PA[2:0] PSEL PSTB PWRITE APB INTERFACE PD[7:0] DDIS AR MR PCLK Fig 72.
UM10237 Chapter 18: LPC24XX CAN controllers CAN1/2 Rev. 02 — 19 December 2008 User manual 1. How to read this chapter The CAN controller in available on parts LPC2458 and LPC2460/68/70/78. 2. Basic configuration The CAN1/2 peripherals are configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bits PCAN1/2. Remark: On reset, the CAN1/2 blocks are disabled (PCAN1/2 = 0). 2.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 4. Features 4.1 General CAN features • • • • • • • • • Compatible with CAN specification 2.0B, ISO 11898-1. Multi-master architecture with non destructive bit-wise arbitration. Bus access priority determined by the message identifier (11-bit or 29-bit). Guaranteed latency time for high priority messages. Programmable transfer rate (up to 1 Mbit/s). Multicast and broadcast message facility. Data length from 0 up to 8 bytes.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 6. CAN controller architecture The CAN Controller is a complete serial interface with both Transmit and Receive Buffers but without Acceptance Filter. CAN Identifier filtering is done for all CAN channels in a separate block (Acceptance Filter). Except for message buffering and acceptance filtering the functionality is similar to the PeliCAN concept.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 6.3 Transmit Buffers (TXB) The TXB represents a Triple Transmit Buffer, which is the interface between the Interface Management Logic (IML) and the Bit Stream Processor (BSP). Each Transmit Buffer is able to store a complete message which can be transmitted over the CAN network. This buffer is written by the CPU and read out by the BSP. 31 24 23 TX Frame info 16 15 unused TX DLC 87 unused 0 . . . 0 0 TX Priority TFS ID.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 31 24 23 RX Frame info 16 15 unused RX DLC 10 9 8 7 unused unused 0 ID Index RFS ID.28 ... ID.18 RID RX Data 4 RX Data 3 RX Data 2 RX Data 1 RDA RX Data 8 RX Data 7 RX Data 6 RX Data 5 RDB Descriptor Field Data Field BPM=bypass message Standard Frame Format (11-bit Identifier) 31 24 23 RX Frame info unused 16 15 unused RX DLC ID.28 10 9 8 7 unused 0 ID Index ... RFS ID.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Both self-tests are using the ‘Self Reception’ feature of the CAN Controller. With the Self Reception Request, the transmitted message is also received and stored in the receive buffer. Therefore the acceptance filter has to be configured accordingly. As soon as the CAN message is transmitted, a transmit and a receive interrupt are generated, if enabled.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 7. Memory map of the CAN block The CAN Controllers and Acceptance Filter occupy a number of APB slots, as follows: Table 416. Memory map of the CAN block Address Range Used for 0xE003 8000 - 0xE003 87FF Acceptance Filter RAM. 0xE003 C000 - 0xE003 C017 Acceptance Filter Registers. 0xE004 0000 - 0xE004 000B Central CAN Registers. 0xE004 4000 - 0xE004 405F CAN Controller 1 Registers.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 418.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 419.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 420. Mode register (CAN1MOD - address 0xE004 4000, CAN2MOD - address 0xE004 8000) bit description Bit Symbol Value 2 STM[3][6] Function Reset RM Value Set Self Test Mode. 0 x 0 x 0 0 0 x Reserved, user software should not write ones to reserved bits. 0 0 Test Mode. 0 x 0(normal) A transmitted message must be acknowledged to be considered successful.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 421. Command Register (CAN1CMR - address 0xE004 4004, CAN2CMR - address 0xE004 8004) bit description Bit Symbol Value 0[1][2] TR 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (no action) Do not abort the transmission. 1 (present) if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled. Release Receive Buffer. 0 (no action) Do not release the receive buffer.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 [2] If the Transmission Request or the Self-Reception Request bit was set '1' in a previous command, it cannot be cancelled by resetting the bits. The requested transmission may only be cancelled by setting the Abort Transmission bit. [3] The Abort Transmission bit is used when the CPU requires the suspension of the previously requested transmission, e.g. to transmit a more urgent message before.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 422. Global Status Register (CAN1GSR - address 0xE004 4008, CAN2GSR - address 0xE004 8008) bit description Bit Symbol Value 4 RS[4] 1 0 1 0 0 0 0 0 1 (receive) The CAN controller is receiving a message. Transmit Status. 0 (idle) The CAN controller is idle. 1 (transmit) The CAN controller is sending a message. Error Status. 0 (ok) Both error counters are below the Error Warning Limit.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 RX Error Counter = (CANxGSR AND 0x00FF0000) / 0x00010000 Note that a CPU-forced content change of the RX Error Counter is possible only if the Reset Mode was entered previously. An Error Status change (Status Register), an Error Warning or an Error Passive Interrupt forced by the new register content will not occur until the Reset Mode is cancelled again.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Bits 24-31 are captured when CAN arbitration is lost. At the same time, if the ALIE bit in CANIER is 1, the ALI bit in this register is set, and a CAN interrupt can occur. Once either of these bytes is captured, its value will remain the same until it is read, at which time it is released to capture a new value.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 423. Interrupt and Capture Register (CAN1ICR - address 0xE004 400C, CAN2ICR address 0xE004 800C) bit description Bit Symbol Value Function 8 IDI 0 (reset) 1 (set) ID Ready Interrupt -- this bit is set if the IDIE bit in 0 CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted).
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 423. Interrupt and Capture Register (CAN1ICR - address 0xE004 400C, CAN2ICR address 0xE004 800C) bit description Bit Symbol Value 20:16 ERRBIT 4:0[3] 21 Function Error Code Capture: when the CAN controller detects 0 a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 Start of Frame 00010 ID28 ...
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 423. Interrupt and Capture Register (CAN1ICR - address 0xE004 400C, CAN2ICR address 0xE004 800C) bit description Bit Symbol Value 31:24 ALCBIT[4] - Function Reset RM Value Set Each time arbitration is lost while trying to send on the 0 CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 424. Interrupt Enable Register (CAN1IER - address 0xE004 4010, CAN2IER - address 0xE004 8010) bit description Bit Symbol Function Reset RM Value Set 0 RIE Receiver Interrupt Enable. When the Receive Buffer Status is 'full', 0 the CAN Controller requests the respective interrupt. X 1 TIE1 Transmit Interrupt Enable for Buffer1.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 425. Bus Timing Register (CAN1BTR - address 0xE004 4014, CAN2BTR - address 0xE004 8014) bit description Bit Symbol Value Function Reset RM Value Set 9:0 BRP Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock. 0 13:10 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 (9) t TSEG1 = t SCL × ( TSEG1 + 1 ) (10) t TSEG2 = t SCL × ( TSEG2 + 1 ) 8.7 Error Warning Limit Register (CAN1EWL - 0xE004 4018, CAN2EWL 0xE004 8018) This register sets a limit on Tx or Rx errors at which an interrupt can occur. It can be read at any time but can only be written if the RM bit in CANmod is 1. The default value (after hardware reset) is 96. Table 426.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 427. Status Register (CAN1SR - address 0xE004 401C, CAN2SR - address 0xE004 801C) bit description Bit Symbol Value Function Reset RM Value Set 5 TS1 Transmit Status 1. 1 0 0(idle) There is no transmission from Tx Buffer 1. 1(transmit) The CAN Controller is transmitting a message from Tx Buffer 1. 6 ES Error Status. This bit is identical to the ES bit in the CANxGSR. 0 0 7 BS Bus Status.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 427. Status Register (CAN1SR - address 0xE004 401C, CAN2SR - address 0xE004 801C) bit description Bit Symbol Value Function Reset RM Value Set 22 ES Error Status. This bit is identical to the ES bit in the CANxGSR. 0 0 23 BS Bus Status. This bit is identical to the BS bit in the CANxGSR. 0 0 Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 8.9.1 ID index field The ID Index is a 10-bit field in the Info Register that contains the table position of the ID Look-up Table if the currently received message was accepted. The software can use this index to simplify message transfers from the Receive Buffer into the Shared Message Memory. Whenever bit 10 (BP) of the ID Index in the CANRFS register is 1, the current CAN message was received in acceptance filter bypass mode. 8.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 431. Receive Data register A (CAN1RDA - address 0xE004 4028, CAN2RDA - address 0xE004 8028) bit description Bit Symbol Function Reset RM Value Set 15:8 Data 2 If the DLC field in CANRFS ≥ 0010, this contains the first Data byte 0 of the current received message. X 23:16 Data 3 If the DLC field in CANRFS ≥ 0011, this contains the first Data byte 0 of the current received message.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 433. Transmit Frame Information Register (CAN1TFI[1/2/3] - address 0xE004 40[30/40/50], CAN2TFI[1/2/3] - 0xE004 80[30/40/50]) bit description Bit Symbol Function 7:0 PRIO If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 8.14 Transmit Identifier Register (CAN1TID[1/2/3] - 0xE004 40[34/44/54], CAN2TID[1/2/3] - 0xE004 80[34/44/54]) When the corresponding TBS bit in CANxSR is 1, software can write to one of these registers to define the Identifier field of the next transmit message. Bits not listed read as 0 and should be written as 0. The register assumes two different formats depending on the FF bit in CANTFI.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 8.16 Transmit Data Register B (CAN1TDB[1/2/3] - 0xE004 40[3C/4C/5C], CAN2TDB[1/2/3] - 0xE004 80[3C/4C/5C]) When the corresponding TBS bit in CANSR is 1, software can write to one of these registers to define the 5th through 8th data bytes of the next transmit message. The Data Length Code defines the number of transferred data bytes. The first bit transmitted is the most significant bit of TX Data Byte 1. Table 437.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 The CAN Controller wakes up (and sets WUI in the CAN Interrupt register if WUIE in the CAN Interrupt Enable register is 1) in response to a) a dominant bit on the CAN bus, or b) software clearing SM in the CAN Mode register. A sleeping CAN Controller, that wakes up in response to bus activity, is not able to receive an initial message, until after it detects Bus_Free (11 consecutive recessive bits).
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 438. Central Transit Status Register (CANTxSR - address 0xE004 0000) bit description Bit Symbol Description Reset Value 15:10 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 16 TCS1 When 1, all requested transmissions have been completed successfully 1 by the CAN1 controller (same as TCS in CAN1GSR).
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 440. Central Miscellaneous Status Register (CANMSR - address 0xE004 0008) bit description Bit Symbol Description 8 BS1 When 1, the CAN1 controller is currently involved in bus activities (same 0 as BS in CAN1GSR). 9 BS2 When 1, the CAN2 controller is currently involved in bus activities (same 0 as BS in CAN2GSR). 31:10 - Reset Value Reserved, user software should not write ones to reserved bits.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 12.2 Acceptance filter Bypass mode The Acceptance Filter Bypass Mode can be used for example to change the acceptance filter configuration during a running system, e.g. change of identifiers in the ID-Look-up Table memory. During this re-configuration, software acceptance filtering has to be used. It is recommended to use the ID ready Interrupt (ID Index) and the Receive Interrupt (RI).
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 If Standard (11 bit) Identifiers are used in the application, at least one of 3 tables in Acceptance Filter RAM must not be empty. If the optional “fullCAN mode” is enabled, the first table contains Standard identifiers for which reception is to be handled in this mode.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 The table of ranges of Extended Identifiers must contain an even number of entries, of the same form as in the individual Extended Identifier table. Like the Individual Extended table, the Extended Range must be arranged in ascending numerical order.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 443. Acceptance Filter Mode Register (AFMR - address 0xE003 C000) bit description Bit Symbol Value Description Reset Value 0 AccOff[2] 1 if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored. 1 1 AccBP[1] 1 All Rx messages are accepted on enabled CAN controllers.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 15.3 Standard Frame Individual Start Address Register (SFF_sa 0xE003 C004) Table 444. Standard Frame Individual Start Address Register (SFF_sa - address 0xE003 C004) bit description Bit Symbol Description Reset Value 1:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 15.5 Extended Frame Start Address Register (EFF_sa - 0xE003 C00C) Table 446. Extended Frame Start Address Register (EFF_sa - address 0xE003 C00C) bit description Bit Symbol Description Reset Value 1:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 10:2 EFF_sa[1] The start address of the table of individual Extended Identifiers in AF 0 Lookup RAM.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 15.7 End of AF Tables Register (ENDofTable - 0xE003 C014) Table 448. End of AF Tables Register (ENDofTable - address 0xE003 C014) bit description Bit Symbol Description Reset Value 1:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 11:2 EndofTable The address above the last active address in the last active AF table.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 15.10 LUT Error Register (LUTerr - 0xE003 C01C) Table 450. LUT Error Register (LUTerr - address 0xE003 C01C) bit description Bit Symbol Description Reset Value 0 LUTerr This read-only bit is set to 1 if the Acceptance Filter encounters an error 0 in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 16. Configuration and search algorithm The CAN Identifier Look-up Table Memory can contain explicit identifiers and groups of CAN identifiers for Standard and Extended CAN Frame Formats. They are organized as a sorted list or table with an increasing order of the Source CAN Channel (SCC) together with CAN Identifier in each section. SCC value equals CAN_controller - 1, i.e., SCC = 0 matches CAN1 and SCC = 1 matches CAN2.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Message disable bit Message disable bit Index 0, 1 SCC = 1 0 ID = 0x5A SCC = 1 0 ... Index 2, 3 SCC = 2 0 ... SCC = 3 0 ... Index 4, 5 SCC = 4 0 ... SCC = 5 0 ... Index 6, 7 SCC = 6 0 ... SCC = 6 0 ... Index 8, 9 SCC = 1 0 ID = 0x5A SCC = 1 0 ... Index 10, 11 SCC = 2 0 ... SCC = 3 0 ... Index 12, 13 SCC = 4 0 ... SCC = 5 0 ...
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 receive interrupt whenever a CAN message is accepted and received. Software has to move the received message out of the receive buffer from the according CAN controller into the user RAM. To cover dashboard like applications where the controller typically receives data from several CAN channels for further processing, the CAN Gateway block was extended by a so-called FullCAN receive function.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 17.1 FullCAN message layout Table 454. Format of automatically stored Rx messages Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 SEM [1:0] 0000 DLC 00000 8 7 6 5 0 F R 0000 F T R +4 Rx Data 4 Rx Data 3 Rx Data 2 Rx Data 1 +8 Rx Data 8 Rx Data 7 Rx Data 6 Rx Data 5 4 3 2 1 0 ID.28 ... ID.18 The FF, RTR, and DLC fields are as described in Table 18–428.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 START read 1st word SEM == 01? SEM == 11? this message has not been received since last check clear SEM, write back 1st word read 2nd and 3rd words read 1st word SEM == 00? most recently read 1st, 2nd, and 3rd words are from the same message Fig 82. Semaphore procedure for reading an auto-stored message UM10237_2 User manual © NXP B.V. 2008. All rights reserved. Rev.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 17.2 FullCAN interrupts The CAN Gateway Block contains a 2 kB ID Look-up Table RAM. With this size a maximum number of 146 FullCAN objects can be defined if the whole Look-up Table RAM is used for FullCAN objects only. Only the first 64 FullCAN objects can be configured to participate in the interrupt scheme. It is still possible to define more than 64 FullCAN objects.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Message disable bit Message disable bit 3 1 0 2 9 8 7 6 5 4 3 2 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 Index 0, 1 SCC 0 11-bit CAN ID SCC 0 11-bit CAN ID Index 2, 3 SCC 0 11-bit CAN ID SCC 0 11-bit CAN ID Index 4, 5 SCC 0 11-bit CAN ID SCC 0 11-bit CAN ID Index 6, 7 SCC 0 11-bit CAN ID SCC 0 11-bit CAN ID New: FullCAN Message Interrupt enable bit 3 2 1 0 FullCAN Explicit Sta
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 17.2.3 Setting the interrupt pending bits (IntPnd 63 to 0) The interrupt pending bit (IntPndx) gets asserted in case of an accepted FullCAN message and if the interrupt of the according FullCAN Object is enabled (enable bit FCANIntxEn) is set). During the last write access from the data storage of a FullCAN message object the interrupt pending bit of a FullCAN object (IntPndx) gets asserted. 17.2.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 semaphore bits 01 11 00 IntPndx look-up table access Write ID, SEM write D1 write D2 write SEM read clear SEM SEM read D1 read read D2 SEM MsgLostx message handler access ARM processor access Fig 85. Normal case, no messages lost 17.3.2 Scenario 2: Message lost In this scenario a first FullCAN Message is stored and read out by Software (1st Object write and read).
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 17.3.3 Scenario 3: Message gets overwritten indicated by Semaphore bits This scenario is a special case in which the lost message is indicated by the existing semaphore bits. The scenario is entered, if during a Software read of a message object another new message gets stored by the message handler. In this case, the FullCAN Interrupt bit gets set for a second time with the 2nd Object write.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 semaphore bits 01 11 00 01 11 00 IntPndx look-up table access write write write write ID, D1 D2 SEM SEM 1st Object write read clear SEM SEM write write write write ID, D1 D2 SEM SEM read read read D1 D2 SEM clear SEM read read read D1 D2 SEM 2nd Object write 2nd Object read 1st Object read Interrupt Service Routine MsgLostx message handler access ARM processor access Fig 88.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 semaphore bits 01 11 01 11 00 01 11 IntPndx look-up table access write write write write read ID, D1 D2 SEM SEM SEM 1st Object write write write write write ID, D1 D2 SEM SEM clear SEM 2nd Object write read read read D1 D2 SEM write write write write ID, D1 D2 SEM SEM 3rd Object write 1st Object read Interrupt Service Routine MsgLostx message handler access ARM processor access Fig 89.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 semaphore bits 01 11 01 11 11 00 IntPndx look-up table access write write write write ID, D1 D2 SEM SEM 1st Object write write write write write ID, D1 D2 SEM SEM read clear SEM SEM read read read D1 D2 SEM write write write write ID, D1 D2 SEM SEM 2nd Object write 3rd Object write 1st Object read MsgLostx message handler access ARM processor access Fig 90. Clearing message lost 18.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 In cases where explicit identifiers as well as groups of the identifiers are programmed, a CAN identifier search has to start in the explicit identifier section first. If no match is found, it continues the search in the group of identifier section.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 000 d := 000 h := 0 0000 0000 b look-up table RAM APB base + address column_lower 00d = 00h 0 1 04d = 04h 2 3 44d = 2Ch 22 23 48d = 30h 24 25 column_upper 2 6 52d = 34h ID index # 0 1 2 3 22 23 24 25 explicit SFF table SFF_sa 26 d 84d = 54h lower_boundary 3 4 upper_boundary 34 d 88d = 58h lower_boundary 3 5 upper_boundary 35 d 92d = 5Ch lower_boundary 3 6 upper_boundary 36 d 100d = 64h 38 38 d 104d = 6
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Table 457.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 Message disable bit Message disable bit Index SFF_sa = 0x00 SFF_GRP_sa = 0x10 EFF_sa = 0x20 EFF_GRP_sa = 0x30 Explicit Standard Frame ... Format Identifier Section Group of Standard Frame ...
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 FullCAN explicit standard frame format identfier section (11-bit CAN ID) The start address of the FullCAN Explicit Standard Frame Format Identifier section is (automatically) set to 0x00. The end of this section is defined in the SFF_sa register. In the FullCAN ID section only identifiers of FullCAN Object are stored for acceptance filtering.
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 FullCAN Interrupt Enable bit Message Disable bit FullCAN Explicit Standard Frame ... Format Identifier Section SFF_sa = 0x10 ENDofTable = SFF_GRP_sa = EFF_sa = EFF_GRP_sa = 0x20 Explicit Standard Frame ...
UM10237 NXP Semiconductors Chapter 18: LPC24XX CAN controllers CAN1/2 • Each section has to be organized as a sorted list or table with an increasing order of the Source CAN Channel (SCC) in conjunction with the CAN Identifier (there is no exception for disabled identifiers). • The upper and lower bound in a Group of Identifiers definition has to be from the same Source CAN Channel. • To disable a Group of Identifiers the message disable bit has to be set for both, the upper and lower bound.
UM10237 Chapter 19: LPC24XX SPI Rev. 02 — 19 December 2008 User manual 1. Basic configuration The SPI is configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bit PCSPI. Remark: On reset, the SPI is enabled (PCSPI = 1). 2. Clock: In PCLK_SEL0 select PCLK_SPI (see Table 4–56). In master mode, the clock must be scaled down (see Section 19–7.4). 3. Pins: Select SPI pins and their modes in PINSEL0 to PINSEL4 and PINMODE0 to PINMODE4 (see Section 9–5). 4.
UM10237 NXP Semiconductors Chapter 19: LPC24XX SPI SCK (CPOL = 0) SCK (CPOL = 1) SSEL CPHA = 0 Cycle # CPHA = 0 1 2 3 4 5 6 7 8 MOSI (CPHA = 0) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 MISO (CPHA = 0) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 CPHA = 1 Cycle # CPHA = 1 1 2 3 4 5 6 7 8 MOSI (CPHA = 1) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 MISO (CPHA = 1) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 Fig 94.
UM10237 NXP Semiconductors Chapter 19: LPC24XX SPI When a device is a slave and CPHA is set to 0, the transfer starts when the SSEL signal goes active, and ends when SSEL goes inactive. When a device is a slave, and CPHA is set to 1, the transfer starts on the first clock edge when the slave is selected, and ends on the last clock edge where data is sampled. 5. SPI peripheral details 5.1 General information There are four registers that control the SPI peripheral.
UM10237 NXP Semiconductors Chapter 19: LPC24XX SPI 5. Read the SPI status register. 6. Read the received data from the SPI data register (optional). 7. Go to step 3 if more data is required to transmit. Note: A read or write of the SPI data register is required in order to clear the SPIF status bit. Therefore, if the optional read of the SPI data register does not take place, a write to this register is required in order to clear the SPIF status bit. 5.
UM10237 NXP Semiconductors Chapter 19: LPC24XX SPI If the SSEL signal goes active, when the SPI block is a master, this indicates another master has selected the device to be a slave. This condition is known as a mode fault. When a mode fault is detected, the mode fault (MODF) bit in the status register will be activated, the SPI signal drivers will be de-activated, and the SPI mode will be changed to be a slave. If the Px.y/SSEL/...
UM10237 NXP Semiconductors Chapter 19: LPC24XX SPI 7. Register description The SPI contains 5 registers as shown in Table 19–461. All registers are byte, half word and word accessible. Table 461. SPI register map Name Description Access Reset Value[1] Address S0SPCR SPI Control Register. This register controls the operation of the SPI. R/W 0x00 0xE002 0000 S0SPSR SPI Status Register. This register shows the status of the SPI. RO 0x00 0xE002 0004 S0SPDR SPI Data Register.
UM10237 NXP Semiconductors Chapter 19: LPC24XX SPI Table 462: SPI Control Register (S0SPCR - address 0xE002 0000) bit description Bit Symbol 5 MSTR 6 Value Description Master mode select. 0 The SPI operates in Slave mode. 1 The SPI operates in Master mode. LSBF 7 0 SPI data is transferred MSB (bit 7) first. 1 SPI data is transferred LSB (bit 0) first. 0 SPI interrupts are inhibited. 1 A hardware interrupt is generated each time the SPIF or MODF bits are activated.
UM10237 NXP Semiconductors Chapter 19: LPC24XX SPI Table 463: SPI Status Register (S0SPSR - address 0xE002 0004) bit description Bit Symbol Description Reset Value 5 ROVR Read overrun. When 1, this bit indicates that a read overrun has 0 occurred. This bit is cleared by reading this register. 6 WCOL Write collision. When 1, this bit indicates that a write collision has 0 occurred. This bit is cleared by reading this register, then accessing the SPI data register.
UM10237 NXP Semiconductors Chapter 19: LPC24XX SPI Table 466: SPI Test Control Register (SPTCR - address 0xE002 0010) bit description Bit Symbol Description Reset Value 0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 7:1 Test SPI test mode. When 0, the SPI operates normally. When 1, 0 SCK will always be on, independent of master mode select, and data availability setting. 7.
UM10237 NXP Semiconductors Chapter 19: LPC24XX SPI MOSI_IN MOSI_OUT MISO_IN MISO_OUT SPI SHIFT REGISTER SPI CLOCK SCK_IN SCK_OUT SS_IN GENERATOR & DETECTOR SPI Interrupt APB Bus SPI REGISTER INTERFACE SPI STATE CONTROL OUTPUT ENABLE LOGIC SCK_OUT_EN MOSI_OUT_EN MISO_OUT_EN Fig 95. SPI block diagram UM10237_2 User manual © NXP B.V. 2008. All rights reserved. Rev.
UM10237 Chapter 20: LPC24XX SSP interface SSP0/1 Rev. 02 — 19 December 2008 User manual 1. Basic configuration The SSP0/1 interfaces are configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bit PCSSP0/1. Remark: On reset, both SSP interfaces are enabled (PCSSP0/1 = 1). 2. Clock: In PCLK_SEL0 select PCLK_SSP1; in PCLK_SEL1 select PCLK_SSP0 (see Section 4–3.3.4. In master mode, the clock must be scaled down (see Section 20–6.5). 3.
UM10237 NXP Semiconductors Chapter 20: LPC24XX SSP interface SSP0/1 4. Pin descriptions Table 469. SSP pin descriptions Pin Name Interface pin Type name/function Pin Description SPI SSI Microwire SCK0/1 I/O SSEL0/1 I/O SCK CLK SSEL FS SK Serial Clock. SCK/CLK/SK is a clock signal used to synchronize the transfer of data. It is driven by the master and received by the slave. When SPI interface is used the clock is programmable to be active high or active low, otherwise it is always active high.
UM10237 NXP Semiconductors Chapter 20: LPC24XX SSP interface SSP0/1 CLK FS DX/DR MSB LSB 4 to 16 bits a. Single frame transfer CLK FS DX/DR MSB LSB MSB 4 to 16 bits LSB 4 to 16 bits b. Continuous/back-to-back frames transfer Fig 96. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two Frames Transfer For device configured as a master in this mode, CLK and FS are forced LOW, and the transmit data line DX is tristated whenever the SSP is idle.
UM10237 NXP Semiconductors Chapter 20: LPC24XX SSP interface SSP0/1 The CPHA control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the CPHA phase control bit is LOW, data is captured on the first clock edge transition. If the CPHA clock phase control bit is HIGH, data is captured on the second clock edge transition. 5.2.
UM10237 NXP Semiconductors Chapter 20: LPC24XX SSP interface SSP0/1 In the case of a single word transmission, after all bits of the data word have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSEL signal must be pulsed HIGH between each data word transfer.
UM10237 NXP Semiconductors Chapter 20: LPC24XX SSP interface SSP0/1 SCK SSEL MOSI MISO MSB LSB MSB LSB Q 4 to 16 bits a. Single transfer with CPOL=1 and CPHA=0 SCK SSEL MOSI MISO MSB LSB MSB LSB MSB Q LSB MSB LSB Q 4 to 16 bits 4 to 16 bits b. Continuous transfer with CPOL=1 and CPHA=0 Fig 99. SPI frame format with CPOL = 1 and CPHA = 0 (a) Single and b) Continuous Transfer) In this configuration, during idle periods: • The CLK signal is forced HIGH. • SSEL is forced HIGH.
UM10237 NXP Semiconductors Chapter 20: LPC24XX SSP interface SSP0/1 5.2.5 SPI format with CPOL = 1,CPHA = 1 The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in Figure 20–100, which covers both single and continuous transfers. SCK SSEL MOSI MISO Q MSB LSB MSB LSB Q 4 to 16 bits Fig 100. SPI Frame Format with CPOL = 1 and CPHA = 1 In this configuration, during idle periods: • The CLK signal is forced HIGH. • SSEL is forced HIGH.
UM10237 NXP Semiconductors Chapter 20: LPC24XX SSP interface SSP0/1 SK CS SO SI MSB LSB 8 bit control 0 MSB LSB 4 to 16 bits output data Fig 101. Microwire frame format (single transfer) Microwire format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8 bit control word that is transmitted from the SSP to the off-chip slave device.
UM10237 NXP Semiconductors Chapter 20: LPC24XX SSP interface SSP0/1 SK CS SO LSB MSB LSB 8 bit control SI 0 MSB LSB MSB 4 to 16 bits output data LSB 4 to 16 bits output data Fig 102. Microwire frame format (continuos transfers) 5.3.1 Setup and hold time requirements on CS with respect to SK in Microwire mode In the Microwire mode, the SSP slave samples the first bit of receive data on the rising edge of SK after CS has gone LOW.
UM10237 NXP Semiconductors Chapter 20: LPC24XX SSP interface SSP0/1 Table 470. SSP Register Map Generic Name Description CR0 Control Register 0. Selects the serial clock rate, bus R/W type, and data size. 0 SSP0CR0 - 0xE006 8000 SSP1CR0 - 0xE003 0000 CR1 Control Register 1. Selects master/slave and other modes. R/W 0 SSP0CR1 - 0xE006 8004 SSP1CR1 - 0xE003 0004 DR Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.
UM10237 NXP Semiconductors Chapter 20: LPC24XX SSP interface SSP0/1 Table 471: SSPn Control Register 0 (SSP0CR0 - address 0xE006 8000, SSP1CR0 0xE003 0000) bit description Bit Symbol 3:0 DSS 5:4 6 7 15:8 Value Reset Value Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.
UM10237 NXP Semiconductors Chapter 20: LPC24XX SSP interface SSP0/1 Table 472: SSPn Control Register 1 (SSP0CR1 - address 0xE006 8004, SSP1CR1 0xE003 0004) bit description Bit Symbol 0 LBM 1 2 Value Description Reset Value Loop Back Mode. 0 0 During normal operation. 1 Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). SSE SSP Enable. 0 0 The SSP controller is disabled.
UM10237 NXP Semiconductors Chapter 20: LPC24XX SSP interface SSP0/1 6.4 SSPn Status Register (SSP0SR - 0xE006 800C, SSP1SR 0xE003 000C) This read-only register reflects the current status of the SSP controller. Table 474: SSPn Status Register (SSP0SR - address 0xE006 800C, SSP1SR - 0xE003 000C) bit description Bit Symbol Description Reset Value 0 TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. 1 1 TNF Transmit FIFO Not Full.
UM10237 NXP Semiconductors Chapter 20: LPC24XX SSP interface SSP0/1 Table 476: SSPn Interrupt Mask Set/Clear register (SSP0IMSC - address 0xE006 8014, SSP1IMSC - 0xE003 0014) bit description Bit Symbol Description Reset Value 0 RORIM Software should set this bit to enable interrupt when a Receive 0 Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
UM10237 NXP Semiconductors Chapter 20: LPC24XX SSP interface SSP0/1 Table 478: SSPn Masked Interrupt Status register (SSPnMIS -address 0xE006 801C, SSP1MIS - 0xE003 001C) bit description Bit Symbol Description 0 RORMIS This bit is 1 if another frame was completely received while the 0 RxFIFO was full, and this interrupt is enabled. Reset Value 1 RTMIS This bit is 1 if the Rx FIFO is not empty, has not been read for a "timeout period", and this interrupt is enabled.
UM10237 Chapter 21: LPC24XX SD/MMC card interface Rev. 02 — 19 December 2008 User manual 1. Basic configuration The SD/MMC is configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bit PC_MCI. Remark: On reset, the SD/MMC is disabled (PCMCI = 0). 2. Clock: In PCLK_SEL1 select PCLK_MCI (see Table 4–57). 3. Pins: Select SD/MMC pins and their modes in PINSEL0 to PINSEL4 and PINMODE0 to PINMODE4 (see Section 9–5). 4.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface There is one additional signal needed in the interface, a power control line MCIPWR, but it can be sourced from any GPIO signal. 5. Functional overview The MCI may be used as a multimedia card bus host (see Section 21–5.1 “Mutimedia card”) or a secure digital memory card bus host (see Section 21–5.2 “Secure digital memory card”).
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface CLK SECURE DIGITAL MEMORY CARD CONTROLLER CMD D[3:0] SECURE DIGITAL MEMORY CARD Fig 105. Secure digital memory card connection 5.2.1 Secure digital memory card bus signals The following signals are used on the secure digital memory card bus: • CLK Host to card clock signal • CMD Bidirectional command/response signal • DAT[3:0] Bidirectional data signals 5.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface 5.3.1 Adapter register block The adapter register block contains all system registers. This block also generates the signals that clear the static flags in the multimedia card. The clear signals are generated when 1 is written into the corresponding bit location of the MCIClear register. 5.3.2 Control unit The control unit contains the power management functions and the clock divider for the memory card clock.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface IDLE Response received or disabled or command CRC failed Enabled and Pending command Disabled RECEIVE Disabled or no response PEND Disabled or timeout Enabled and command start Response started LastData SEND WAIT Wait for response Fig 107. Command path state machine When the WAIT state is entered, the command timer starts running.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface 5.3.5 Command format The command path operates in a half-duplex mode, so that commands and responses can either be sent or received. If the CPSM is not in the SEND state, the MCICMD output is in HI-Z state, as shown in Figure 21–108. Data on MCICMD is synchronous to the rising MCICLK edge. All commands have a fixed length of 48 bits. Table 21–482 shows the command format. Table 482.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface Table 485. Command path status flags Flag Description CmdRespEnd Set if response CRC is OK. CmdCrcFail Set if response CRC fails. CmdSent Set when command (that does not require response) is sent. CmdTimeOut Response timeout. CmdActive Command transfer in progress. The CRC generator calculates the CRC checksum for all bits before the CRC code.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface Reset Disabled or FIFO underrun or end of data or CRC fail IDLE Disabled or CRC fail or timeout Disabled or Rx FIFO empty or timeout or start bit error Disabled or end of data Enable and send BUSY Enable and not send Disabled or CRC fail WAIT_R Not busy WAIT_S End of packet Start bit End of packet or end of data or FIFO overrun Data ready SEND RECEIVE Fig 109.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface Note: The DPSM remains in the WAIT_S state for at least two clock periods to meet Nwr timing constraints. • SEND: The DPSM starts sending data to a card. Depending on the transfer mode bit in the data control register, the data transfer mode can be either block or stream: – In block mode, when the data block counter reaches zero, the DPSM sends an internally generated CRC code and end bit, and moves to the BUSY state.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface MCICLK MCICMD 3 2 1 cmd state MCIDAT0 0 7 6 5 4 PEND Z Z data counter 3 2 1 CMD CMD CMD SEND Z Z Z S CMD 7 CMD 6 CmdPend Fig 110. Pending command start The data block counter determines the end of a data block. If the counter is zero, the end-of-data condition is TRUE (see Section 21–6.9 “Data Control Register (MCIDataCtrl 0xE008 C02C)” for more information). 5.3.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface 5.3.11 Status flags Table 21–487 lists the data path status flags (see Section 21–6.11 “Status Register (MCIStatus - 0xE008 C034)” on page 569 for more information). Table 487. Data path status flags Flag Description TxFifoFull Transmit FIFO is full. TxFifoEmpty Transmit FIFO is empty. TxFifoHalfEmpty Transmit FIFO is half full. TxDataAvlbl Transmit FIFO data available. TxUnderrun Transmit FIFO underrun error.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface • The receive FIFO refers to the receive logic and data buffer when RxActive is asserted (see Section 21–5.3.15 “Receive FIFO”). 5.3.14 Transmit FIFO Data can be written to the transmit FIFO through the APB interface once the MCI is enabled for transmission. The transmit FIFO is accessible via 16 sequential addresses (see Section 21–6.15 “Data FIFO Register (MCIFIFO - 0xE008 C080 to 0xE008 C0BC)”).
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface Table 489. Receive FIFO status flags Symbol Description RxFifoFull Set to HIGH when all 16 receive FIFO words contain valid data. RxFifoEmpty Set to HIGH when the receive FIFO does not contain valid data. RxHalfFull Set to HIGH when 8 or more receive FIFO words contain valid data. This flag can be used as a DMA request. RxDataAvlbl Set to HIGH when the receive FIFO is not empty. This flag is the inverse of the RxFifoEmpty flag.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface Table 490. Summary of MCI registers Name Description Access Width Reset Value[1] Address MCIMask0 Interrupt 0 mask register. R/W 0x000000 0xE008 C03C 0xE008 C048 22 MCIFifoCnt FIFO Counter. RO 15 0x0000 MCIFIFO Data FIFO Register. R/W 32 0x00000000 0xE008 C080 to 0xE008 C0BC [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. 6.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface Table 492: Clock Control register (MCIClock - address 0xE008 C004) bit description Bit Symbol 7:0 ClkDiv Value Description Reset Value 0x00 MCI bus clock period: MCLCLK frequency = MCLK / [2×(ClkDiv+1)]. 8 Enable 9 Enable MCI bus clock: 0 Clock disabled. 1 Clock enabled. PwrSave 10 Disable MCI clock output when bus is idle: 0 Always enabled. 1 Clock enabled when bus is active.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface Table 494: Command register (MCICommand - address 0xE008 C00C) bit description Bit Symbol Description Reset Value 5:0 CmdIndex Command index. 0 6 Response If set, CPSM waits for a response. 0 7 LongRsp If set, CPSM receives a 136 bit long response. 0 8 Interrupt If set, CPSM disables command timer and waits for interrupt request. 0 9 Pending If set, CPSM waits for CmdPend before it starts sending a command.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface Table 497: Response registers (MCIResponse0-3 - addresses 0xE008 0014, 0xE008 C018, 0xE008 001C and 0xE008 C020) bit description Bit Symbol 31:0 Status Description Reset Value Card status 0x0000 0000 The card status size can be 32 or 127 bits, depending on the response type (see Table 21–498).
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface 6.9 Data Control Register (MCIDataCtrl - 0xE008 C02C) The MCIDataCtrl register controls the DPSM. Table 21–501 shows the bit assignment of the MCIDataCtrl register. Table 501: Data Control register (MCIDataCtrl - address 0xE008 C02C) bit description Bit Symbol 0 Enable Data transfer enable. 0 1 Direction Data transfer direction: 0 2 Value Description 0 From controller to card. 1 From card to controller.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface Table 503: Data Counter register (MCIDataCnt - address 0xE008 C030) bit description Bit Symbol Description Reset Value 15:0 DataCount Remaining data 0x0000 31:16 - NA Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. Note: This register should be read only when the data transfer is complete. 6.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface Table 504: Status register (MCIStatus - address 0xE008 C034) bit description Bit Symbol Description Reset Value 20 TxDataAvlbl Data available in transmit FIFO. 0 21 RxDataAvlbl Data available in receive FIFO. 0 31:22 - Reserved, user software should not write ones to reserved NA bits. The value read from a reserved bit is not defined. 6.
UM10237 NXP Semiconductors Chapter 21: LPC24XX SD/MMC card interface Table 506: Interrupt Mask registers (MCIMask0 - address 0xE008 C03C) bit description Bit Symbol Description Reset Value 8 Mask8 Mask DataEnd flag. 0 9 Mask9 Mask StartBitErr flag. 0 10 Mask10 Mask DataBlockEnd flag. 0 11 Mask11 Mask CmdActive flag. 0 12 Mask12 Mask TxActive flag. 0 13 Mask13 Mask RxActive flag. 0 14 Mask14 Mask TxFifoHalfEmpty flag. 0 15 Mask15 Mask RxFifoHalfFull flag.
UM10237 Chapter 22: LPC24XX I2C interfaces I2C0/1/2 Rev. 02 — 19 December 2008 User manual 1. Basic configuration The I2C0/1/2 interfaces are configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bit PCI2C0/1/2. Remark: On reset, all I2C interfaces are enabled (PCI2C0/1/2 = 1). 2. Clock: In PCLK_SEL0 select PCLK_I2C0; in PCLK_SEL1 select PCLK_I2C1/2 (see Section 4–3.3.4. 3.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 • Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. Next follows the data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a “not acknowledge” is returned.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 5. Pin description Table 509. I2C Pin Description Pin Type Description SDA0,1, 2 Input/Output I2C Serial Data SCL0,1, 2 Input/Output I2C Serial Clock 6. I2C operating modes In a given application, the I2C block may operate as a master, a slave, or both. In the slave mode, the I2C hardware looks for its own slave address and the general call address. If one of these addresses is detected, an interrupt is requested.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 S SLAVE ADDRESS RW A DATA “0” - write “1” - read A A/A DATA P data transferred (n Bytes + Acknowledge) A = Acknowledge (SDA low) from Master to Slave A = Not acknowledge (SDA high) from Slave to Master S = START condition P = STOP condition Fig 112. Format in the Master Transmitter mode 6.2 Master Receiver mode In the master receiver mode, data is received from a slave transmitter.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 S SLA R A DATA A DATA A RS SLA W A DATA A P data transferred (n Bytes + Acknowledge) A = Acknowledge (SDA low) From master to slave A = Not acknowledge (SDA high) From slave to master S = START condition P = STOP condition SLA = Slave Address Fig 114. A master receiver switch to master Transmitter after sending repeated START 6.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 6.4 Slave Transmitter mode The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit will be 1, indicating a read operation. Serial data is transmitted via SDA while the serial clock is input through SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. In a given application, I2C may operate as a master and as a slave.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 8 I2ADR ADDRESS REGISTER COMPARATOR INPUT FILTER SDA OUTPUT STAGE SHIFT REGISTER ACK I2DAT BIT COUNTER/ ARBITRATION & SYNC LOGIC INPUT FILTER PCLK APB BUS 8 TIMING & CONTROL LOGIC SCL OUTPUT STAGE interrupt SERIAL CLOCK GENERATOR I2CONSET I2CONCLR I2SCLH I2SCLL CONTROL REGISTER & SCL DUTY CYCLE REGISTERS 16 status bus STATUS DECODER STATUS REGISTER I2STAT 8 Fig 117.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 7.2 Address Register I2ADDR This register may be loaded with the 7 bit slave address (7 most significant bits) to which the I2C block will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable general call address (0x00) recognition. 7.3 Comparator The comparator compares the received 7 bit slave address with its own slave address (7 most significant bits in I2ADR).
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device. If two or more master devices generate clock pulses, the “mark” duration is determined by the device that generates the shortest “marks,” and the “space” duration is determined by the device that generates the longest “spaces”. Figure 22–119 shows the synchronization procedure.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 The contents of the I2C control register may be read as I2CONSET. Writing to I2CONSET will set bits in the I2C control register that correspond to ones in the value written. Conversely, writing to I2CONCLR will clear bits in the I2C control register that correspond to ones in the value written. 7.9 Status decoder and status register The status decoder takes all of the internal status bits and compresses them into a 5 bit code.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 Table 512. Summary of I2C registers Generic Name Description Access Reset I2Cn Register value[1] Name & Address I2SCLH SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. R/W 0x04 I2C0SCLH - 0xE001 C010 I2C1SCLH - 0xE005 C010 I2C2SCLH - 0xE008 0010 I2SCLL R/W SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 When STA is 1 and the I2C interface is not already in master mode, it enters master mode, checks the bus and generates a START condition if the bus is free. If the bus is not free, it waits for a STOP condition (which will free the bus) and generates a START condition after a delay of a half clock period of the internal clock generator.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 8.2 I2C Control Clear Register (I2C[0/1/2]CONCLR: 0xE001 C018, 0xE005 C018, 0xE008 0018) The I2CONCLR registers control clearing of bits in the I2CON register that controls operation of the I2C interface. Writing a one to a bit of this register causes the corresponding bit in the I2C control register to be cleared. Writing a zero has no effect. Table 514.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 8.4 I2C Data Register (I2C[0/1/2]DAT - 0xE001 C008, 0xE005 C008, 0xE008 0008) This register contains the data to be transmitted or the data just received. The CPU can read and write to this register only while it is not in the process of shifting a byte, when the SI bit is set. Data in I2DAT remains stable as long as the SI bit is set.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 (12) f PCLK I 2 C bitfrequency = -------------------------------------------------------I2CSCLH + I2CSCLL The values for I2SCLL and I2SCLH should not necessarily be the same. Software can set different duty cycles on SCL by setting these two registers. For example, the I2C bus specification defines the SCL low time and high time at different values for a 400 kHz I2C rate.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 Table 521. Abbreviations used to describe an I2C operation Abbreviation Explanation A Not acknowledge bit (high level at SDA) Data 8 bit data byte P Stop condition In Figures 120 to 124, circles are used to indicate when the serial interrupt flag is set. The numbers in the circles show the status code held in the I2STAT register. At these points, a service routine must be executed to continue or complete the serial transfer.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 9.2 Master Receiver mode In the master receiver mode, a number of data bytes are received from a slave transmitter (see Figure 22–121). The transfer is initialized as in the master transmitter mode. When the start condition has been transmitted, the interrupt service routine must load I2DAT with the 7 bit slave address and the data direction bit (SLA+R). The SI bit in I2CON must then be cleared before the serial transfer can continue.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 If the AA bit is reset during a transfer, the I2C block will return a not acknowledge (logic 1) to SDA after the next received data byte. While AA is reset, the I2C block does not respond to its own slave address or a general call address. However, the I2C bus is still monitored and address recognition may be resumed at any time by setting AA.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 MT successful transmission to a Slave Receiver S SLA W A DATA A 18H 08H P 28H next transfer started with a Repeated Start condition S SLA W 10H Not Acknowledge received after the Slave address A P R 20H Not Acknowledge received after a Data byte A P to Master receive mode, entry = MR 30H arbitration lost in Slave address or Data byte A OR A other Master continues A OR A 38H arbitration lost and addressed
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 MR successful transmission to a Slave transmitter S 08H SLA R A DATA 40H A DATA 50H A P 58H next transfer started with a Repeated Start condition S SLA R 10H Not Acknowledge received after the Slave address A P W 48H to Master transmit mode, entry = MT arbitration lost in Slave address or Acknowledge bit other Master continues A OR A A 38H arbitration lost and addressed as Slave A other Master continues
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 reception of the own Slave address and one or more Data bytes all are acknowledged S SLA R A DATA 60H A DATA 80H last data byte received is Not acknowledged A P OR S 80H A0H A P OR S 88H arbitration lost as Master and addressed as Slave A 68H reception of the General Call address and one or more Data bytes GENERAL CALL A DATA 70h A DATA 90h last data byte is Not acknowledged A P OR S 90h A0H A P OR S
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 reception of the own Slave address and one or more Data bytes all are acknowledged S SLA R A DATA A8H arbitration lost as Master and addressed as Slave A B8H DATA A P OR S C0H A B0H last data byte transmitted.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 Table 525. Master Transmitter mode Status Status of the I2C bus Application software response Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI AA 0x08 A START condition Load SLA+W has been transmitted. Clear STA X 0 0 X SLA+W will be transmitted; ACK bit will be received. 0x10 A repeated START condition has been transmitted. Load SLA+W or X 0 0 X As above.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 Table 526. Master Receiver mode Status Status of the I2C bus Application software response Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI AA 0x08 A START condition Load SLA+R has been transmitted. X 0 0 X 0x10 A repeated START condition has been transmitted. Load SLA+R or X 0 0 X As above. Load SLA+W X 0 0 X SLA+W will be transmitted; the I2C block will be switched to MST/TRX mode.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 Table 527. Slave Receiver Mode Status Status of the I2C bus Application software response Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI AA 0x60 0x68 0x70 0x78 0x80 0x88 0x90 Next action taken by I2C hardware Own SLA+W has been received; ACK has been returned. No I2DAT action or X 0 0 0 Data byte will be received and NOT ACK will be returned.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 Table 527. Slave Receiver Mode Status Status of the I2C bus Application software response Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI AA 0x98 0xA0 Previously addressed with General Call; DATA byte has been received; NOT ACK has been returned. A STOP condition or repeated START condition has been received while still addressed as SLV/REC or SLV/TRX.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 Table 528. Tad_105: Slave Transmitter mode Status Status of the I2C bus Application software response Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI AA 0xA8 0xB0 0xB8 0xC0 0xC8 Own SLA+R has been Load data byte or received; ACK has been returned. Load data byte Next action taken by I2C hardware X 0 0 0 Last data byte will be transmitted and ACK bit will be received.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 9.5 Miscellaneous states There are two I2STAT codes that do not correspond to a defined I2C hardware state (see Table 22–529). These are discussed below. 22.9.5.1 I2STAT = 0xF8 This status code indicates that no relevant information is available because the serial interrupt flag, SI, is not yet set. This occurs between other states and when the I2C block is not involved in a serial transfer. 22.9.5.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 Table 529. Miscellaneous states Status Status of the I2C bus Application software response Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI 0xF8 No relevant state information available; SI = 0. No I2DAT action 0x00 Bus error during MST No I2DAT action or selected slave modes, due to an illegal START or STOP condition. State 0x00 can also occur when interference causes the I2C block to enter an undefined state.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 If an uncontrolled source generates a superfluous START or masks a STOP condition, then the I2C bus stays busy indefinitely. If the STA flag is set and bus access is not obtained within a reasonable amount of time, then a forced access to the I2C bus is possible. This is achieved by setting the STO flag while the STA flag is still set. No STOP condition is transmitted.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 time limit STA flag STO flag SDA line SCL line start condition Fig 125. Forced access to a busy I2C bus STA flag (2) (1) SDA line (3) (1) SCL line start condition (1) Unsuccessful attempt to send a start condition. (2) SDA line is released. (3) Successful attempt to send a start condition. State 08H is entered. Fig 126. Recovering from a bus obstruction caused by a low level on SDA 9.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 The I2C hardware now begins checking the I2C bus for its own slave address and general call. If the general call or the own slave address is detected, an interrupt is requested and I2STAT is loaded with the appropriate state information. 9.12.2 I2C interrupt service When the I2C interrupt is entered, I2STAT contains a status code which identifies one of the 26 state services to be executed. 9.12.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 2. Set up the Slave Address to which data will be transmitted, and add the Read bit. 3. Write 0x20 to I2CONSET to set the STA bit. 4. Set up the Master Receive buffer. 5. Initialize the Master data counter to match the length of the message to be received. 6. Exit 10.4 I2C interrupt routine Determine the I2C state and which state routine will be used to handle it. 1. Read the I2C status from I2STA. 2.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 4. Set up Master Transmit mode data buffer. 5. Set up Master Receive mode data buffer. 6. Initialize Master data counter. 7. Exit 10.7 Master Transmitter states 10.7.1 State : 0x18 Previous state was State 8 or State 10, Slave Address + Write has been transmitted, ACK has been received. The first data byte will be transmitted, an ACK bit will be received. 1. Load I2DAT with first data byte from Master Transmit buffer. 2.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 10.7.5 State : 0x38 Arbitration has been lost during Slave Address + Write or data. The bus has been released and not addressed Slave mode is entered. A new Start condition will be transmitted when the bus is free again. 1. Write 0x24 to I2CONSET to set the STA and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit 10.8 Master Receive states 10.8.1 State : 0x40 Previous state was State 08 or State 10.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 1. Read data byte from I2DAT into Master Receive buffer. 2. Write 0x14 to I2CONSET to set the STO and AA bits. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Exit 10.9 Slave Receiver states 10.9.1 State : 0x60 Own Slave Address + Write has been received, ACK has been returned. Data will be received and ACK returned. 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 3. Set up Slave Receive mode data buffer. 4. Initialize Slave data counter. 5. Exit 10.9.5 State : 0x80 Previously addressed with own Slave Address. Data has been received and ACK has been returned. Additional data will be read. 1. Read data byte from I2DAT into the Slave Receive buffer. 2. Decrement the Slave data counter, skip to step 5 if not the last data byte. 3. Write 0x0C to I2CONCLR to clear the SI flag and the AA bit. 4.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit 10.10 Slave Transmitter States 10.10.1 State : 0xA8 Own Slave Address + Read has been received, ACK has been returned. Data will be transmitted, ACK bit will be received. 1. Load I2DAT from Slave Transmit buffer with first data byte. 2. Write 0x04 to I2CONSET to set the AA bit. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4.
UM10237 NXP Semiconductors Chapter 22: LPC24XX I2C interfaces I2C0/1/2 3. Exit 10.10.5 State : 0xC8 The last data byte has been transmitted, ACK has been received. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit UM10237_2 User manual © NXP B.V. 2008. All rights reserved. Rev.
UM10237 Chapter 23: LPC24XX I2S interface Rev. 02 — 19 December 2008 User manual 1. Basic configuration The I2S interface is configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bit PCI2S. Remark: On reset, the I2S interface is disabled (PCI2S = 0). 2. Clock: In PCLK_SEL1 select PCLK_I2S, see Table 4–57. 3. Pins: Select I2S pins and their modes in PINSEL0 to PINSEL4 and PINMODE0 to PINMODE4 (see Section 9–5). 4.
UM10237 NXP Semiconductors Chapter 23: LPC24XX I2S interface next falling edge of the transmitting clock after a WS change. In stereo mode when WS is low left data is transmitted and right data when WS is high. In mono mode the same data is transmitted twice, once when WS is low and again when WS is high. • In master mode (ws_sel = 0), word select is generated internally with a 9 bit counter. The half period count value of this counter can be set in the control register.
UM10237 NXP Semiconductors Chapter 23: LPC24XX I2S interface SCK: serial clock TRANSMITTER (MASTER) SCK: serial clock RECEIVER (SLAVE) WS: word select SD: serial data TRANSMITTER (SLAVE) WS: word select SD: serial data RECEIVER (MASTER) CONTROLLER (MASTER) SCK TRANSMITTER (SLAVE) WS SD RECEIVER (SLAVE) SCK WS SD MSB word n-1 right channel LSB word n left channel MSB word n+1 right channel Fig 127. Simple I2S configurations and bus timing 5.
UM10237 NXP Semiconductors Chapter 23: LPC24XX I2S interface Table 531. Summary of I2S registers Name Description I2SIRQ Interrupt Request Control Register. Contains bits R/W that control how the I2S interrupt request is generated. 0xE008 801C I2STXRATE Transmit bit rate divider. This register R/W determines the I2S transmit bit rate by specifying the value to divide pclk by in order to produce the transmit bit clock. 0xE008 8020 I2SRXRATE Receive bit rate divider.
UM10237 NXP Semiconductors Chapter 23: LPC24XX I2S interface Table 533: Digital Audio Input register (I2SDAI - address 0xE008 8004) bit description Bit Symbol 1:0 wordwidth Value Description Reset Value Selects the number of bytes in data as follows: 00 8 bit data 01 16 bit data 10 Reserved, do not use this setting 11 32 bit data 01 2 mono When one, data is of monaural format. When zero, the data is in stereo format.
UM10237 NXP Semiconductors Chapter 23: LPC24XX I2S interface Table 536: Status Feedback register (I2SSTATE - address 0xE008 8010) bit description Bit Symbol Description Reset Value 15:8 rx_level Reflects the current level of the Receive FIFO. 0 23:16 tx_level Reflects the current level of the Transmit FIFO. 0 31:24 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 5.
UM10237 NXP Semiconductors Chapter 23: LPC24XX I2S interface Table 539: Interrupt Request Control register (I2SIRQ - address 0xE008 801C) bit description Bit Symbol Description Reset Value 0 rx_Irq_enable When 1, enables I2S receive interrupt. 0 1 tx_Irq_enable When 1, enables I2S transmit interrupt. 0 7:2 Unused Unused. 0 15:8 rx_depth_Irq Set the FIFO level on which to create an irq request. 0 23:16 tx_depth_Irq Set the FIFO level on which to create an irq request.
UM10237 NXP Semiconductors Chapter 23: LPC24XX I2S interface • Data word length is determined by the wordwidth value in the configuration register. There is a separate wordwidth value for the receive channel and the transmit channel. – 0: word is considered to contain four 8 bits data words. – 1: word is considered to contain two 16 bits data words. – 3: word is considered to contain one 32 bits data word.
UM10237 NXP Semiconductors Chapter 23: LPC24XX I2S interface Table 542. Conditions for FIFO level comparison Level Comparison Condition dmareq_tx_1 tx_depth_dma1 >= tx_level dmareq_rx_1 rx_depth_dma1 <= rx_level dmareq_tx_2 tx_depth_dma2 >= tx_level dmareq_rx_2 rx_depth_dma2 <= rx_level irq_tx tx_depth_irq >= tx_level irq_rx rx_depth_irq <= rx_level System signaling occurs when a level detection is true and enabled. Table 543.
UM10237 NXP Semiconductors Chapter 23: LPC24XX I2S interface Mono 8-bit data mode 7 N+3 0 7 0 7 N+2 0 7 0 7 0 15 0 15 N+1 0 7 0 7 N 0 Stereo 8-bit data mode 7 LEFT + 1 RIGHT + 1 LEFT RIGHT 0 Mono 16-bit data mode 15 N+1 N 0 Stereo 16-bit data mode 15 LEFT RIGHT 0 Mono 32-bit data mode N 31 0 Stereo 32-bit data mode LEFT 31 RIGHT 31 0 0 N N+1 Fig 128. FIFO contents for various I2S modes UM10237_2 User manual © NXP B.V. 2008. All rights reserved. Rev.
UM10237 Chapter 24: LPC24XX Timer0/1/2/3 Rev. 02 — 19 December 2008 User manual 1. Basic configuration The Timer0/1/2/3 peripherals are configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bits PCTIM0/1/2/3. Remark: On reset, Timer0/1 are enabled (PCTIM0/1 = 1), and Timer2/3 are disabled (PCTIM2/3 = 0). 2. Peripheral clock: In the PCLK_SEL0 register (Table 4–56), select PCLK_TIMER0/1; in the PCLK_SEL1 register (Table 4–57), select PCLK_TIMER2/3. 3.
UM10237 NXP Semiconductors Chapter 24: LPC24XX Timer0/1/2/3 • Free running timer. 4. Description The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally-supplied clock, and can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 5.
UM10237 NXP Semiconductors Chapter 24: LPC24XX Timer0/1/2/3 Table 546. Summary of timer/counter registers Generic Description Name Access Reset TIMERn Register/ Value[1] Name & Address IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. R/W 0 T0IR - 0xE000 4000 T1IR - 0xE000 8000 T2IR - 0xE007 0000 T3IR - 0xE007 4000 TCR Timer Control Register.
UM10237 NXP Semiconductors Chapter 24: LPC24XX Timer0/1/2/3 Table 546. Summary of timer/counter registers …continued Generic Description Name Access Reset TIMERn Register/ Value[1] Name & Address CR0 Capture Register 0. CR0 is loaded with the RO value of TC when there is an event on the CAPn[0] (CAP0[0], CAP1[0], CAP2[0], CAP3[0]) inputs. 0 T0CR0 - 0xE000 402C T1CR0 - 0xE000 802C T2CR0 - 0xE007 002C T3CR0 - 0xE007 402C CR1 Capture Register 1.
UM10237 NXP Semiconductors Chapter 24: LPC24XX Timer0/1/2/3 Table 548: Timer Control Register (TCR, TIMERn: TnTCR - addresses 0xE000 4004, 0xE000 8004, 0xE007 0004, 0xE007 4004) bit description Bit Symbol 0 Counter Enable When one, the Timer Counter and Prescale Counter are 0 enabled for counting. When zero, the counters are disabled. Description Reset Value 1 Counter Reset When one, the Timer Counter and the Prescale Counter 0 are synchronously reset on the next positive edge of PCLK.
UM10237 NXP Semiconductors Chapter 24: LPC24XX Timer0/1/2/3 Table 549: Count Control Register (T[0/1/2/3]CTCR - addresses 0xE000 4070, 0xE000 8070, 0xE007 0070, 0xE007 4070) bit description Bit Symbol 3:2 Count Input Select Value 00 01 Description Reset Value When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking: 00 CAPn.0 for TIMERn CAPn.
UM10237 NXP Semiconductors Chapter 24: LPC24XX Timer0/1/2/3 6.8 Match Control Register (T[0/1/2/3]MCR - 0xE000 4014, 0xE000 8014, 0xE007 0014, 0xE007 4014) The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter. The function of each of the bits is shown in Table 24–550.
UM10237 NXP Semiconductors Chapter 24: LPC24XX Timer0/1/2/3 6.9 Capture Registers (CR0 - CR3) Each Capture register is associated with a device pin and may be loaded with the Timer Counter value when a specified event occurs on that pin. The settings in the Capture Control Register register determine whether the capture function is enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both edges. 6.
UM10237 NXP Semiconductors Chapter 24: LPC24XX Timer0/1/2/3 6.11 External Match Register (T[0/1/2/3]EMR - 0xE000 403C, 0xE000 803C, 0xE007 003C, 0xE007 403C) The External Match Register provides both control and status of the external match pins. In the descriptions below, “n” represents the Timer number, 0,1, 2, or 3, and “m” represent a Match number, 0 through 3.
UM10237 NXP Semiconductors Chapter 24: LPC24XX Timer0/1/2/3 7. Example timer operation Figure 24–129 shows a timer configured to reset the count and generate an interrupt on match. The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle where the match occurs, the timer count is reset. This gives a full length cycle to the match value. The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value.
UM10237 NXP Semiconductors Chapter 24: LPC24XX Timer0/1/2/3 MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER INTERRUPT REGISTER CONTROL = MAT[3:0] INTERRUPT = CAP[3:0] = STOP ON MATCH RESET ON MATCH LOAD[3:0] = CAPTURE CONTROL REGISTER CSN CAPTURE REGISTER 0 TIMER COUNTER CAPTURE REGISTER 1 CE CAPTURE REGISTER 2 CAPTURE REGISTER 3 TCI PCLK PRESCALE COUNTER reset enable TIMER CONTROL REGISTER MAXVAL PRESCALE REGISTER Fig 1
UM10237 Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 Rev. 02 — 19 December 2008 User manual 1. Basic configuration The PWM is configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bit PCPWM0/1. Remark: On reset, the both PWMs are enabled (PCPWM0/1 = 1). 2. Peripheral clock: In the PCLK_SEL0 register (Table 4–56), select PCLK_PWM0/1. 3. Pins: Select PWM pins and pin modes in registers PINSELn and PINMODEn (see Section 9–5). 4.
UM10237 NXP Semiconductors Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 3. Description The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the microcontroller. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers.
UM10237 NXP Semiconductors Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 MATCH REGISTER 0 SHADOW REGISTER 0 LOAD ENABLE MATCH REGISTER 1 SHADOW REGISTER 1 LOAD ENABLE MATCH REGISTER 2 SHADOW REGISTER 2 LOAD ENABLE MATCH REGISTER 3 SHADOW REGISTER 3 LOAD ENABLE MATCH REGISTER 4 SHADOW REGISTER 4 LOAD ENABLE MATCH REGISTER 5 SHADOW REGISTER 5 LOAD ENABLE MATCH REGISTER 6 Match 0 SHADOW REGISTER 6 LOAD ENABLE PWM1 S Q R EN Match 1 PWMENA1 PWMSEL2 PWM2 MUX S Q R EN Match0 PWME
UM10237 NXP Semiconductors Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 3.1 Rules for single edge controlled PWM outputs 1. All single edge controlled PWM outputs go high at the beginning of a PWM cycle unless their match value is equal to 0. 2. Each PWM output will go low when its match value is reached. If no match occurs (i.e. the match value is greater than the PWM rate), the PWM output remains continuously high. 3.
UM10237 NXP Semiconductors Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 5. The maximum number of match registers is increased to 7 in order to allow support for up to 3 double edge PWM channels. This includes the necessary match outputs, control bits, etc. for each match register: – Three new Match registers are added, creating Match channels 4 through 6. – Three additional sets of stop (S), reset (R), and interrupt (I) bits are added to the MCR register (3 per additional match register). 6.
UM10237 NXP Semiconductors Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 Table 554.
UM10237 NXP Semiconductors Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 Table 557. PWM0 and PWM1 register map Generic Description Name Access Reset PWM0 Address PWM1 Address Value[1] & Name & Name IR Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. R/W 0 0xE001 4000 PWM0IR 0xE001 8000 PWM1IR TCR Timer Control Register. The TCR is used to control the Timer Counter functions.
UM10237 NXP Semiconductors Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 Table 557. PWM0 and PWM1 register map Generic Description Name Access Reset PWM0 Address PWM1 Address Value[1] & Name & Name MR4 Match Register 4. MR4 can be enabled in the MCR to R/W reset the TC, stop both the TC and PC, and/or generate an interrupt when it matches the TC. In addition, a match between this value and the TC clears PWM4 in either edge mode, and sets PWM5 if it’s in double-edge mode.
UM10237 NXP Semiconductors Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 Table 558: PWM Interrupt Register (PWM0IR - address 0xE001 4000 and PWM1IR address 0xE001 8000) bit description Bit Symbol 9 PWMMR5 Interrupt Interrupt flag for PWM match channel 5. 0 10 PWMMR6 Interrupt Interrupt flag for PWM match channel 6. 0 15:11 - Description Reset Value Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 6.
UM10237 NXP Semiconductors Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 6.3 PWM Count Control Register (PWM0CTCR - 0xE001 4070 and PWM1CTCR 0xE001 8070) The Count Control Register (CTCR) is used to select between Timer and Counter mode, and in Counter mode to select the pin and edge(s) for counting. The function of each of the bits is shown in Table 25–560.
UM10237 NXP Semiconductors Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 Table 561: Match Control Register (PWM0MCR - address 0xE000 4014 and PWM1MCR address 0xE000 8014) bit description Bit Symbol Value Description Reset Value 3 PWMMR1I 1 Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC. 0 0 This interrupt is disabled. 4 PWMMR1R 1 0 5 PWMMR1S 1 1 Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC.
UM10237 NXP Semiconductors Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 Table 561: Match Control Register (PWM0MCR - address 0xE000 4014 and PWM1MCR address 0xE000 8014) bit description Bit Symbol Value Description 16 PWMMR5R 1 Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it. 0 17 18 Stop on PWMMR5: the PWMTC and PWMPC will be stopped 0 and PWMTCR[0] will be set to 0 if PWMMR5 matches the PWMTC.
UM10237 NXP Semiconductors Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 Table 562: PWM Capture Control Register (PWM0CCR - address 0xE001 4028 and PWM1CCR address 0xE001 8028) bit description Bit Symbol Value Description Reset Value 3 Capture on PCAPn.1 rising edge[1] 0 This feature is disabled. 0 1 A synchronously sampled rising edge on the PCAPn.1 input will cause CR1 to be loaded with the contents of the TC. 4 5 Capture on 0 PCAPn.1 1 falling edge[1] Interrupt on PCAPn.
UM10237 NXP Semiconductors Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 6.7 PWM Latch Enable Register (PWM0LER - 0xE001 4050 and PWM1LER 0xE001 8050) The PWM Latch Enable registers are used to control the update of the PWM Match registers when they are used for PWM generation. When software writes to the location of a PWM Match register while the Timer is in PWM mode, the value is actually held in a shadow register and not used immediately.
UM10237 NXP Semiconductors Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1 Table 564: PWM Latch Enable Register (PWM0LER - address 0xE001 4050 and PWM1LER address 0xE001 8050) bit description Bit Symbol Description Reset Value 5 Enable PWM Match 5 Latch PWM MR5 register update control. See bit 0 for details. 0 6 Enable PWM Match 6 Latch PWM MR6 register update control. See bit 0 for details. 0 7 - Reserved, user software should not write ones to reserved bits.
UM10237 Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM Rev. 02 — 19 December 2008 User manual 1. Basic configuration The RTC is configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bits PCRTC. Remark: On reset, the RTC is enabled. See Section 26–9 for power saving options. 2. Clock: Select clock source in Table 26–570. If the peripheral clock is selected, select PCLK_RTC in the PCLK_SEL0 register (Table 4–56).
UM10237 NXP Semiconductors Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM and resume operation. The alarm output has a nominal voltage swing of 1.8 V. Note that the PLL is disabled when waking up from power down. See Section 4–3.2.10 for the PLL start-up procedure. 4.
UM10237 NXP Semiconductors Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM 6. Register description The RTC includes a number of registers. The address space is split into four sections by functionality. The first eight addresses are the Miscellaneous Register Group (Section 26–6.2). The second set of eight locations are the Time Counter Group (Section 26–6.4). The third set of eight locations contain the Alarm Register Group (Section 26–7).
UM10237 NXP Semiconductors Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM [1] Registers in the RTC other than those that are part of the Prescaler are not affected by chip Reset. These registers must be initialized by software if the RTC is enabled. Reset Value reflects the data stored in used bits only. It does not include reserved bits content. 6.
UM10237 NXP Semiconductors Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM Table 568. Interrupt Location Register (ILR - address 0xE002 4000) bit description Bit Symbol Description Reset value 0 RTCCIF When one, the Counter Increment Interrupt block generated an interrupt. NC Writing a one to this bit location clears the counter increment interrupt. 1 RTCALF When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt.
UM10237 NXP Semiconductors Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM Table 570. Clock Control Register (CCR - address 0xE002 4008) bit description Bit Symbol Description Reset value 3:2 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 4 CLKSRC If this bit is 0, the Clock Tick Counter takes its clock from the Prescaler, NA as on earlier devices in the NXP Embedded ARM family.
UM10237 NXP Semiconductors Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM Table 572. Counter Increment Select Mask register (CISS - address 0xE002 4040) bit description Bit Symbol Value Description 2:0 SubSecSel Reset value SubSecSelSub-Second Select. This field selects a count for the sub-second interrupt as NC follows: 000 An interrupt is generated on every 16 counts of the Clock Tick Counter. At 32.768 kHz, this generates an interrupt approximately every 488 microseconds.
UM10237 NXP Semiconductors Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM 6.3 Consolidated time registers The values of the Time Counters can optionally be read in a consolidated format which allows the programmer to read all time counters with only three read operations. The various registers are packed into 32 bit values as shown in Table 26–574, Table 26–575, and Table 26–576. The least significant bit of each register is read back at bit 0, 8, 16, or 24.
UM10237 NXP Semiconductors Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM Table 576. Consolidated Time register 2 (CTIME2 - address 0xE002 401C) bit description Bit Symbol Description Reset value 11:0 Day of Year Day of year value in the range of 1 to 365 (366 for leap years). NA 31:12 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 6.
UM10237 NXP Semiconductors Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM 7. Alarm register group The alarm registers are shown in Table 26–579. The values in these registers are compared with the time counters. If all the unmasked (See Section 26–6.2.6 “Alarm Mask Register (AMR - 0xE002 4010)” on page 653) alarm registers match their corresponding time counters then an interrupt is generated.
UM10237 NXP Semiconductors Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM during system operation (by reconfiguring the PLL, the APB divider, or the RTC prescaler) will result in some form of accumulated time error. Accumulated time errors may occur in case RTC clock source is switched between the PCLK to the RTCX pins, too. Once the 32 kHz signal from RTCX1-2 pins is selected as a clock source, the RTC can operate completely without the presence of the APB clock (PCLK).
UM10237 NXP Semiconductors Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM PREINT = int (PCLK/32768) - 1. The value of PREINT must be greater than or equal to 1. Table 581: Prescaler Integer register (PREINT - address 0xE002 4080) bit description Bit Symbol Description Reset Value 12:0 Prescaler Integer Contains the integer portion of the RTC prescaler value. 0 15:13 - NA Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
UM10237 NXP Semiconductors Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM PCLK (APB clock) to clock tick counter CLK CLK UNDERFLOW 15 BIT FRACTION COUNTER 13 BIT INTEGER COUNTER (DOWN COUNTER) RELOAD 15 13 COMBINATORIAL LOGIC extend reload 15 13 BIT RELOAD INTEGER REGISTER (PREINT) 15 BIT FRACTION REGISTER (PREFRAC) 13 15 APB bus Fig 135. RTC prescaler block diagram 10.
UM10237 NXP Semiconductors Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM Table 583.
UM10237 NXP Semiconductors Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM LPC24xx RTCX1 CX1 RTCX2 32 kHz Xtal CX2 Fig 136. RTC 32 kHz crystal oscillator circuit Table 26–584 gives the crystal parameters that should be used. CL is the typical load capacitance of the crystal and is usually specified by the crystal manufacturer. The actual CL influences oscillation frequency.
UM10237 Chapter 27: LPC24XX WatchDog Timer (WDT) Rev. 02 — 19 December 2008 User manual 1. Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be disabled. • • • • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate Watchdog reset. Programmable 32 bit timer with internal pre-scaler.
UM10237 NXP Semiconductors Chapter 27: LPC24XX WatchDog Timer (WDT) When the Watchdog counter underflows, the program counter will start from 0x0000 0000 as in the case of external reset. The Watchdog time-out flag (WDTOF) can be examined to determine if the Watchdog has caused the reset condition. The WDTOF flag must be cleared by software. The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB accesses to the watchdog registers.
UM10237 NXP Semiconductors Chapter 27: LPC24XX WatchDog Timer (WDT) Table 586. Watchdog operating modes selection WDEN WDRESET Mode of Operation 0 X (0 or 1) Debug/Operate without the Watchdog running. 1 0 Watchdog interrupt mode: debug with the Watchdog interrupt but no WDRESET enabled. When this mode is selected, a watchdog counter underflow will set the WDINT flag and the Watchdog interrupt request will be generated.
UM10237 NXP Semiconductors Chapter 27: LPC24XX WatchDog Timer (WDT) errors. After writing 0xAA to WDFEED, access to any Watchdog register other than writing 0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled. The reset will be generated during the second PCLK following an incorrect access to a Watchdog register during a feed sequence. Interrupts should be disabled during the feed sequence. An abort condition will occur if an interrupt happens during the feed sequence.
UM10237 NXP Semiconductors Chapter 27: LPC24XX WatchDog Timer (WDT) 5. Block diagram The block diagram of the Watchdog is shown below in the Figure 27–137. The synchronization logic (PCLK - WDCLK) is not shown in the block diagram. feed sequence WDTC feed ok WDFEED feed error RTC oscillator pclk internal RC oscillator wdclk ÷4 32 BIT DOWN COUNTER underflow enable count WDCLKSEL SHADOW BIT WMOD register WDINT WDTOF WDRESET WDEN reset interrupt Fig 137.
UM10237 Chapter 28: LPC24XX Analog-to Digital Converter (ADC) Rev. 02 — 19 December 2008 User manual 1. Basic configuration The ADC is configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bits PCADC. Remark: On reset, the ADC is disabled. To enable the ADC, first set the PCADC bit, and then enable the ADC in the AD0CR register (bit PDN) Table 28–594. To disable the ADC, first clear the PDN bit, and then clear the PCADC bit. 2.
UM10237 NXP Semiconductors Chapter 28: LPC24XX Analog-to Digital Converter (ADC) Table 592. ADC pin description Pin Type Description AD0[7:0] Input Analog Inputs. The A/D converter cell can measure the voltage on any of these input signals. Note that these analog inputs are always connected to their pins, even if the Pin Multiplexing Register assigns them to port pins. A simple self-test of the A/D Converter can be done by driving these pins as port outputs.
UM10237 NXP Semiconductors Chapter 28: LPC24XX Analog-to Digital Converter (ADC) Table 593. Summary of ADC registers Name Description Access Reset Value[1] Address AD0DR3 A/D Channel 3 Data Register. This register contains the result of the most recent conversion completed on channel 3. R/W NA 0xE003 401C AD0DR4 A/D Channel 4 Data Register. This register contains the result of the most recent conversion completed on channel 4. R/W NA 0xE003 4020 AD0DR5 A/D Channel 5 Data Register.
UM10237 NXP Semiconductors Chapter 28: LPC24XX Analog-to Digital Converter (ADC) Table 594: A/D Control Register (AD0CR - address 0xE003 4000) bit description Bit Symbol Value Description 19:17 CLKS This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).
UM10237 NXP Semiconductors Chapter 28: LPC24XX Analog-to Digital Converter (ADC) Table 595: A/D Global Data Register (AD0GDR - address 0xE003 4004) bit description Bit Symbol Description Reset Value 5:0 Unused These bits always read as zeroes. They provide compatible expansion room for future, higher-resolution A/D converters.
UM10237 NXP Semiconductors Chapter 28: LPC24XX Analog-to Digital Converter (ADC) 5.4 A/D Interrupt Enable Register (AD0INTEN - 0xE003 400C) This register allows control over which A/D channels generate an interrupt when a conversion is complete. For example, it may be desirable to use some A/D channels to monitor sensors by continuously performing conversions on them. The most recent results are read by the application program whenever they are needed.
UM10237 NXP Semiconductors Chapter 28: LPC24XX Analog-to Digital Converter (ADC) 6. Operation 6.1 Hardware-triggered conversion If the BURST bit in the ADCR is 0 and the START field contains 010-111, the A/D converter will start a conversion when a transition occurs on a selected pin or Timer Match signal. The choices include conversion on a specified edge of any of 4 Match signals, or conversion on a specified edge of either of 2 Capture/Match pins.
UM10237 Chapter 29: LPC24XX Digital-to Analog Converter (DAC) Rev. 02 — 19 December 2008 User manual 1. Basic configuration The DAC is configured using the following registers: 1. Power: The DAC is always on. 2. Clock: In the PCLK_SEL0 register (Table 4–56), select PCLK_DAC. 3. Pins: Select the DAC pin and pin mode in registers PINSEL1 and PINMODE1 (see Section 9–5). 2. Features • • • • • 10 bit digital to analog converter Resistor string architecture Buffered output Power down mode Selectable speed vs.
UM10237 NXP Semiconductors Chapter 29: LPC24XX Digital-to Analog Converter (DAC) Table 600: D/A Converter Register (DACR - address 0xE006 C000) bit description Bit Symbol Value Description Reset Value 5:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 15:6 VALUE 0 After the selected settling time after this field is written with a new VALUE, the voltage on the AOUT pin (with respect to VSSA) is VALUE/1024 × VREF.
UM10237 Chapter 30: LPC24XX Flash memory programming firmware Rev. 02 — 19 December 2008 User manual 1. How to read this chapter Remark: This chapter applies to parts LPC2458, LPC2468, and LPC2478. 2. Flash boot loader The Boot Loader controls initial operation after reset, and also provides the means to accomplish programming of the Flash memory.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware When ISP mode is entered after a power on reset, the IRC and PLL are used to generate CCLK of 14.748 MHz. This may not be the case when ISP is invoked by the user application (see Section 30–10.8 “Reinvoke ISP” on page 695). 5.1 Memory map after any reset The Flash portion of the boot block is 8 kB in size and resides in the top portion (starting from 0x0007 E000) of the on-chip Flash memory.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware If the signature is not valid, the auto-baud routine synchronizes with the host via serial port 0. The host should send a ’?’ (0x3F) as a synchronization character and wait for a response. The host side serial port settings should be 8 data bits, 1 stop bit and no parity.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware A description of UU-encode is available at the wotsit webpage. 5.2.4 ISP flow control A software XON/XOFF flow control scheme is used to prevent data loss due to buffer overrun. When the data arrives rapidly, the ASCII control character DC3 (stop) is sent to stop the flow of data. Data flow is resumed by sending the ASCII control character DC1 (start). The host should also support the same flow control scheme. 5.2.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware 6. Boot process flowchart RESET INITIALIZE CRP1/2/3 ENABLED? no ENABLE DEBUG yes WATCHDOG FLAG SET? yes A no yes USER CODE VALID? no CRP3 ENABLED? yes EXECUTE INTERNAL USER CODE Enter ISP MODE? (P2.10=LOW) USER CODE VALID? no yes no yes A RUN AUTO-BAUD no AUTO-BAUD SUCCESSFUL? yes RECEIVE CRYSTAL FREQUENCY 1 RUN ISP COMMAND HANDLER 2 (1) For details on handling the crystal frequency, see Section 30–10.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware 7. Sector numbers Some IAP and ISP commands operate on "sectors" and specify sector numbers. The following table indicate the correspondence between sector numbers and memory addresses for LPC2400 devices. IAP, ISP, and RealMonitor routines are located in the boot block. The boot block is present at addresses 0x0007 E000 to 0x0007 FFFF. ISP and IAP commands do not allow write/erase/go operation on the boot block.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware 8. Code Read Protection (CRP) Code Read Protection is a mechanism that allows user to enable different levels of security in the system so that access to the on-chip Flash and use of the ISP can be restricted. When needed, CRP is invoked by programming a specific pattern in Flash location at 0x000001FC. IAP commands are not affected by the code read protection. Starting with bootloader version 3.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware Table 603. Code Read Protection hardware/software interaction CRP option User Code Valid P2.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware Table 604. ISP command summary ISP Command Usage Described in Read Part ID J Table 30–616 Read Boot code version K Table 30–618 Compare Table 30–619 M 9.1 Unlock Table 605.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware 9.3 Echo Table 608. ISP Echo command Command A Input Setting: ON = 1 | OFF = 0 Return Code CMD_SUCCESS | PARAM_ERROR Description The default setting for echo command is ON. When ON the ISP command handler sends the received serial data back to the host. Example "A 0" turns echo off. 9.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware "OK" to continue further transmission. If the check-sum does not match then the host should respond with "RESEND". In response the ISP command handler sends the data again. Table 610. ISP Read Memory command Command R Input Start Address: Address from where data bytes are to be read. This address should be a word boundary. Number of Bytes: Number of bytes to be read. Count should be a multiple of 4.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware 9.7 Copy RAM to Flash Table 612. ISP Copy command Command C Input Flash Address(DST): Destination Flash address where data bytes are to be written. The destination address should be a 256 byte boundary. RAM Address(SRC): Source RAM address from where data bytes are to be read. Number of Bytes: Number of bytes to be written. Should be 256 | 512 | 1024 | 4096.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware 9.9 Erase sector(s) Table 614. ISP Erase sector command Command E Input Start Sector Number End Sector Number: Should be greater than or equal to start sector number.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware Table 617. LPC24xx part Identification numbers Device ASCII/dec coding Hex coding LPC2458 352386869 0x1500 FF35 LPC2468 369164085 0x1600 FF35 LPC2478 386006837 0x1701 FF35 9.12 Read Boot code version number Table 618. ISP Read Boot Code version number command Command K Input None Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format. It is to be interpreted as .
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware Table 620. ISP Return Codes Summary Return Mnemonic Code Description 3 DST_ADDR_ERROR Destination address is not on a correct boundary. 4 SRC_ADDR_NOT_MAPPED Source address is not mapped in the memory map. Count value is taken in to consideration where applicable. 5 DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory map. Count value is taken in to consideration where applicable.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware Define the IAP location entry point. Since the 0th bit of the IAP location is set there will be a change to Thumb instruction set when the program counter branches to this address.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware The Flash memory is not accessible during a write or erase operation. IAP commands, which results in a Flash write/erase operation, use 32 bytes of space in the top portion of the on-chip RAM for execution. The user program should not be use this space if IAP Flash programming is permitted in the application. Table 621.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware Table 622. IAP Prepare sector(s) for write operation command Command Prepare sector(s) for write operation Input Command code: 5010 Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number). Return Code CMD_SUCCESS | BUSY | INVALID_SECTOR Result None Description This command must be executed before executing "Copy RAM to Flash" or "Erase Sector(s)" command.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware 10.3 Erase Sector(s) Table 624. IAP Erase Sector(s) command Command Erase Sector(s) Input Command code: 5210 Param0: Start Sector Number Param1: End Sector Number (should be greater than or equal to start sector number). Param2: System Clock Frequency (CCLK) in kHz.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware 10.6 Read Boot code version number Table 627. IAP Read Boot Code version number command Command Read boot code version number Input Command code: 5510 Parameters: None Return Code CMD_SUCCESS | Result Result0: 2 bytes of boot code version number in ASCII format. It is to be interpreted as . Description This command is used to read the boot code version number. 10.
UM10237 NXP Semiconductors Chapter 30: LPC24XX Flash memory programming firmware Table 629. Reinvoke ISP Command Compare Return Code None Result None. Description This command is used to invoke the bootloader in ISP mode. It maps boot vectors, sets PCLK = CCLK / 4, configures UART0 pins Rx and Tx, restets TIMER1 and resets the U0FDR (see Section 16–4.12). This command may be used when a valid user program is present in the internal Flash memory and the P2.
UM10237 Chapter 31: LPC24XX On-chip bootloader for flashless parts Rev. 02 — 19 December 2008 User manual 1. How to read this chapter Remark: This chapter describes the boot process for flashless parts LPC2420/60 and LPC2470. It does not apply to parts LPC2458, LPC2468, and LPC2478. The on-chip bootloader version 3.4 controls the boot process for flashless LPC2400 parts LPC2420/60 and LPC2470. 2.
UM10237 NXP Semiconductors Chapter 31: LPC24XX On-chip bootloader for flashless parts Pin P2.10 that is used as hardware request for ISP requires special attention. Since P2.10 is in high impedance mode after reset, it is important that the user provides external hardware (a pull-up resistor or other device) to put the pin in a defined state. Otherwise unintended entry into ISP mode may occur. When ISP mode is entered after a power on reset, the IRC and PLL are used to generate CCLK of 14.748 MHz. 4.
UM10237 NXP Semiconductors Chapter 31: LPC24XX On-chip bootloader for flashless parts 4.2.1 ISP command format "Command Parameter_0 Parameter_1 ... Parameter_n" "Data" (Data only for Write commands). 4.2.2 ISP response format "Return_CodeResponse_0Response_1 ... Response_n" "Data" (Data only for Read commands). 4.2.3 ISP data format The data stream is in UU-encode format.
UM10237 NXP Semiconductors Chapter 31: LPC24XX On-chip bootloader for flashless parts 4.2.9 RAM used by IAP command handler IAP programming commands use the top 32 bytes of on-chip RAM. The maximum stack usage in the user allocated stack space is 128 bytes and it grows downwards. 4.2.10 RAM used by RealMonitor The RealMonitor uses on-chip RAM from 0x4000 0040 to 0x4000 011F. The user could use this area if RealMonitor based debug is not required.
UM10237 NXP Semiconductors Chapter 31: LPC24XX On-chip bootloader for flashless parts 6. ISP commands The following commands are accepted by the ISP command handler. Detailed status codes are supported for each command. The command handler sends the return code INVALID_COMMAND when an undefined command is received. Commands and return codes are in ASCII format.
UM10237 NXP Semiconductors Chapter 31: LPC24XX On-chip bootloader for flashless parts Table 633. ISP Set Baud Rate command Command B Return Code CMD_SUCCESS | INVALID_BAUD_RATE | INVALID_STOP_BIT | PARAM_ERROR Description This command is used to change the baud rate. The new baud rate is effective after the command handler sends the CMD_SUCCESS return code. Example "B 57600 1" sets the serial port to baud rate 57600 bps and 1 stop bit. Table 634.
UM10237 NXP Semiconductors Chapter 31: LPC24XX On-chip bootloader for flashless parts continue further transmission. If the check-sum does not match, the ISP command handler responds with "RESEND". In response the host should retransmit the bytes. Table 636. ISP Write to RAM command Command W Input Start Address: RAM address where data bytes are to be written. This address should be a word boundary. Number of Bytes: Number of bytes to be written.
UM10237 NXP Semiconductors Chapter 31: LPC24XX On-chip bootloader for flashless parts 6.6 Go
Table 638. ISP Go command Command G Input Address: RAM address from which the code execution is to be started. This address should be on a word boundary. Mode: T (Execute program in Thumb Mode) | A (Execute program in ARM mode).UM10237 NXP Semiconductors Chapter 31: LPC24XX On-chip bootloader for flashless parts 6.9 Compare Table 642. ISP Compare command Command M Input Address1 (DST): Starting RAM address of data bytes to be compared. This address should be a word boundary. Address2 (SRC): StartingRAM address of data bytes to be compared. This address should be a word boundary. Number of Bytes: Number of bytes to be compared; should be a multiple of 4.
UM10237 NXP Semiconductors Chapter 31: LPC24XX On-chip bootloader for flashless parts Table 643. ISP Return Codes Summary Return Mnemonic Code Description 14 ADDR_NOT_MAPPED Address is not mapped in the memory map. Count value is taken in to consideration where applicable. 15 CMD_LOCKED Command is locked. 16 INVALID_CODE Unlock code is invalid. 17 INVALID_BAUD_RATE Invalid baud rate setting. 18 INVALID_STOP_BIT Invalid stop bit setting. 19 - not used 7.
UM10237 NXP Semiconductors Chapter 31: LPC24XX On-chip bootloader for flashless parts Setting function pointer: iap_entry=(IAP) IAP_LOCATION; Whenever you wish to call IAP you could use the following statement. iap_entry (command, result); The IAP call could be simplified further by using the symbol definition file feature supported by ARM Linker in ADS (ARM Developer Suite). You could also call the IAP routine using assembly code.
UM10237 NXP Semiconductors Chapter 31: LPC24XX On-chip bootloader for flashless parts COMMAND CODE PARAMETER 1 command parameter table PARAMETER 2 ARM REGISTER r0 PARAMETER n ARM REGISTER r1 STATUS CODE RESULT 1 command result table RESULT 2 RESULT n Fig 143. IAP parameter passing 7.1 Read Part Identification number Table 645.
UM10237 NXP Semiconductors Chapter 31: LPC24XX On-chip bootloader for flashless parts 7.3 Compare Table 647. IAP Compare command Command Compare Input Command code: 5610 Param0(DST): Starting RAM address of data bytes to be compared. This address should be a word boundary. Param1(SRC): Starting RAM address of data bytes to be compared. This address should be a word boundary. Param2: Number of bytes to be compared; should be a multiple of 4.
UM10237 NXP Semiconductors Chapter 31: LPC24XX On-chip bootloader for flashless parts Table 649. IAP Status Codes Summary Status Mnemonic Code Description 3 DST_ADDR_ERROR Destination address is not on a correct boundary. 4 SRC_ADDR_NOT_MAPPED Source address is not mapped in the memory map. Count value is taken in to consideration where applicable. 5 DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory map. Count value is taken in to consideration where applicable.
UM10237 Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller Rev. 02 — 19 December 2008 User manual 1. Basic configuration The GPDMA is configured using the following registers: 1. Power: In the PCONP register (Table 4–63), set bit PCGPDMA. Remark: On reset, the GPDMA is disabled (PCGPDMA = 0). 2. Clock: see Table 4–53. 3. Interrupts are enabled in the VIC using the VICIntEnable register (Section 7–3.4). 4. Initialization: see Section 32–5. 2.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller • Supports 8, 16, and 32 bit wide transactions. • Big-endian and little-endian support. The GPDMA defaults to little-endian mode on reset. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Interrupt masking. The DMA error and DMA terminal count interrupt requests can be masked. • Raw interrupt status.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller example, a bidirectional port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master. Figure 32–144 shows a block diagram of the GPDMA.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller 4.2.4 Channel Logic and Channel Register Bank The channel logic and channel register bank contains registers and logic required for each DMA channel. 4.2.5 Interrupt Request The interrupt request generates interrupts to the ARM processor. 4.2.6 AHB Master Interface The GPDMA contains a full AHB master. See Figure 32–145 for an example showing the GPDMA connected into a system.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller Table 32–651 shows endian behavior for different source and destination combinations. Table 651.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller Table 651.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller 4.2.10 Channel hardware Each stream is supported by a dedicated hardware channel, including source and destination controllers, and a FIFO. This enables better latency than a DMA controller with only a single hardware channel shared between several DMA streams and simplifies the control logic. 4.2.11 DMA request priority DMA channel priority is fixed.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller Table 652. DMA Connections Peripheral Function DMA Single Request Input DMA Burst Request Input DMA Last Word DMA Last Burst Request Input Request Input SSP1 Rx 3 - 3 - SD/MMC 4 4 4 4 I2S channel 0 - 5 - - I2S channel 1 - 6 - - 5. Programming the GPDMA The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller 5.3 Enabling a DMA channel To enable the DMA channel set the Channel Enable bit in the relevant DMA channel Configuration Register ( Section 32–6.2.6 “Channel Configuration Registers (DMACC0Configuration - 0xFFE0 4110 and DMACC1Configuration - 0xFFE0 4130)”). Note: The channel must be fully initialized before it is enabled. Additionally, you must set the Enable bit of the GPDMA before any channels are enabled. 5.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller 5.9 Programming a DMA channel To program a DMA channel: 1. Choose a free DMA channel with the priority required. DMA channel 0 has the highest priority and DMA channel 1 the lowest priority. 2. Clear any pending interrupts on the channel to be used by writing to the DMACIntTCClr Register (Section 32–6.1.3 “Interrupt Terminal Count Clear Register (DMACIntClear - 0xFFE0 4008)”) and DMACIntErrClr Register (Section 32–6.1.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller Table 653.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller Table 654. Interrupt Status register (DMACIntStatus - address 0xFFE0 4000) bit description Bit Symbol Description Reset Value 0 IntStatus0 Status of channel 0 interrupts after masking. 0 1 IntStatus1 Status of channel 1 interrupts after masking. 0 31:2 - Reserved, user software should not write ones to reserved bits. NA The value read from a reserved bit is not defined. 6.1.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller Table 657. Interrupt Error Status register (DMACIntErrorStatus - address 0xFFE0 400C) bit description Bit Symbol Description Reset Value 0 IntErrorStatus0 Interrupt error status for channel 0. 0x0 1 IntErrorStatus1 Interrupt error status for channel 1. 0x0 31:2 - Reserved, user software should not write ones to reserved bits. NA The value read from a reserved bit is not defined. 6.1.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller Table 660. Raw Error Interrupt Status register (DMACRawIntErrorStatus - address 0xFFE0 4018) bit description Bit Symbol Description Reset Value 0 RawIntErrorStatus0 Status of the error interrupt for channel 0 prior to masking. - 1 RawIntErrorStatus1 Status of the error interrupt for channel 1 prior to masking. - 31:2 - NA Reserved, user software should not write ones to reserved bits.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller 6.1.10 Software Single Request Register (DMACSoftSReq - 0xFFE0 4024) The DMACSoftSReq Register is read/write and enables DMA single requests to be generated by software. A DMA request can be generated for each source by writing a 1 to the corresponding register bit. A register bit is cleared when the transaction has completed. Writing 0 to this register has no effect.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller Table 665. Software Last Single Request register (DMACSoftLSReq - address 0xFFE0 402C) bit description Bit Symbol Description Reset Value 3:0 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. NA 4 SoftLSReqSDMMC Software last single request flags for SD/MMC. 0 31:5 - Reserved, user software should not write ones to reserved bits.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller 6.2 Channel registers The channel registers are used to program the two DMA channels. These registers consist of: • • • • • Two DMACCxSrcAddr Registers Two DMACCxDestAddr Registers Two DMACCxLLI Registers Two DMACCxControl Registers Two DMACCxConfiguration Registers When performing scatter/gather DMA the first four registers are automatically updated. 6.2.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller Table 669. Channel Destination Address registers (DMACC0DestAddr - address 0xFFE0 4104 and DMACC1DestAddr - address 0xFFE0 4124) bit description Bit Symbol Description Reset Value 31:0 DestAddr DMA destination address 0x0000 0000 6.2.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller Table 671. Channel Control registers (DMACC0Control - address 0xFFE0 410C and DMACC1Control - address 0xFFE0 412C) bit description Bit Symbol 11:0 TransferSize Transfer size. A write to this field sets the size of the transfer 0 when the GPDMA is the flow controller.A read from this field indicates the number of transfers completed on the destination bus.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller Table 672. Source or destination burst size Bit value of DBSize or SBSize Source or distention burst transfer request size 100 32 101 64 110 128 111 256 Table 32–673 shows the value of the 3 bit SWidth or DWidth fields and the corresponding transfer width. Table 673.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller Table 674. Protection bits DMACC1Control Value Bit Description Reset Value 30 Cacheable or not cacheable. This indicates that the access is 0 cacheable. This bit can, for example, be used to indicate to an AMBA bridge that when it saw the first read of a burst of eight it can transfer the whole burst of eight reads on the destination bus, rather than pass the transactions through one at a time.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller Table 675. Channel Configuration registers (DMACC0Configuration - address 0xFFE0 4110 and DMACC1Configuration - address 0xFFE0 4130) bit description Bit Symbol Value Description 4:1 SrcPeripheral 5 - 9:6 DestPeriphera l 10 - Reset Value Source peripheral. This value selects the DMA source request peripheral.This field is ignored if the source of the transfer is from memory.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller There are situations when the GPDMA asserts the lock for source transfers followed by destination transfers. This is possible when internal conditions in the GPDMA permit it to perform a source fetch followed by a destination drain back-to-back. 6.2.8 Flow control and transfer type Table 32–676 lists the bit values of the three flow control and transfer type bits. Table 676.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller 8.2 Programming the GPDMA for scatter/gather DMA To program the GPDMA for scatter/gather DMA: 1. Write the LLIs for the complete DMA transfer to memory. Each linked list item contains four words: – Source address. – Destination address. – Pointer to next LLI. – Control word. The last LLI has its linked list word pointer set to 0. The LLIs must be stored in the memory where the GPDMA has access to (i.e.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller • • • • • • Source start address 0x0A200. Destination address set to the destination peripheral address. Transfer width, word (32 bit). Transfer size, 3 072 bytes (0XC00). Source and destination burst sizes, 16 transfers. Next LLI address, 0x20010. The second LLI, stored at 0x20010 , describes the next block of data to be transferred: • • • • • • Source start address 0x0B200.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller 9.1 Hardware interrupt sequence flow When a DMA interrupt request occurs, the Interrupt Service Routine needs to: 1. Read the DMACIntStatus Register to determine which channel generated the interrupt. If more than one request is active it is recommended that the highest priority channels be checked first. 2.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller Table 677.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller – The DMA stream has the highest pending priority. – The GPDMA is the bus master of the AHB bus. 4. If an error occurs while transferring the data an error interrupt is generated, then finishes. 5. Decrement the transfer count if the GPDMA is performing the flow control. 6.
UM10237 NXP Semiconductors Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller 11. Flow control The peripheral that controls the length of the packet is known as the flow controller. The flow controller is usually the GPDMA where the packet length is programmed by software before the DMA channel is enabled. If the packet length is unknown when the DMA channel is enabled, either the source or destination peripherals can be used as the flow controller.
UM10237 Chapter 33: LPC24XX EmbeddedICE Rev. 02 — 19 December 2008 User manual 1. Features • No target resources are required by the software debugger in order to start the debugging session. • Allows the software debugger to talk via a JTAG (Joint Test Action Group) port directly to the core. • Inserts instructions directly in to the ARM7TDMI-S core. • The ARM7TDMI-S core or the System state can be examined, saved or changed depending on the type of instruction inserted.
UM10237 NXP Semiconductors Chapter 33: LPC24XX EmbeddedICE trigger on an access to a peripheral and the second to trigger on the code segment that performs the task switching. Therefore when the breakpoints trigger the information regarding which task has switched out will be ready for examination. • The watchpoints can be configured such that a range of addresses are enabled for the watchpoints to be active.
UM10237 NXP Semiconductors Chapter 33: LPC24XX EmbeddedICE 5. JTAG function select Remark: JTAG access to the LPC2400 is only possible if no code read protection is selected, see Section 3–5. The JTAG port may be used either for debug or for boundary scan. The state of the DBGEN pin determines which function is available. When DBGEN = 0, the JTAG port may be used for boundary scan. When DBGEN = 1, the JTAG port may be used for debug. 6.
UM10237 NXP Semiconductors Chapter 33: LPC24XX EmbeddedICE JTAG PORT serial parallel interface EMBEDDED ICE INTERFACE PROTOCOL CONVERTER 5 EMBEDDED ICE host running debugger ARM7TDMI-S TARGET BOARD Fig 147. EmbeddedICE debug environment block diagram UM10237_2 User manual © NXP B.V. 2008. All rights reserved. Rev.
UM10237 Chapter 34: LPC24XX Embedded Trace Module (ETM) Rev. 02 — 19 December 2008 User manual 1. Features • • • • • • Closely track the instructions that the ARM core is executing. One external trigger input. 10 pin interface. All registers are programmed through JTAG interface. Does not consume power when trace is not being used. THUMB instruction set support. 2.
UM10237 NXP Semiconductors Chapter 34: LPC24XX Embedded Trace Module (ETM) Table 680. ETM configuration Resource number/type Small[1] External Inputs 2 External Outputs 0 FIFOFULL Present Yes (Not wired) FIFO depth 10 bytes Trace Packet Width 4/8 [1] For details refer to ARM documentation "Embedded Trace Macrocell Specification (ARM IHI 0014E)". 4. Pin description Table 681. ETM pin description Pin Name Type Description TRACECLK Output Trace Clock.
UM10237 NXP Semiconductors Chapter 34: LPC24XX Embedded Trace Module (ETM) Table 682. ETM Registers Name Description Access Register Encoding ETM Control Controls the general operation of the ETM. R/W 000 0000 ETM Configuration Code Allows a debugger to read the number of each type of resource. RO 000 0001 Trigger Event Holds the controlling event. WO 000 0010 Memory Map Decode Control Eight bit register, used to statically configure WO the memory map decoder.
UM10237 NXP Semiconductors Chapter 34: LPC24XX Embedded Trace Module (ETM) 7. Block diagram The block diagram of the ETM debug environment is shown below in Figure 34–148. APPLICATION PCB CONNECTOR TRACE PORT ANALYZER TRACE 10 ETM TRIGGER PERIPHERAL PERIPHERAL CONNECTOR Host running debugger RAM JTAG INTERFACE UNIT 5 ARM ROM EMBEDDED ICE LAN Fig 148. ETM debug environment block diagram UM10237_2 User manual © NXP B.V. 2008. All rights reserved. Rev.
UM10237 Chapter 35: LPC24XX RealMonitor Rev. 02 — 19 December 2008 User manual 1. Features Remark: RealMonitor is a configurable software module which enables real time debug. RealMonitor is developed by ARM Inc. Information presented in this chapter is taken from the ARM document RealMonitor Target Integration Guide (ARM DUI 0142A). It applies to a specific configuration of RealMonitor software programmed in the on-chip ROM boot memory of this device.
UM10237 NXP Semiconductors Chapter 35: LPC24XX RealMonitor processor context saving and restoring. RealMonitor is pre-programmed in the on-chip ROM memory (boot sector). When enabled It allows user to observe and debug while parts of application continue to run. Refer to Section 35–4 “How to enable RealMonitor” on page 751 for details. 3.1 RealMonitor components As shown in Figure 35–149, RealMonitor is split in to two functional components: DEBUGGER RDI 1.5.1 host REALMONITOR.DLL RMHOST RDI 1.5.
UM10237 NXP Semiconductors Chapter 35: LPC24XX RealMonitor 3.2 How RealMonitor works In general terms, the RealMonitor operates as a state machine, as shown in Figure 35–150. RealMonitor switches between running and stopped states, in response to packets received by the host, or due to asynchronous events on the target. RMTarget supports the triggering of only one breakpoint, watchpoint, stop, or semihosting SWI at a time. There is no provision to allow nested events to be saved and restored.
UM10237 NXP Semiconductors Chapter 35: LPC24XX RealMonitor – Undef exception caused by the undefined instructions in user foreground application. This indicates an error in the application being debugged. RealMonitor stops the user application until a "Go" packet is received from the host. When one of these exceptions occur that is not handled by user application, the following happens: • RealMonitor enters a loop, polling the DCC.
UM10237 NXP Semiconductors Chapter 35: LPC24XX RealMonitor 4.5 Prefetch Abort mode RealMonitor uses four words on entry to its Prefetch abort interrupt handler. 4.6 Data Abort mode RealMonitor uses four words on entry to its data abort interrupt handler. 4.7 User/System mode RealMonitor makes no use of this stack. 4.8 FIQ mode RealMonitor makes no use of this stack. 4.9 Handling exceptions This section describes the importance of sharing exception handlers between RealMonitor and user application.
UM10237 NXP Semiconductors Chapter 35: LPC24XX RealMonitor RealMonitor supplied exception vector handlers RM_UNDEF_HANDLER() RM_PREFETCHABORT_HANDLER() RM_DATAABORT_HANDLER() RM_IRQHANDLER() RESET UNDEF SWI sharing IRQs between RealMonitor and user IRQ handler PREFETCH ABORT RM_IRQHANDLER2() DATA ABORT APP_IRQDISPATCH RESERVED APP_IRQHANDLER2() OR IRQ FIQ Fig 151. Exception handlers 4.
UM10237 NXP Semiconductors Chapter 35: LPC24XX RealMonitor NOP ; Insert User code valid signature here.
UM10237 NXP Semiconductors Chapter 35: LPC24XX RealMonitor ; ; ; ; ; ; ; ; /********************************************************************* * Setup Vectored Interrupt controller. DCC Rx and Tx interrupts * generate Non Vectored IRQ request. rm_init_entry is aware * of the VIC and it enables the DBGCommRX and DBGCommTx interrupts. * Default vector address register is programmed with the address of * Non vectored app_irqDispatch mentioned in this example. User can setup * Vectored IRQs or FIQs here.
UM10237 NXP Semiconductors Chapter 35: LPC24XX RealMonitor ;is not aware of the VIC interrupt priority hardware so trick ;rm_irqhandler2 to return here STMFD sp!, {ip,pc} LDR pc, rm_irqhandler2 ;rm_irqhandler2 returns here MSR cpsr_c, #0x52 MSR spsr, r12 STMFD sp!, {r0} LDR r0, =VICBaseAddr STR r1, [r0,#VICVectAddrOffset] LDMFD sp!, {r12,r14,r0} SUBS pc, r14, #4 ;Disable irq, move to IRQ mode ;Restore SPSR from r12 ;Acknowledge Non Vectored irq has finished ;Restore registers ;Return to the interrupted
UM10237 NXP Semiconductors Chapter 35: LPC24XX RealMonitor RM_OPT_READBYTES=TRUE RM_OPT_WRITEBYTES=TRUE RM_OPT_READHALFWORDS=TRUE RM_OPT_WRITEHALFWORDS=TRUE RM_OPT_READWORDS=TRUE RM_OPT_WRITEWORDS=TRUE Enables/Disables support for 8/16/32 bit read/write. RM_OPT_EXECUTECODE=FALSE Enables/Disables support for executing code from "execute code" buffer. The code must be downloaded first. RM_OPT_GETPC=TRUE This option enables or disables support for the RealMonitor GetPC packet.
UM10237 NXP Semiconductors Chapter 35: LPC24XX RealMonitor This option specifies the size, in words, of the data logging FIFO buffer. CHAIN_VECTORS=FALSE This option allows RMTarget to support vector chaining through µHAL (ARM HW abstraction API). UM10237_2 User manual © NXP B.V. 2008. All rights reserved. Rev.
UM10237 Chapter 36: LPC24XX Supplementary information Rev. 02 — 19 December 2008 User manual 1. Abbreviations Table 684.
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 2. Legal information 2.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 2.
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 3. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. LPC24XX overview. . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 0xFFE0 8028) bit description . . . . . . . . . . . . . .81 Table 74. Dynamic Memory Percentage Command Period register (EMCDynamictRP - address 0xFFE0 8030) bit description . . . . . . . . . . . . . .82 Table 75. Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS - address 0xFFE0 8034) bit description . . . . . . . . . . . . . .82 Table 76.
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information Interrupt Controller . . . . . . . . . . . . . . . . . . . . . 115 Table 117. Interrupt sources bit allocation table . . . . . . . . 117 Table 118. LPC2400 pin configurations overview . . . . . . 119 Table 119. LPC2458 pin allocation table . . . . . . . . . . . . .120 Table 120.Pin description . . . . . . . . . . . . . . . . . . . . . . . .123 Table 121.LPC2420/60/68 pin allocation table . . . . . . . .136 Table 122.
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information Table 175.GPIO overall Interrupt Status register (IOIntStatus - address 0xE002 8080) bit description . . . . .206 Table 176.GPIO Interrupt Enable for Rising edge register (IO0IntEnR - address 0xE002 8090 and IO2IntEnR - address 0xE002 80B0) bit description . . . . . . . . . . . . . . . . . . . . . . . . .206 Table 177.
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information Table 228.Interrupt Status register (IntStatus - address 0xFFE0 0FE0) bit description . . . . . . . . . . . . .238 Table 229.Interrupt Enable register (intEnable - address 0xFFE0 0FE4) bit description . . . . . . . . . . . . .238 Table 230.Interrupt Clear register (IntClear - address 0xFFE0 0FE8) bit description . . . . . . . . . . . . .239 Table 231.Interrupt Set register (IntSet - address 0xFFE0 0FEC) bit description. . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information (USBDevIntSt - address 0xFFE0 C200) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 Table 299.USB Device Interrupt Status register (USBDevIntSt - address 0xFFE0 C200) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .339 Table 300.USB Device Interrupt Enable register (USBDevIntEn - address 0xFFE0 C204) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 Table 301.
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information description . . . . . . . . . . . . . . . . . . . . . . . . . . .358 Table 345.USB System Error Interrupt Clear register (USBSysErrIntClr - address 0xFFE0 C2BC) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .359 Table 346.USB System Error Interrupt Set register (USBSysErrIntSet - address 0xFFE0 C2C0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .359 Table 347.SIE command code table . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information Table 401:UART1 Interrupt Enable Register (U1IER address 0xE001 0004 when DLAB = 0) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .448 Table 402:UART1 Interrupt Identification Register (U1IIR address 0xE001 0008, Read Only) bit description 449 Table 403:UART1 Interrupt Handling . . . . . . . . . . . . . . .451 Table 404:UART1 FIFO Control Register (U1FCR - address 0xE001 0008, Write Only) bit description . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information Table 452.FullCAN Interrupt and Capture register 0 (FCANIC0 - address 0xE003 C024) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .505 Table 453.FullCAN Interrupt and Capture register 1 (FCANIC1 - address 0xE003 C028) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .505 Table 454.Format of automatically stored Rx messages.509 Table 455.FullCAN semaphore operation . . . . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information Table 514.I2C Control Set Register (I2C[0/1/2]CONCLR addresses 0xE001 C018, 0xE005 C018, 0xE008 0018) bit description . . . . . . . . . . . . .584 Table 515.I2C Status Register (I2C[0/1/2]STAT - addresses 0xE001 C004, 0xE005 C004, 0xE008 0004) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .584 Table 516.I2C Data Register ( I2C[0/1/2]DAT - addresses 0xE001 C008, 0xE005 C008, 0xE008 0008) bit description . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information Table 573.Alarm Mask Register (AMR - address 0xE002 4010) bit description . . . . . . . . . . . . .653 Table 574.Consolidated Time register 0 (CTIME0 - address 0xE002 4014) bit description . . . . . . . . . . . . .654 Table 575.Consolidated Time register 1 (CTIME1 - address 0xE002 4018) bit description . . . . . . . . . . . . .654 Table 576.Consolidated Time register 2 (CTIME2 - address 0xE002 401C) bit description . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information Table 656.Interrupt Terminal Count Clear register (DMACIntClear - address 0xFFE0 4008) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .722 Table 657.Interrupt Error Status register (DMACIntErrorStatus - address 0xFFE0 400C) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .723 Table 658.Interrupt Error Clear register (DMACIntErrClr address 0xFFE0 4010) bit description . . . . . .723 Table 659.
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 4. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. Fig 29. Fig 30. Fig 31. Fig 32. Fig 33. Fig 34. Fig 35. Fig 36. Fig 37. Fig 38. Fig 39. Fig 40. Fig 41. Fig 42. Fig 43. Fig 44. Fig 45. Fig 46. LPC2458 block diagram . . . . . . . . . . . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information Fig 88. Message overwritten indicated by semaphore bits and message lost. . . . . . . . . . . . . . . . . . . . . . . .516 Fig 89. Message overwritten indicated by message lost517 Fig 90. Clearing message lost . . . . . . . . . . . . . . . . . . . .518 Fig 91. Detailed example of acceptance filter tables and ID index values. . . . . . . . . . . . . . . . . . . . . . . . . . . .520 Fig 92.
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 5. Contents Chapter 1: LPC24XX Introductory information 1 2 3 4 5 5.1 5.2 5.3 5.4 5.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to read this manual . . . . . . . . . . . . . . . . . . LPC2400 features. . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering options . . . . . . . . . . . . . . . . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 3.2.14 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.4 3.4.1 3.4.2 PLL setup sequence . . . . . . . . . . . . . . . . . . . . 56 Clock dividers . . . . . . . . . . . . . . . . . . . . . . . . . 56 CPU Clock Configuration register (CCLKCFG 0xE01F C104) . . . . . . . . . . . . . . . . . . . . . . . . 57 USB Clock Configuration register (USBCLKCFG 0xE01F C108) . . . . . . . . . . . . . . . . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 10.26 10.27 Static Memory Write Delay registers (EMCStaticWaitwr0-3 - 0xFFE0 8214, 234, 254, 274) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3 - 0xFFE0 8218, 238, 258, 278) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11 11.1 11.2 11.3 11.4 External memory interface . . . . . . . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 5.9 5.10 5.11 5.12 5.13 5.14 5.15 Pin Function Select Register 8 (PINSEL8 0xE002 C020). . . . . . . . . . . . . . . . . . . . . . . . 186 Pin Function Select Register 9 (PINSEL9 0xE002 C024). . . . . . . . . . . . . . . . . . . . . . . . 187 Pin Function Select Register 10 (PINSEL10 0xE002 C028). . . . . . . . . . . . . . . . . . . . . . . . 188 Pin Function Select Register 11 (PINSEL11 0xE002 C02C) . . . . . . . . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 7.1.8 7.1.9 7.1.10 7.1.11 7.1.12 7.1.13 7.1.14 7.1.15 7.1.16 7.1.17 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16 7.2.17 7.3 Test Register (TEST - 0xFFE0 001C). . . . . . 223 MII Mgmt Configuration Register (MCFG 0xFFE0 0020) . . . . . . . . . . . . . . . . . . . . . . . . 224 MII Mgmt Command Register (MCMD 0xFFE0 0024) . . . . . . . . . . . . . . . . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 4.1 4.2 4.3 4.4 4.5 4.6 5 5.1 5.1.1 5.1.2 5.1.3 6 6.1 6.1.1 6.1.2 6.2 Programmable parameters . . . . . . . . . . . . . . 281 Hardware cursor support . . . . . . . . . . . . . . . 281 Types of LCD panels supported . . . . . . . . . . 282 TFT panels . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Color STN panels . . . . . . . . . . . . . . . . . . . . . 282 Monochrome STN panels . . . . . . . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 7 7.1 8 8.1 8.2 8.3 8.4 9 9.1 9.1.1 9.2 9.2.1 9.2.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.5 9.5.1 9.5.2 9.5.3 9.5.4 9.6 9.6.1 9.6.2 9.6.3 9.6.4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 333 USB device usage note . . . . . . . . . . . . . . . . 333 Clocking and power management . . . . . . . . 333 Power requirements . . . . . . . . . . . . . . . . . . . 334 Clocks. . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 12 13 13.1 13.2 13.3 14 14.1 14.2 14.3 14.4 14.4.1 14.4.2 14.4.3 14.4.4 14.4.5 14.4.6 14.4.7 14.4.8 Read Test Register (Command: 0xFD, Data: read 2 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Set Device Status (Command: 0xFE, Data: write 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 OTG Interrupt Enable Register (OTGIntEn 0xFFE0 C104) . . . . . . . . . . . . . . . . . . . . . . . 401 OTG Interrupt Set Register (OTGIntSet 0xFFE0 C20C) . . . . . . . . . . . . . . . . . . . . . . . 401 OTG Interrupt Clear Register (OTGIntClr 0xFFE0 C10C) . . . . . . . . . . . . . . . . . . . . . . . 401 OTG Status and Control Register (OTGStCtrl 0xFFE0 C110). . . . . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 17.4.9.1 17.4.9.2 UART1 Receiver Buffer Register (U1RBR 0xE001 0000, when DLAB = 0 Read Only) . 447 UART1 Transmitter Holding Register (U1THR 0xE001 0000 when DLAB = 0, Write Only) . 447 UART1 Divisor Latch LSB and MSB Registers (U1DLL - 0xE001 0000 and U1DLM 0xE001 0004, when DLAB = 1) . . . . . . . . . . 447 UART1 Interrupt Enable Register (U1IER 0xE001 0004, when DLAB = 0) . . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 9.3 9.4 10 10.1 10.2 10.3 11 12 12.1 12.2 12.3 12.4 13 14 15 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 15.10 15.11 15.12 16 16.1 17 17.1 17.2 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 Transmit priority . . . . . . . . . . . . . . . . . . . . . . 495 Centralized CAN registers. . . . . . . . . . . . . . . 495 Central Transmit Status Register (CANTxSR 0xE004 0000) . . . . . . . . . . . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 7.4 7.5 SPI Clock Counter Register (S0SPCCR 0xE002 000C). . . . . . . . . . . . . . . . . . . . . . . . 533 SPI Test Control Register (SPTCR 0xE002 0010) . . . . . . . . . . . . . . . . . . . . . . . . 533 7.6 7.7 8 SPI Test Status Register (SPTSR - 0xE002 0014) 534 SPI Interrupt Register (S0SPINT - 0xE002 001C) 534 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 6.14 FIFO Counter Register (MCIFifoCnt 0xE008 C048). . . . . . . . . . . . . . . . . . . . . . . . 571 6.15 Data FIFO Register (MCIFIFO - 0xE008 C080 to 0xE008 C0BC) . . . . . . . . . . . . . . . . . . . . . . . 571 Chapter 22: LPC24XX I2C interfaces I2C0/1/2 1 2 3 4 5 6 6.1 6.2 6.3 6.4 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 8 8.1 Basic configuration . . . . . . . . . . . . . . . . . . . . 572 Features . . . . . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 3 4 5 5.1 5.2 5.3 5.4 5.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . Register description . . . . . . . . . . . . . . . . . . . Digital Audio Output Register (I2SDAO 0xE008 8000) . . . . . . . . . . . . . . . . . . . . . . . . Digital Audio Input Register (I2SDAI 0xE008 8004) . . . . . . . . . . . . . . . . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 5 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.3 6.3.1 6.3.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 648 Register description . . . . . . . . . . . . . . . . . . . 649 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . 650 Miscellaneous register group . . . . . . . . . . . . 650 Interrupt Location Register (ILR - 0xE002 4000) . 650 Clock Tick Counter Register (CTCR 0xE002 4004) . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 5.2.10 6 7 8 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 ISP flow control. . . . . . . . . . . . . . . . . . . . . . . 679 ISP command abort . . . . . . . . . . . . . . . . . . . 679 Interrupts during ISP. . . . . . . . . . . . . . . . . . . 679 Interrupts during IAP. . . . . . . . . . . . . . . . . . . 679 RAM used by ISP command handler . . . . . . 679 RAM used by IAP command handler . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 Programming the GPDMA. . . . . . . . . . . . . . . 718 Enabling the GPDMA . . . . . . . . . . . . . . . . . . 718 Disabling the GPDMA. . . . . . . . . . . . . . . . . . 718 Enabling a DMA channel . . . . . . . . . . . . . . . 719 Disabling a DMA channel . . . . . . . . . . . . . . .
UM10237 NXP Semiconductors Chapter 36: LPC24XX Supplementary information 3.1.1 3.1.2 3.2 4 4.1 4.2 4.3 4.4 4.5 RMHost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . RMTarget . . . . . . . . . . . . . . . . . . . . . . . . . . . How RealMonitor works . . . . . . . . . . . . . . . . How to enable RealMonitor. . . . . . . . . . . . . . Adding stacks . . . . . . . . . . . . . . . . . . . . . . . . IRQ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . Undef mode . . . . . . . . . . . . . .
