56F805 Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F805 Rev. 16 09/2007 freescale.
Document Revision History Version History Rev. 16 Description of Change Added revision history. Added this text to footnote 2 in Table 3-8: “However, the high pulse width does not have to be any particular percent of the low pulse width.
56F805 General Description • Up to 40 MIPS at 80MHz core frequency • Two 6-channel PWM Modules • DSP and MCU functionality in a unified, C-efficient architecture • Two 4-channel, 12-bit ADCs • Two Quadrature Decoders • Hardware DO and REP loops • CAN 2.0 B Module • MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes • Two Serial Communication Interfaces (SCIs) • Serial Peripheral Interface (SPI) • 31.
Part 1 Overview 1.1 56F805 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
6F805 Description • • • • • • • • • • • 1.1.4 • • • • Two General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with four pins CAN 2.
The 56F805 incorporates a total of 2K words of Boot Flash for easy customer-inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased. Key application-specific features of the 56F805 include the two Pulse Width Modulator (PWM) modules.
Product Documentation 1.4 Product Documentation The four documents listed in Table 2-1 are required for a complete description and proper design with the 56F805. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at www.freescale.com.
Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F805 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2 through Table 2-18, each table row describes the signal or signals present on a pin.
Introduction Power Port Ground Port VDD 8 VSS Power Port VDDA Ground Port VSSA 8* 1 VCAPC PLL and Clock EXTAL VPP XTAL CLKO A0-A5 External Data Bus A6-7 (GPIOE2-E3) A8-15 (GPIOA0-A7) D0–D15 PS DS External Bus Control RD WR PHASEA0 (TA0) Quadrature Decoder0 or Quad Timer A PHASEB0 (TA1) INDEX0 (TA2) HOME0 (TA3) PHASEA1 (TB0) Quadrature Decoder1 or Quad Timer B 6 GPIOB0–7 GPIOD0–5 Dedicated GPIO 1 Other Supply Ports External Address Bus or GPIO 8 PHASEB1 (TB1) INDEX1 (TB2) HOME
2.2 Power and Ground Signals Table 2-2 Power Inputs No. of Pins Signal Name Signal Description 8 VDD Power—These pins provide power to the internal structures of the chip, and should all be attached to VDD. 1 VDDA Analog Power—This pin is a dedicated power pin for the analog portion of the chip and should be connected to a low noise 3.3V supply. Table 2-3 Grounds No.
Clock and Phase Locked Loop Signals 2.3 Clock and Phase Locked Loop Signals Table 2-5 PLL and Clock No. of Pins Signal Name Signal Type State During Reset 1 EXTAL Input Input External Crystal Oscillator Input—This input should be connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Section 3.5. 1 XTAL Input/O utput Chip-driven Crystal Oscillator Output—This output should be connected to an 8MHz external crystal or ceramic resonator.
Table 2-7 Data Bus Signals No. of Pins Signal Name Signal Type State During Reset 16 D0–D15 Input/O utput Tri-stated Signal Description Data Bus— D0–D15 specify the data for external Program or Data memory accesses. D0–D15 are tri-stated when the external bus is inactive. Internal pullups may be active. Table 2-8 Bus Control Signals No. of Pins Signal Name Signal Type State During Reset 1 PS Output Tri-stated Program Memory Select—PS is asserted low for external Program memory access.
Interrupt and Program Control Signals 2.5 Interrupt and Program Control Signals Table 2-9 Interrupt and Program Control Signals State During Reset No. of Pins Signal Name Signal Type 1 IRQA Input (Schmitt) Input External Interrupt Request A—The IRQA input is a synchronized external interrupt request indicating an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered.
2.6 GPIO Signals Table 2-10 Dedicated General Purpose Input/Output (GPIO) Signals No. of Pins Signal Name Signal Type State During Reset 8 GPIOB0– GPIOB7 Input or Output Input Signal Description Port B GPIO—These eight dedicated General Purpose I/O (GPIO) pins can be individually programmed as input or output pins. After reset, the default state is GPIO input.
Serial Peripheral Interface (SPI) Signals 2.8 Serial Peripheral Interface (SPI) Signals Table 2-12 Serial Peripheral Interface (SPI) Signals No. of Pins Signal Name Signal Type State During Reset 1 MISO Input/ Output Input SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected.
2.9 Quadrature Decoder Signals Table 2-13 Quadrature Decoder (Quad Dec0 and Quad Dec1) Signals No.
Serial Communications Interface (SCI) Signals 2.10 Serial Communications Interface (SCI) Signals Table 2-14 Serial Communications Interface (SCI0 and SCI1) Signals No. of Pins Signal Name Signal Type State During Reset 1 TXD0 Output Input Transmit Data (TXD0)—SCI0 transmit data output GPIOE0 Input/Output Input Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. Signal Description After reset, the default state is SCI output.
2.12 Analog-to-Digital Converter (ADC) Signals Table 2-16 Analog to Digital Converter Signals No. of Pins Signal Name Signal Type State During Reset 4 ANA0–3 Input Input ANA0–3—Analog inputs to ADC channel 1 4 ANA4–7 Input Input ANA4–7—Analog inputs to ADC channel 2 1 VREF Input Input VREF—Analog reference voltage for ADC. Must be set to VDDA - 0.3V for optimal performance. Signal Description 2.13 Quad Timer Module Signals Table 2-17 Quad Timer Module Signals No.
JTAG/OnCE 2.14 JTAG/OnCE Table 2-18 JTAG/On-Chip Emulation (OnCE) Signals No. of Pins Signal Name Signal Type State During Reset 1 TCK Input (Schmitt) Input, pulled low internally 1 TMS Input Input, pulled Test Mode Select Input—This input pin is used to sequence the (Schmitt) high internally JTAG TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor.
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged. Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. The 56F805 DC/AC electrical specifications are preliminary and are from design simulations.
General Characteristics Table 3-2 Recommended Operating Conditions Characteristic Symbol Min Typ Max Unit Voltage difference VDD to VDDA ΔVDD -0.1 - 0.1 V Voltage difference VSS to VSSA ΔVSS -0.1 - 0.1 V ADC reference voltage VREF 2.7 – VDDA V TA –40 – 85 °C Ambient operating temperature Table 3-3 Thermal Characteristics6 Value Characteristic Comments Symbol Unit Notes 144-pin LQFP Junction to ambient Natural convection Junction to ambient (@1m/sec) RθJA 47.
4. Thermal Characterization Parameter, Psi-JT (ΨJT ), is the “resistance” from junction to reference point thermocouple on top center of case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction temperature in steady-state customer environments. 5.
DC Electrical Characteristics Table 3-4 DC Electrical Characteristics (Continued) Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Symbol Min Typ Max Unit Output Low Voltage (at IOL) VOL — — 0.
180 IDD Analog IDD Digital IDD Total 150 IDD (mA) 120 90 60 30 0 20 40 60 80 Freq. (MHz) Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Figure 3-14) 3.3 AC Electrical Characteristics Timing waveforms in Section 3.3 are tested using the VIL and VIH levels specified in the DC Characteristics table. In Figure 3-2 the levels of VIH and VIL for an input signal are shown.
Flash Memory Characteristics Data2 Valid Data1 Valid Data1 Data3 Valid Data2 Data3 Data Tri-stated Data Invalid State Data Active Data Active Figure 3-3 Signal States 3.4 Flash Memory Characteristics Table 3-5 Flash Memory Truth Table Mode XE1 YE2 SE3 OE4 PROG5 ERASE6 MAS17 NVSTR8 Standby L L L L L L L L Read H H H H L L L L Word Program H H L L H L L H Page Erase H L L L L H L H Mass Erase H L L L L H H H 1.
Table 3-7 Flash Timing Parameters Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.
Flash Memory Characteristics IFREN XADR XE Tadh YADR YE DIN Tads PROG Tnvs Tprog Tpgh NVSTR Tpgs Tnvh Trcv Thv Figure 3-4 Flash Program Cycle IFREN XADR XE YE=SE=OE=MAS1=0 ERASE Tnvs NVSTR Tnvh Terase Trcv Figure 3-5 Flash Erase Cycle 56F805 Technical Data, Rev.
IFREN XADR XE MAS1 YE=SE=OE=0 ERASE Tnvs NVSTR Tnvh1 Tme Trcv Figure 3-6 Flash Mass Erase Cycle 3.5 External Clock Operation The 56F805 system clock can be derived from a crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins. 3.5.
External Clock Operation as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as determined by the following equation: CL1 * CL2 CL = CL1 + CL2 12 * 12 + Cs = + 3 = 6 + 3 = 9pF 12 + 12 This is the value load capacitance that should be used when selecting a crystal and determining the actual frequency of operation of the crystal oscillator circuit.
3.5.3 External Clock Source The recommended method of connecting an external clock is given in Figure 3-9. The external clock source is connected to XTAL and the EXTAL pin is grounded. 56F805 XTAL EXTAL External Clock VSS Figure 3-9 Connecting an External Clock Signal Table 3-8 External Clock Operation Timing Requirements3 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.
External Clock Operation 3.5.4 Phase Locked Loop Timing Table 3-9 PLL Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C Characteristic Symbol Min Typ Max Unit fosc 4 8 10 MHz fout/2 40 — 110 MHz PLL stabilization time 3 0o to +85oC tplls — 1 10 ms PLL stabilization time3 -40o to 0oC tplls — 100 200 ms External reference crystal frequency for the PLL1 PLL output frequency2 1.
3.6 External Bus Asynchronous Timing Table 3-10 External Bus Asynchronous Timing 1, 2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Symbol Min Max Unit Address Valid to WR Asserted tAWR 6.5 — ns WR Width Asserted Wait states = 0 Wait states > 0 tWR 7.5 (T*WS)+7.5 — — ns ns WR Asserted to D0–D15 Out Valid tWRD — T + 4.2 ns Data Out Hold Time from WR Deasserted tDOH 4.
External Bus Asynchronous Timing 1. Timing is both wait state- and frequency-dependent. In the formulas listed, WS = the number of wait states and T = Clock Period. For 80MHz operation, T = 12.5ns. 2. Parameters listed are guaranteed by design. To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula: Top = Clock period @ desired operating frequency WS = Number of wait states Memory Access Time = (Top*WS) + (Top- 11.
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 6 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.
Reset, Stop, Wait, Mode Select, and Interrupt Timing RESET tRA tRAZ tRDA A0–A15, D0–D15 First Fetch PS, DS, RD, WR First Fetch Figure 3-12 Asynchronous Reset Timing IRQA IRQB tIRW Figure 3-13 External Interrupt Timing (Negative-Edge-Sensitive) A0–A15, PS, DS, RD, WR First Interrupt Instruction Execution tIDM IRQA, IRQB a) First Interrupt Instruction Execution Purpose I/O Pin tIG IRQA, IRQB b) General Purpose I/O Figure 3-14 External Level-Sensitive Interrupt Timing 56F805 Technical Data, R
IRQA, IRQB tIRI A0–A15, PS, DS, RD, WR First Interrupt Vector Instruction Fetch Figure 3-15 Interrupt from Wait State Timing tIW IRQA tIF A0–A15, PS, DS, RD, WR First Instruction Fetch Not IRQA Interrupt Vector Figure 3-16 Recovery from Stop State Using Asynchronous Interrupt Timing tIRQ IRQA tII A0–A15 PS, DS, RD, WR First IRQA Interrupt Instruction Fetch Figure 3-17 Recovery from Stop State Using IRQA Interrupt Service RSTO tRSTO Figure 3-18 Reset Output Timing 56F805 Technical Data, Rev.
Serial Peripheral Interface (SPI) Timing 3.8 Serial Peripheral Interface (SPI) Timing Table 3-12 SPI Timing1 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz Characteristic Symbol Cycle time Master Slave Min Max Unit See Figure 50 25 — — ns ns Figures 3-19, 3-20, 3-21, 3-22 — 25 — — ns ns — 100 — — ns ns 17.6 12.5 — — ns ns 24.
SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tR tCL SCLK (CPOL = 1) (Output) tDH tDS tCH MISO (Input) tCH MSB in Bits 14–1 tDI(ref) tDV tDI MOSI (Output) LSB in Master MSB out Bits 14–1 Master LSB out tR tF Figure 3-19 SPI Master Timing (CPHA = 0) SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH MISO (Input) MSB in tDH Bits 14–1 tDI tDV(ref) MOSI (Output) tDS tR Ma
Serial Peripheral Interface (SPI) Timing SS (Input) tC tF tR tCL SCLK (CPOL = 0) (Input) tELG tCH tELD tCL SCLK (CPOL = 1) (Input) tA tCH MISO (Output) Slave MSB out tDS tDH MOSI (Input) MSB in tF tR tD Bits 14–1 Slave LSB out tDV tDI Bits 14–1 tDI LSB in Figure 3-21 SPI Slave Timing (CPHA = 0) SS (Input) tF tC tR tCL SCLK (CPOL = 0) (Input) tCH tELG tELD SCLK (CPOL = 1) (Input) tCL tDV tA MISO (Output) tF tCH Slave MSB out tR Bits 14–1 tDV tDS tD Slave LSB out tDI t
3.9 Quad Timer Timing Table 3-13 Timer Timing1, 2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz Characteristic Symbol Min Max Unit PIN 4T+6 — ns Timer input high/low period PINHL 2T+3 — ns Timer output period POUT 2T — ns POUTHL 1T — ns Timer input period Timer output high/low period 1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns. 2. Parameters listed are guaranteed by design.
Serial Communication Interface (SCI) Timing PPH PPH PPH PPH Phase A (Input) PIN PHL PHL Phase B (Input) PIN PHL PHL Figure 3-24 Quadrature Decoder Timing 3.11 Serial Communication Interface (SCI) Timing Table 3-15 SCI Timing4 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz Characteristic Symbol Min Max Unit BR — (fMAX*2.5)/(80) Mbps RXD2 Pulse Width RXDPW 0.965/BR 1.04/BR ns TXD3 Pulse Width TXDPW 0.965/BR 1.
TXD SCI receive data pin (Input) TXDPW Figure 3-26 TXD Pulse Width 3.12 Analog-to-Digital Converter (ADC) Characteristics Table 3-16 ADC Characteristics Characteristic Symbol Min Typ Max Unit VADCIN 01 — VREF2 V Resolution RES 12 — 12 Bits Integral Non-Linearity3 INL — +/-2.5 +/-4 LSB4 Differential Non-Linearity DNL — +/- 0.9 +/-1 LSB4 ADC input voltages Monotonicity GUARANTEED ADC internal clock5 fADIC 0.
Controller Area Network (CAN) Timing Table 3-16 ADC Characteristics (Continued) Characteristic Symbol Min Typ Max Unit ADC Quiescent Current (both ADCs) IADC — 50 — mA VREF Quiescent Current (both ADCs) IVREF — 12 16.5 mA 1. For optimum ADC performance, keep the minimum VADCIN value > 25mV. Inputs less than 25mV may convert to a digital output code of 0. 2. VREF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF to VDDA-0.3V. 3. .
MSCAN_RX CAN receive data pin (Input) T WAKEUP Figure 3-28 Bus Wakeup Detection 3.14 JTAG Timing Table 3-18 JTAG Timing1, 3 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz Characteristic Symbol Min Max Unit TCK frequency of operation2 fOP DC 10 MHz TCK cycle time tCY 100 — ns TCK clock pulse width tPW 50 — ns TMS, TDI data set-up time tDS 0.4 — ns TMS, TDI data hold time tDH 1.
JTAG Timing TCK (Input) tDS TDI TMS (Input) tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) tDV TDO (Output) Output Data Valid Figure 3-30 Test Access Port Timing Diagram TRST (Input) tTRST Figure 3-31 TRST Timing Diagram DE tDE Figure 3-32 OnCE—Debug Event 56F805 Technical Data, Rev.
Part 4 Packaging 4.1 Package and Pin-Out Information 56F805 EXTBOOT RESET DE CLKO TD0 TD1 VDD TD2 VSS EXTAL XTAL ANA7 ANA6 ANA5 ANA4 GPIOB3 VDD GPIOB2 PHASEB0 GPIOB1 PHASEA0 GPIOB0 VSS VDD VDD VDDA VSSA RXD0 TXD0 PWMA5 PWMA4 GPIOD2 PWMA3 GPIOD1 PWMA2 GPIOD0 PWMA1 GPIOB7 PWMA0 GPIOB6 HOME0 GPIOB5 INDEX0 GPIOB4 VSS This section contains package and pin-out information for the 144-pin LQFP configuration of the 56F805.
Package and Pin-Out Information 56F805 Table 4-1 56F805 Pin Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
Table 4-1 56F805 Pin Identification by Pin Number (Continued) Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name 31 FAULTB1 67 FAULTA3 103 PWMA3 139 D4 32 A12 68 VREF 104 GPIOD2 140 D5 33 A13 69 ANA0 105 PWMA4 141 D6 34 VDD 70 ANA1 106 PWMA5 142 D7 35 PS 71 ANA2 107 TXD0 143 D8 36 DS 72 ANA3 108 RXD0 144 D9 56F805 Technical Data, Rev.
Package and Pin-Out Information 56F805 Figure 4-2 144-pin LQFP Mechanical Information Please see www.freescale.com for the most current case outline. 56F805 Technical Data, Rev.
Part 5 Design Considerations 5.
Electrical Design Considerations • Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case determined by a thermocouple. The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package.
• • Because the processor’s output signals have fast rise and fall times, PCB trace lengths should be minimal. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits. • Take special care to minimize noise levels on the VREF, VDDA and VSSA pins.
Electrical Design Considerations Part 6 Ordering Information Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 6-1 56F805 Ordering Information Part Supply Voltage 56F805 3.0–3.6 V 56F805 3.0–3.
56F805 Technical Data, Rev.
Electrical Design Considerations 56F805 Technical Data, Rev.
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