Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal HVQFN 56

1. General description

The ADC1213D is a dual-channel 12-bit Analog-to-Digital Converter (ADC) optimized for

high dynamic performance and low power at sample rates up to 125 Msps. Pipelined

architecture and output error correction ensure the ADC1213D is accurate enough to

guarantee zero missing codes over the entire operating range. Supplied from a 3 V

source for analog and a 1.8 V source for the output driver, it embeds two serial outputs.

Each lane is differential and complies with the JESD204A standard. An integrated Serial

Peripheral Interface (SPI) allows the user to easily configure the ADC. A set of IC

configurations is also available via the binary level control pins taken, which are used at

power-up. The device also includes a programmable full-scale SPI to allow flexible input

voltage range of 1 V to 2 V (peak-to-peak).

Excellent dynamic performance is maintained from the baseband to input frequencies of

170 MHz or more, making the ADC1213D ideal for use in communications, imaging, and

medical applications.

2. Features and benefits

ADC1213D series

Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;

serial JESD204A interface

Rev. 7 — 9 June 2011 Product data sheet

 SNR, 70 dBFS; SFDR, 86 dBc  Input bandwidth, 600 MHz

 Sample rate up to 125 Msps  Power dissipation, 995 mW at 80 Msps

 Clock input divided by 2 for less jitter

contribution

 SPI register programming

 3 V, 1.8 V single supplies  Duty cycle stabilizer (DCS)

 Flexible input voltage range:

1V(p-p)to2V(p-p)

 High IF capability

 Two configurable serial outputs  Offset binary, two’s complement, gray

code

 Compliant with JESD204A serial

transmission standard

 Power-down mode and Sleep mode

 Pin compatible with the

ADC1613D series, ADC1413D series,

and ADC1113D125

 HVQFN56 package

Summary of content (42 pages)

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ADC1213D series Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A interface Rev. 7 — 9 June 2011 Product data sheet 1. General description The ADC1213D is a dual-channel 12-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low power at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1213D is accurate enough to guarantee zero missing codes over the entire operating range.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface 3. Applications  Wireless and wired broadband communications  Spectral analysis  Ultrasound equipment  Portable instrumentation  Imaging systems  Software defined radio 4. Ordering information Table 1.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface 5.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface 6. Pinning information 43 SYNCP 44 SYNCN 45 DGND 46 VDDD 47 SWING_0 48 SWING_1 49 DNC 50 VDDA 51 AGND 52 AGND 53 VDDA 54 SENSE 55 VREF 56 VDDA 6.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface ADC1213D_SER Product data sheet Table 2.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Table 2. Pin description …continued Symbol Pin Type [1] Description VDDA 53 P analog power supply 3 V SENSE 54 I reference programming pin VREF 55 I/O voltage reference input/output VDDA 56 P analog power supply 3 V [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. [2] OTRA stands for “OuT of Range” A. OTRB stands for “OuT of Range” B 7. Limiting values Table 3.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Table 5. Static characteristics[1] …continued Symbol Parameter Conditions Min Typ Max Unit P power dissipation Power-down mode - 30 - mW Standby mode - 200 - mW Clock inputs: pins CLKP and CLKM (AC-coupled) Low-Voltage Positive Emitter-Coupled Logic (LVPECL) Vi(clk)dif differential clock input voltage peak-to-peak - 0.8 - V differential clock input voltage peak-to-peak 0.8 1.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Table 5. Symbol Static characteristics[1] …continued Parameter Conditions Min Typ Max Unit output 0.5 - 1 V input 0.5 - 1 V - pin AGND; VVREF; VDDA - V Reference voltage input/output: pin VREF VVREF voltage on pin VREF Reference mode selection: pin SENSE VSENSE voltage on pin SENSE Data outputs: pins CMLPA, CMLNA Output levels, VDDD = 1.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Table 5. Static characteristics[1] …continued Symbol Parameter MG(CTC) channel-to-channel gain matching Conditions Min Typ Max Unit - 1.1 - % - 54 - dB Supply PSRR [1] power supply rejection ratio 200 mV (p-p) on pin VDDA; fi = DC Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 C.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface 10.3 Serial output timing The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions are: • 3.125 Gbps data rate • Tamb = 25 °C • DC coupling with two different receiver common-mode voltages 005aaa088 Fig 3. Eye diagram at 1 V receiver common-mode 005aaa089 Fig 4.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface 10.4 SPI timing Table 8.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface package ESD parasitics switch INAP INBP Ron = 15 Ω 1, 14 4 pF Cs internal clock switch INAM INBM Ron = 15 Ω 2, 13 4 pF Cs internal clock 005aaa069 Fig 6. Input sampling circuit The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Table 9. RC coupling versus input frequency - typical values Input frequency (MHz) Resistance () Capacitance (pF) 3 25 12 70 12 8 170 12 8 11.1.3 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 8 would be suitable for a baseband application.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface 11.2 System reference and power management 11.2.1 Internal/external reference The ADC1213D has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pin VREF and SENSE (see Figure 11 to Figure 14), in 1 dB steps between 0 dB and 6 dB, via SPI control bits INTREF[2:0] (when bit INTREF_EN = logic 1; see Table 21).
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Figure 11 to Figure 14 illustrate how to connect the SENSE and VREF pins to select the required reference voltage source. VREF VREF 330 pF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE 005aaa116 005aaa117 Fig 11. Internal reference, 2 V (p-p) full-scale Fig 12. Internal reference, 1 V (p-p) full-scale VREF VREF V 0.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface PACKAGE ESD PARASITICS COMMON MODE REFERENCE 1.5 V VCMA VCMB 0.1 μF ADC CORE 005aaa077 Fig 15. Reference equivalent schematic 11.2.4 Biasing The common-mode output voltage, VO(cm), should be set externally to 1.5 V (typical). The common-mode input voltage, VI(cm), at the inputs to the sample-and-hold stage (pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal performance. 11.3 Clock input 11.3.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Sine clock input CLKP Sine clock input CLKP CLKM CLKM 005aaa054 005aaa173 a. Sine clock input b. Sine clock input (with transformer) CLKP LVPECL clock input CLKM 005aaa172 c. LVPECL clock input Fig 17. Differential clock input 11.3.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 18.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Single-ended or differential clock inputs can be selected via the SPI (see Table 20). If single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting bit SE_SEL accordingly, the unused pin should be connected to ground via a capacitor. 11.3.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface VDDD 50 Ω CMLPA/CMLPB 10 nF CMLNA/CMLNB − + 100 Ω RECEIVER 10 nF 12 mA to 26 mA 005aaa083 Fig 20. CML output connection to the receiver (AC-coupled) 11.5 JESD204A serializer For more information about the JESD204A standard refer to the JEDEC web site. 11.5.1 Digital JESD204A formatter The block placed after the ADC cores is used to implement all functionalities of the JESD204A standard.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface ADC_MODE[1:0] PRBS DUMMY SCR_IN_MODE[1:0] 11 12 + 1 10 N 12 + 1 AND CS 8 N + CS PLL AND DLL ADC B 12 + 1 frame CLK ×F character CLK 12 + 1 01 10 00 '0' 01 '0/1' 10 PRBS 11 FSM (frame assembly character replication ILA test mode) FRAME ASSEMBLY bit CLK PRBS 11 '0/1' 10 '0' 01 SER 00 PRBS 12 + 1 10 N 12 + 1 AND CS 01 8-bit/ 10-bit SCR N + CS 8 11 PRBS SER SWING_SEL[2:0] ADC_PD DUMMY
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Table 13. Output codes versus input voltage …continued INP  INM (V) Offset binary Two’s complement OTR +0.9985352 1111 1111 1100 0111 1111 1100 0 +0.9990234 1111 1111 1101 0111 1111 1101 0 +0.9995117 1111 1111 1110 0111 1111 1110 0 +1.0000000 1111 1111 1111 0111 1111 1111 0 > +1 1111 1111 1111 0111 1111 1111 1 11.6 Serial Peripheral Interface (SPI) 11.6.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface The steps for a data transfer: 1. The falling edge on pin CS in combination with a rising edge on pin SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but is always be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes) 4.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface 11.6.3 Register description 11.6.3.1 ADC control register Table 18. Register Channel index (address 0003h) Default values are highlighted. Bit Symbol Access Value Description 7 to 2 not used - 111111 not used 1 ADCB R/W 0 ADCA ADC B gets the next SPI command: 0 ADC B not selected 1 ADC B selected R/W ADC A gets the next SPI command: 0 ADC A not selected 1 ADC A selected Table 19.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Table 20. Register Clock (address 0006h) …continued Default values are highlighted. Bit Symbol Access 0 DCS_EN R/W Value Description duty cycle stabilizer enable: 0 disable 1 active Table 21. Register Vref (address 0008h) Default values are highlighted.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Table 23. Register Test pattern 1 (address 0014h) Default values are highlighted. Bit Symbol Access Value 7 to 3 - - 00000 2 to 0 TESTPAT_1[2:0] R/W Description not used digital test pattern: 000 off 001 mid-scale 010  FS 011 + FS 100 toggle ‘1111..1111’/’0000..0000’ 101 custom test pattern, to be written in register 0015h and 0016h 110 ‘010101...’ 111 ‘101010...’ Table 24.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Table 28. Ser_Cfg_Setup (address 0803h) Default values are highlighted. Bit Symbol Access Value Description 7 to 4 - - not used 3 to 0 CFG_SETUP[3:0] R/W Table 29. 0000 quick configuration of JESD204A. These settings overrule the CFG_PAD configuration (see Table 29).
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Table 30. Ser_Control1 (address 0805h) Default values are highlighted. Bit Symbol 7 6 5 4 Access Value Description - - 0 not used TRISTATE_CFG_PINS R/W 1 pins CFG3 to CFG0 are set to high-impedance. Switch to 0 automatically after start-up or reset.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Table 33. Ser_ScramblerA (address 0809h) Default values are highlighted. Bit Symbol Access Value Description 7 - - 0 not used 6 to 0 LSB_INIT[6:0] R/W 0000000 defines the initialization vector for the scrambler polynomial (lower) Table 34. Ser_ScramblerB (address 080Ah) Default values are highlighted.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Table 40. Cfg_5_K (address 0824h) Default values are highlighted. Bit Symbol Access Value Description 7 to 5 - - 000 not used 4 to 0 K[4:0] R/W 01000 defines the number of frames per multiframe, minus 1 Table 41. Cfg_6_M (address 0825h) Default values are highlighted.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Table 47. Cfg_02_2_LID (address 082Dh) Default values are highlighted. Bit Symbol Access Value Description 7 to 5 - 4 to 0 LID[4:0] - 000 not used R/W 11100 defines lane 1 identification number Table 48. Cfg01_13_FCHK (address 084Ch) Default values are highlighted.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Table 50. Lane0_0_Ctrl (address 0870h) …continued Default values are highlighted. Bit Symbol Access 0 LANE_PD R/W Value Description lane power-down control: 0 lane is operational 1 lane is in Power-down mode Table 51. Lane1_0_Ctrl (address 0871h) Default values are highlighted.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Table 52. ADCA_0_Ctrl (address 0890h) …continued Default values are highlighted. Bit Symbol 3 to 1 - 0 ADC_PD Access Value Description 000 not used R/W ADC power-down control: 0 ADC is operational 1 ADC is in Power-down mode Table 53. ADCB_0_ctrl (address 0891h) Default values are highlighted.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface 12. Package outline HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm A B D SOT684-7 terminal 1 index area A E A1 c detail X e1 e 1/2 e L 15 28 14 C C A B C v w b y1 C y 29 e e2 Eh 1/2 e 1 42 terminal 1 index area 56 43 X Dh 0 2.5 scale Dimensions Unit A(1) A1 b max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface 13. Abbreviations Table 54.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface 14. Revision history Table 55. Revision history Document ID Release date Data sheet status Change notice Supersedes ADC1213D_SER v.7 20110609 - ADC1213D_SER v.6 Modifications: • Product data sheet Section 10.2 “Clock and digital output timing” has been updated. ADC1213D_SER v.6 20110209 Product data sheet - ADC1213D_SER v.5 ADC1213D_SER v.5 20100423 Preliminary data sheet - ADC1213D_SER v.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.
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ADC1213D series NXP Semiconductors Dual 12-bit ADC; serial JESD204A interface 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.