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MVME2600 Series

Single Board Computer

Installation and Use

V2600A/IH3

July 2001 Edition

Summary of content (198 pages)

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MVME2600 Series Single Board Computer Installation and Use V2600A/IH3 July 2001 Edition
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© Copyright 1998, 2001 Motorola, Inc. All rights reserved. Printed in the United States of America. Motorola® and the Motorola symbol are registered trademarks of Motorola, Inc. AIX® is a registered trademark of International Business Machines Corporation. PowerPC® is a registered trademark of International Business Machines. SNAPHAT®, TIMEKEEPER®, and ZEROPOWER® are registered trademarks of STMicroelectronics.
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Safety Summary The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment. The safety precautions listed below represent warnings of certain dangers of which Motorola is aware.
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Flammability All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. EMI Caution ! Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection. Lithium Battery Caution This product contains a lithium battery to power the clock and calendar circuitry.
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CE Notice (European Community) Motorola Computer Group products with the CE marking comply with the EMC Directive (89/336/EEC). Compliance with this directive implies conformity to the following European Norms: EN55022 “Limits and Methods of Measurement of Radio Interference Characteristics of Information Technology Equipment”; this product tested to Equipment Class B EN50082-1:1997 “Electromagnetic Compatibility—Generic Immunity Standard, Part 1.
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Limited and Restricted Rights Legend If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov. 1995) and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252.
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Contents About This Manual Summary of Changes ...............................................................................................xviii Overview of Contents ..............................................................................................xviii Comments and Suggestions .......................................................................................xix Conventions Used in This Manual..............................................................................
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MVME712M Transition Module Installation .................................................. 1-44 MVME761 Transition Module Installation...................................................... 1-48 System Considerations ............................................................................................ 1-50 MVME2603/2604 VME Module ..................................................................... 1-51 CHAPTER 2 Operating Instructions Introduction ..................................................
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Disk Drive Controller ................................................................................3-10 Keyboard and Mouse Interface..................................................................3-10 PCI-ISA Bridge (PIB) Controller .....................................................................3-10 Real-Time Clock/NVRAM/Timer Function .....................................................3-11 Programmable Timers......................................................................................
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Ethernet AUI Connector................................................................................... 4-24 MVME761-Compatible Versions ............................................................................ 4-25 VMEbus Connector P2..................................................................................... 4-25 Serial Ports 1 and 2........................................................................................... 4-26 Serial Ports 3 and 4............................................
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APPENDIX C Troubleshooting CPU Boards: Solving Startup Problems Introduction............................................................................................................... C-1 APPENDIX D Related Documentation Motorola Computer Group Documents ....................................................................D-1 Manufacturers’ Documents.......................................................................................D-2 Related Specifications........................................
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List of Figures Figure 1-1. MVME2603/2604 Base Board Block Diagram ......................................1-2 Figure 1-2. MVME2603/2604 Switches, Headers, Connectors, Fuses, LEDs ..........1-9 Figure 1-3. MVME712M Connector and Header Locations ...................................1-16 Figure 1-4. J15 Clock Line Configuration ...............................................................1-17 Figure 1-5. MVME712M Serial Port 1 DCE/DTE Configuration ..........................1-18 Figure 1-6.
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List of Tables Table 1-1. Startup Overview ......................................................................................1-3 Table 1-2. MVME712M Port/Jumper Correspondence...........................................1-17 Table 2-1. Processor Default View of the Memory Map ...........................................2-6 Table 2-2. PCI Arbitration Assignments..................................................................2-10 Table 2-3. IBC DMA Channel Assignments ......................................
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Table B-2. EIA-232-D Interface Transmitter Characteristics ................................. B-5 Table B-3. EIA-232-D Interface Receiver Characteristics ...................................... B-5 Table B-4. MVME761 EIA-530 Interconnect Signals ............................................ B-6 Table B-5. EIA-530 Interface Transmitter Characteristics ..................................... B-8 Table B-6. EIA-530 Interface Receiver Characteristics .......................................... B-9 Table C-1.
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About This Manual This manual provides general information, hardware preparation and installation instructions, operating instructions, and a functional description of the MVME2603/2604 family of single board computers.
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Summary of Changes This is the third edition of the Installation and Use manual. It supersedes the May 1998 edition and incorporates the following updates. Date Changes Replaces July 2001 All data referring to the VME CSR Bit Set Register (VCSR_SET) and VME CSR Bit Clear Register (VCSR_CLR) has been deleted. These registers of the Universe II are unavailable for implementation as intended by the MVME materials and the Universe II User Manual.
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Appendix A, Specifications, lists the general specifications for MVME2603/2604 base boards. Appendix B, Serial Interconnections, describes the MVME2603/2604 serial communications interfaces. Appendix C, Troubleshooting CPU Boards: Solving Startup Problems, supplies the user with troubleshooting tips before having to call for help. Appendix D, Related Documentation, lists all documentation related to the MVME2603/2604 single board computer.
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Conventions Used in This Manual The following typographical conventions are used in this document: bold is used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories and files. italic is used for names of variables to which you assign values. Italic is also used for comments in screen displays and examples, and to introduce new terms.
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1Hardware Preparation and Installation 1 Introduction The MVME2603/2604 is a single-slot VME module equipped with a PowerPC® Series microprocessor. The MVME2603 is equipped with a PowerPC 603™ microprocessor; the MVME2604 has a PowerPC 604™ microprocessor. 256KB L2 cache (level 2 secondary cache memory) is available as an option on all versions.
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Hardware Preparation and Installation 66MHz MPC604 PROCESSOR BUS DEBUG CONNECTOR L2 CACHE 256K PROCESSOR MPC603/604 PHB & MPIC RAVEN ASIC MEMORY EXPANSION CONNECTORS FLASH 4MB or 8MB FLASH 1MB SYSTEM REGISTERS MEMORY CONTROLLER FALCON CHIPSET PCI EXPANSION CLOCK GENERATOR 64-BIT PMC SLOT 33MHz 32/64-BIT PCI LOCAL BUS FLOPPY & LED PIB W83C553 ISA REGISTERS ETHERNET DEC21140 SCSI 53C825A VME BRIDGE UNIVERSE BUFFERS RTC/NVRAM/WD MK48T59 KBD ISA BUS AUI/10BT/100BTX FRONT PANEL ESCC 8523
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Equipment Required Equipment Required The following equipment is required to complete an MVME2603/2604 system: ❏ VME system enclosure ❏ System console terminal ❏ Operating system (and/or application software) ❏ Disk drives (and/or other I/O) and controllers ❏ Transition module (MVME712M or MVME761) and connecting cables MVME2603/2604 VME modules are factory-configured for I/O handling via either MVME712M or MVME761 transition modules.
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1 Hardware Preparation and Installation Table 1-1. Startup Overview (Continued) What you need to do... Refer to... Install the transition module in the chassis. MVME712M Transition Module Installation on page 1-44 or MVME761 Transition Module Installation on page 1-48 Connect a console terminal. System Considerations on page 1-50, MVME2603/2604 VME module Connect any other equipment you will be using. Chapter 4, Connector Pin Assignments Power up the system.
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Unpacking Instructions Unpacking Instructions Note If the shipping carton is damaged upon receipt, request that the carrier’s agent be present during the unpacking and inspection of the equipment. Unpack the equipment from the shipping carton. Refer to the packing list and verify that all items are present. Save the packing material for storing and reshipping of equipment. ! Avoid touching areas of integrated circuitry; static discharge can damage circuits.
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1 Hardware Preparation and Installation MVME2603/2604 Base Board Preparation Figure 1-2 on page 1-9 illustrates the placement of the switches, jumper headers, connectors, and LED indicators on the MVME2603/2604.
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MVME2603/2604 Base Board Preparation Cache Mode Control (J3) 256KB of L2 cache memory is available on the MVME2603/2604. L2 cache operation is transparent to users, but its write-through mode is configurable via header J3 on older boards. On newer MVME2603/2604 boards, header J3 is not provided. With a jumper installed on J3, cache write-through is under CPU control. With the jumper removed, cache write-through occurs in all cases.
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1 Hardware Preparation and Installation Serial Port 4 Receive Clock Configuration (J16) In synchronous serial communications, you can configure Serial Port 4 on the MVME2603/2604 to use the clock signals provided by the RxC signal line. On MVME712M-compatible versions of the base board, header J16 configures port 4 to either drive or receive RxC. The factory configuration has port 4 set to receive RxC. J16 remains open on MVME761-compatible versions.
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MVME2603/2604 Base Board Preparation 2 1 J3 J2 A1 B1 C1 D1 J1 25 24 49 50 ABT P1 CHS J4 FLOPPY/LED RST BFL CPU PCI 1 2 26 27 FUS SYS A32 B32 C32 D32 XU1 J7 6 J5 5 XU2 J6 4 2 1 3 KEYBOARD 6 J8 4 2 1 3 5 MOUSE A1 B1 C1 D1 2 1 2 1 J12 J11 2 1 P2 J9 2 1 2 1 16 15 PCI MEZZANINE CARD J14 J13 64 J15 J23 J16 J17 J18 J20 A32 B32 C32 D32 64 11517.00 9608 J10 J22 Figure 1-2. MVME2603/2604 Switches, Headers, Connectors, Fuses, LEDs http://www.motorola.
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1 Hardware Preparation and Installation Serial Port 4 Transmit Clock Configuration (J17) In synchronous serial communications, you can configure Serial Port 4 on the MVME2603/2604 to use the clock signals provided by the TxC signal line. Header J17 configures port 4 to either drive or receive TxC. The factory configuration has port 4 set to receive TxC.
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MVME2603/2604 Base Board Preparation Serial Port 4 Transmit Clock Receiver Buffer Control (J20) As described in other sections, a complete configuration of Serial Port 4 requires that you set the following jumper headers on the MVME2603/2604 or the transition module: ❏ J16 (Serial Port 4 receive clock configuration) on MVME712Mcompatible versions of the base board ❏ J17 (Serial Port 4 transmit clock configuration) ❏ J20 (Serial Port 4 transmit clock receiver buffer control) on MVME712M-compatible vers
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1 Hardware Preparation and Installation For additional details on the configuration of those headers, refer to MVME712M Transition Module Preparation on page 1-14, MVME761 Transition Module Preparation on page 1-25, or to the respective user’s manuals for the transition modules (listed in Appendix D, Related Documentation) as necessary.
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MVME2603/2604 Base Board Preparation For additional details on the configuration of the MVME761 headers, refer to MVME761 Transition Module Preparation on page 1-25 or to the user’s manual for the module (listed in Appendix D, Related Documentation). J18 J18 3 3 2 2 1 1 Drive TxC Receive TxC (factory configuration) System Controller Selection (J22) The MVME2603/2604 is factory-configured as a VMEbus system controller by jumper header J22.
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1 Hardware Preparation and Installation Remote Status and Control The MVME2603/2604 front panel LEDs and switches are mounted on a removable mezzanine board. Removing the LED mezzanine makes the mezzanine connector (J1, a keyed double-row 14-pin connector) available for service as a remote status and control connector. In this application, J1 can be connected to a user-supplied external cable to carry the Reset and Abort signals and the LED lines to a control panel located apart from the MVME2603/2604.
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MVME712M Transition Module Preparation ❏ Socket-mounted SCSI terminating resistors for end-of-cable or middle-of-cable configurations ❏ Fused SCSI terminator power developed from the +5VDC present at connector P2 ❏ A 64-pin DIN connector to interface the EIA-232-D, parallel, SCSI, and Ethernet signals to the MVME712M http://www.motorola.
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Hardware Preparation and Installation 1 MVME712M J14 J20 1 2 19 20 J17 1 J19 J21 14 J11 13 6 DS1 8 15 DS2 J6 ETHERNET SCSI INTERFACE PRIMARY SIDE 13 14 14 2 J18 13 1 13 1 14 2 14 2 J16 13 1 14 2 14 2 J13 12 11 J8 J10 1 14 1 14 13 1 14 2 13 1 J15 2 1 13 25 13 25 2 J1 13 1 J7 J9 1 14 1 14 1 2 1 13 25 13 25 SERIAL PORT 2 / TTY01 SERIAL PORT 4 R50 C2 J2 1 C3 8 A32 C32 1 J4 2 1 R51 50 J3 8 49 C1 8 49 R49 2 1 50 18 36 1 19 1 A1 C1 1 9 PRINTER
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MVME712M Transition Module Preparation Serial Ports 1-4 DCE/DTE Configuration Serial ports 1 through 4 are configurable as modems (DCE) for connection to terminals, or as terminals (DTE) for connection to modems. The MVME712M is shipped with the serial ports configured for DTE operation. Serial port DCE/DTE configuration is accomplished by positioning jumpers on one of two headers per port. The following table lists the serial ports with their corresponding jumper headers. Table 1-2.
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1 Hardware Preparation and Installation MVME2603/2604 P2 ADAPTER BOARD 64-PIN CABLE MVME712M MODULE DB9 PC87308 RXD 3 SOUT1 CTS RTS1# DTR1# NC DCD +12V 5 8 TXD SIN1 2 DCE RTS CTS1# 4 DSR DCD1# 6 +12V GND DSR1# R11# 7 +5V 11551.00 9609 (1-8) MVME2603/2604 P2 ADAPTER BOARD 64-PIN CABLE MVME712M MODULE DB9 PC87308 TXD 2 SOUT1 RTS RTS1# DTR1# 4 NC +12V DTR 20 RXD SIN1 3 DTE CTS CTS1# 5 DCD1# GND DSR1# R11# 7 +5V 11551.00 9609 (2-8) Figure 1-5.
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MVME712M Transition Module Preparation MVME2603/2604 P2 ADAPTER BOARD 64-PIN CABLE MVME712M MODULE DB9 PC87308 RXD SOUT2 CTS RTS2# DCD DTR2# 3 5 8 TXD SIN2 2 DCE RTS CTS2# 4 DTR DCD2# 20 DSR2# R12# DSR +12V GND +5V 6 7 11551.00 9609 (3-8) MVME2603/2604 P2 ADAPTER BOARD 64-PIN CABLE MVME712M MODULE DB9 PC87308 TXD SOUT2 2 RTS RTS2# 4 DTR DTR2# 20 RXD SIN2 DTE 3 CTS CTS2# 5 DCD DCD2# 8 DSR2# R12# +5V GND 7 11551.00 9609 (4-8) Figure 1-6.
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1 Hardware Preparation and Installation MVME2603/2604 P2 ADAPTER Z85230 64-PIN CABLE MVME712M MODULE DB9 RXD TXDA CTS RTSA# 3 5 DTR DCDA# 20 TXD RXDA 2 RTS CTSA# 4 TRXCA# +5V RTXCA# +5V DCE Z8536 DCD DTR3# 8 LLB3# +5V RLB3# +5V DSR3# DSR R13# +5V +12V 6 GND TM3# 7 +5V NOTE: J18 OPEN 11551.00 9609 (5-8) Figure 1-7.
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MVME712M Transition Module Preparation P2 ADAPTER MVME2603/2604 Z85230 64-PIN CABLE MVME712M MODULE DB25 TXD TXDA RTS RTSA# DCD DCDA# 2 4 8 RXD RXDA 3 CTS CTSA# DTE 5 TRXCA# +5V RTXCA# +5V Z8536 DTR DTR3# LLB3# +5V RLB3# +5V 20 DSR3# R13# +5V TM3# +5V GND 7 NOTE: J18 OPEN 11551.00 9609 (6-8) Figure 1-8. MVME712M Serial Port 3 DTE Configuration http://www.motorola.
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1 Hardware Preparation and Installation MVME2603/2604 P2 ADAPTER Z85230 64-PIN CABLE MVME712M MODULE DB25 RXD TXDB CTS RTSB# 3 5 DTR DCDB# 20 TXD RXDB 2 RTS CTSB# 4 J17 TXCI RXCI TXCO J20 J16 15 17 24 TRXCB RTXCB DCE Z8536 DCD DTR4# LLB4# +5V RLB4# +5V 8 DSR4# DSR R14# +5V +12V 6 GND TM4# 7 +5V NOTE: J20 OPEN J16 1-2 J17 1-2 11551.00 9609 (7-8) Figure 1-9.
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MVME712M Transition Module Preparation MVME2603/2604 P2 ADAPTER Z85230 64-PIN CABLE MVME712M MODULE DB25 TXD TXDB RTS RTSB# DCD DCDB# 2 4 8 RXD RXDB 3 CTS CTSB# 5 J17 TXCI RXCI TXCO J20 J16 15 17 24 TRXCB RTXCB DTE Z8536 DCD DTR4# LLB4# +5V RLB4# +5V 20 DSR4# R14# +5V TM4# +5V GND 7 NOTE: J20 1-2 J16 2-3 J17 2-3 11551.00 9609 (8-8) Figure 1-10. MVME712M Serial Port 4 DTE Configuration http://www.motorola.
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1 Hardware Preparation and Installation P2 Adapter Preparation Preparation of the P2 adapter for the MVME712M consists of removing or installing the SCSI terminating resistors. Figure 1-11 illustrates the location of the resistors, fuse, and connectors. For further information on the preparation of the transition module and the P2 adapter, refer to the user’s manual for the MVME712M (listed in Appendix D, Related Documentation) as necessary.
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MVME761 Transition Module Preparation MVME761 Transition Module Preparation The MVME761 transition module (Figure 1-12) and P2 adapter board are used in conjunction with the MVME2603/2604 base board.
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1 Hardware Preparation and Installation MVME 761-001 COM1 J5 COM2 J6 DTE 1 DCE J2 3 SERIAL 3 60 J1 59 2 1 J7 SERIAL 60 J12 59 2 1 J8 DTE DCE J3 1 3 PARALLEL J4 P2 10/100 BASET J9 1910 9609 Figure 1-12.
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MVME761 Transition Module Preparation Serial Ports 1 and 2 On MVME761-compatible models of the MVME2603/2604 base board, the asynchronous serial ports (Serial Ports 1 and 2) are configured permanently as data circuit-terminating equipment (DCE). The port configuration is illustrated in Figure 1-13 on page 1-29.
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1 Hardware Preparation and Installation Headers J2 and J3 are used to configure Serial Port 3 and Serial Port 4, respectively, in tandem with SIM selection. With the jumper in position 1-2, the port is configured as a DTE. With the jumper in position 2-3, the port is configured as a DCE. The jumper setting of the port should match the configuration of the corresponding SIM module.
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MVME761 Transition Module Preparation MVME2603/2604 MVME761 DB9 DCE SOUT1 3 RTS1# 7 DTR1# 4 SIN1 2 CTS1# 8 DSR1# 6 DCD1# 1 RI1# 9 PC87308 SOUT2 RTS2# DTR2# SIN2 CTS2# P2/P2MX COM1 5 3 7 4 2 8 DSR2# 6 DCD2# 1 RI2# 9 COM2 5 DB9 11552.00 9609 (1-3) Figure 1-13. MVME761 Serial Ports 1 and 2 (DCE Only) http://www.motorola.
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1 Hardware Preparation and Installation MVME761 MVME3600 SERIES Z85230 SCC EIA232-DCE SIM HD26 TXD 3 RTS# 5 RXD 2 CTS# 4 DCD# 20 J2/J3 J15 TRXC 3 2 3 2 1 1 15 17 24 RTXC P2/P2MX DCE Z8536 CIO DTR# 8 LLB# 25 RLB# 22 DSR# 6 RI# 21 TM# 18 7 11552.00 9802 (2-5) Figure 1-14.
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MVME761 Transition Module Preparation MVME3600 SERIES MVME761 Z85230 SCC EIA232-DTE SIM HD26 TXD 2 RTS# 4 RXD 3 CTS# 5 DCD# 8 J15 TRXC J2/J3 3 2 3 1 1 24 2 15 17 RTXC P2/P2MX DTE Z8536 CIO DTR# 20 LLB# 18 RLB# 21 DSR# 6 RI# 22 TM# 25 7 11552.00 9802 (4-5) Figure 1-15. MVME761 Serial Ports 3 and 4 DTE Configuration http://www.motorola.
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1 Hardware Preparation and Installation P2 Adapter Preparation (Three-Row) The P2 adapter for the MVME761 transition module routes the synchronous and asynchronous serial, parallel, and Ethernet signals to the MVME761. The P2 adapter also has a 50-pin female connector (J2) that carries 8-bit SCSI signals from the MVME2603/2604. To run SCSI devices, you may install an additional transition module that is equipped with a SCSI port, such as the MVME712B.
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MVME761 Transition Module Preparation For further information on the preparation of the transition module and the P2 adapter, refer to the user’s manual for the MVME761 (listed in Appendix D, Related Documentation) as necessary. 50 49 J2 2 1 J3 2 1 64 63 C1 1 J1 25 1 R1 9 C5 C6 C4 + 17 C3 C7 R2 U1 C B A C2 CR1 U2 + 32 C B A P1 1933 9610 Figure 1-16.
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1 Hardware Preparation and Installation For further information on the preparation of the transition module and the P2 adapter, refer to the user’s manual for the MVME761 (listed in Appendix D, Related Documentation) as necessary. J1 1 J3 33 2 1 64 63 2 1 64 63 J5 J4 1 25 1 U1 9 C8 + U2 17 U3 25 C9 9 R4 17 + 1 D C B A Z CR1 32 D C B A Z P1 1999 9701 Figure 1-17.
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Hardware Installation Hardware Installation The following sections discuss the placement of mezzanine cards on the MVME2603/2604 base board, the installation of the complete MVME2603/2604 VME module assembly and transition module into a VME chassis, and the system considerations relevant to the installation. Before installing the MVME2603/2604, ensure that the serial ports and all header jumpers are configured as desired.
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1 Hardware Preparation and Installation 1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure. 2. Perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove chassis or system cover(s) as necessary for access to the VME modules.
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Hardware Installation 11661.00 9611 (2-3) Figure 1-18. RAM200 Placement on MVME2603/2604 5. Insert the four short Phillips screws through the holes at the corners of the RAM200, into the standoffs on the MVME2603/2604. Tighten the screws. 6. Reinstall the MVME2603/2604 assembly in its proper card slot. Be sure the module is well seated in the backplane connectors. Do not damage or bend connector pins. 7.
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1 Hardware Preparation and Installation 1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure. 2. Perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove chassis or system cover(s) as necessary for access to the VME modules.
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Hardware Installation 4. Remove the PCI filler from the front panel. 11661.00 9611 (3-3) Figure 1-19. PMC Module Placement on MVME2603/2604 5. Slide the edge connector of the PMC module into the front panel opening from behind and place the PMC module on top of the base board. The four connectors on the underside of the PMC module should then connect smoothly with the corresponding connectors (J11/12/13/14) on the MVME2603/2604. 6.
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1 Hardware Preparation and Installation PMC Carrier Board Installation PCI mezzanine card (PMC) carrier boards mount above the RAM200 mezzanine and (if installed) PMC module on the MVME2603/2604 base board. To install a PMC carrier board for additional PCI expansion, refer to Figure 1-20 and proceed as follows: 1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure. 2.
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Hardware Installation 11661.00 9611 (1-3) Figure 1-20. PMC Carrier Board Placement on MVME2603/2604 5. Remove the LED module screw located at the upper front corner of the base board. Install a short (0.394 inch) standoff in its place. http://www.motorola.
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1 Hardware Preparation and Installation 6. At the other three corners of the base board, install long (0.737 inch) standoffs. 7. Place the PMC carrier board on top of the base board. The connector on the underside of the carrier board should connect smoothly with the corresponding connector J5 (located between P1 and P2) on the MVME2603/2604. 8. Insert the four short Phillips screws through the holes at the corners of the carrier board, into the standoffs on the MVME2603/2604. Tighten the screws. 9.
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Hardware Installation ! Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting. Warning 3. Remove the filler panel from the card slot where you are going to install the MVME2603/2604. – If you intend to use the MVME2603/2604 as system controller, it must occupy the left-most card slot (Slot 1).
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1 Hardware Preparation and Installation 7. If necessary, install an MVME712M or MVME761 transition module and cable it to the MVME2603/2604 as described in the following sections of this document. 8. Replace the chassis or system cover(s), cable peripherals to the panel connectors as appropriate, reconnect the system to the AC or DC power source, and turn the equipment power on. MVME712M Transition Module Installation This section applies to MVME712M-compatible models of the MVME2603/2604 VME module.
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Hardware Installation ! Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting. Warning 3. Remove the filler panel(s) from the appropriate card slot(s) at the front or rear of the chassis. (You may need to shift other modules in the chassis to allow space for the MVME712M, which has a doublewide front panel.) 4. Attach the P2 adapter board to the P2 backplane connector at the slot occupied by the MVME2603/2604 VME module. 5.
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1 Hardware Preparation and Installation 8. Replace the chassis or system cover(s), making sure no cables are pinched. Cable the peripherals to the panel connectors, reconnect the system to the AC or DC power source, and turn the equipment power on. Note 1-46 Not all peripheral cables are provided with the MVME712M; you may need to fabricate or purchase certain cables. (To minimize radiation, Motorola recommends shielded cable for peripheral connections where possible.
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Hardware Installation TERMINATORS INSTALLED T SCSI DEVICE SCSI DEVICE MVME2600 MVME712M J9 J7 P1 50-CONDUCTOR CABLE J10 J8 64-CONDUCTOR CABLE P2 ADAPTER J6 J4 J2 J3 J3 P2 J2 P2 J5 TERMINATORS REMOVED TERMINATORS INSTALLED ENCLOSURE BOUNDARY cb2349301 Figure 1-21. MVME712M/MVME2603/2604 Cable Connections http://www.motorola.
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1 Hardware Preparation and Installation MVME761 Transition Module Installation This section applies to MVME761-compatible models of the MVME2603/2604 VME module. With the MVME2603/2604 installed, refer to Figure 1-22 and proceed as follows to install an MVME761 transition module: 1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure. 2. Perform an operating system shutdown.
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Hardware Installation 4. Attach the P2 adapter board to the P2 backplane connector at the slot occupied by the MVME2603/2604 VME module. MVME761-001 MVME2600/MVME3600 P1 64-CONDUCTOR CABLE P2 ADAPTER J2 P2 P2 P2 J3 ENCLOSURE BOUNDARY 11635.00 9610 Figure 1-22. MVME761/MVME2603/2604 Cable Connections 5. Route the 64-conductor cable furnished with the MVME761 from J3 on the P2 adapter board to P2 on the transition module. Be sure to orient cable pin 1 with connector pin 1.
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1 Hardware Preparation and Installation 6. Secure the MVME761 in the chassis with the screws provided, making good contact with the transverse mounting rails to minimize RF emissions. Note The cabling can be configured in a number of ways to accommodate various device and system configurations. Figure 1-22 shows one possible configuration.
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System Considerations The MVME2603/2604 contains shared onboard DRAM (and, optionally, secondary cache memory) whose base address is software-selectable. Both the onboard processor and offboard VMEbus devices see this local DRAM at base physical address $00000000, as programmed by the firmware. This may be changed via software to any other base address. Refer to the MVME2600 Series Single Board Computer Programmer’s Reference Guide, listed in Appendix D, Related Documentation, for more information.
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1 Hardware Preparation and Installation the 14-pin combined LED-mezzanine/remote-reset connector, J1. The FUS LED (DS5) on the MVME2603/2604 front panel illuminates when all three voltages are available. In MVME712M I/O mode, the MVME2603/2604 supplies SCSI terminator power through a 1A fuse (F1) located on the P2 adapter board. If the fuse is blown, the SCSI device(s) may function erratically or not at all.
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System Considerations 9600 baud is the power-up default for serial ports on MVME2603/2604 boards. After power-up you can reconfigure the baud rate if you wish, using the PPCBug PF (Port Format) command via the command line interface. Whatever the baud rate, some type of hardware handshaking — either XON/OFF or via the RTS/CTS line — is desirable if the system supports it. http://www.motorola.
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2Operating Instructions 2 Introduction This chapter supplies information for use of the MVME2603/2604 family of Single Board Computers in a system configuration. Here you will find the power-up procedure and descriptions of the switches and LEDs, memory maps, and software initialization. Applying Power After you have verified that all necessary hardware preparation has been done, that all connections have been made correctly, and that the installation is complete, you can power up the system.
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Operating Instructions 2 STARTUP SYSTEM INITIALIZATION CONSOLE DETECTION RUN SELFTESTS (IF ENABLED) AUTOBOOT (IF ENABLED) OPERATING SYSTEM 11734.00 9702 Figure 2-1. PPCBug System Startup The MVME2603/2604 front panel has ABORT and RESET switches and six LED (light-emitting diode) status indicators (CHS, BFL, CPU, PCI, FUS, SYS). The switches and LEDs are mounted on an LED mezzanine board that plugs into the base board.
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Applying Power ABORT Switch (S1) 2 When activated by software, the ABORT switch can generate an interrupt signal from the base board to the processor at a user-programmable level. The interrupt is normally used to abort program execution and return control to the debugger firmware located in the MVME2603/2604 ROM and Flash memory. The interrupt signal reaches the processor module via ISA bus interrupt line IRQ8∗.
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Operating Instructions 2 Front Panel Indicators (DS1 – DS6) There are six LEDs on the MVME2603/2604 front panel: CHS, BFL, CPU, PCI, FUS, and SYS. (DS1, yellow). Checkstop; driven by the MPC603/604 status lines on the MVME2603/2604. Lights when a halt condition from the processor is detected. ❏ CHS (DS2, yellow). Board Failure; lights when the BRDFAIL∗ signal line is active. ❏ BFL (DS3, green). CPU activity; lights when the DBB∗ (Data Bus Busy) signal line on the processor bus is active.
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Memory Maps Memory Maps 2 There are three points of view for memory maps: ❏ The mapping of all resources as viewed by the processor (MPU bus memory map) ❏ The mapping of onboard resources as viewed by PCI local bus masters (PCI bus memory map) ❏ The mapping of onboard resources as viewed by VMEbus masters (VMEbus memory map) The following sections give a general description of the MVME2603/2604 memory organization from the above three points of view.
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Operating Instructions 2 Default Processor Memory Map The default processor memory map that is valid at power-up or reset remains in effect until reprogrammed for specific applications. Table 2-1 defines the entire default map ($00000000 to $FFFFFFFF). Table 2-2 further defines the map for the local I/O devices (accessible through the PCI/ISA I/O Space). Table 2-1.
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Memory Maps For detailed processor memory maps, including suggested CHRP- and PREP-compatible memory maps, refer to the MVME2600 Series Single Board Computer Programmer’s Reference Guide, listed in Appendix D, Related Documentation. PCI Local Bus Memory Map The PCI memory map is controlled by the Raven MPU/PCI bus bridge controller ASIC and by the Universe PCI/VME bus bridge ASIC. The Raven and Universe devices adjust system mapping to suit a given application via programmable map decoder registers.
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Operating Instructions 2 Programming Considerations Good programming practice dictates that only one MPU at a time have control of the MVME2603/2604 control registers.
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Programming Considerations PROCESSOR VMEBUS PCI MEMORY 2 ONBOARD MEMORY PROGRAMMABLE SPACE NOTE 2 PCI MEMORY SPACE NOTE 1 VME A24 VME A16 NOTE 3 VME A24 VME A16 NOTE 1 PCI/ISA MEMORY SPACE VME A24 VME A16 PCI I/O SPACE VME A24 VME A16 MPC RESOURCES NOTES: 1. Programmable mapping done by Raven ASIC. 2. Programmable mapping performed via PCI Slave images in Universe ASIC. 3. Programmable mapping performed via Special Slave image (SLSI) in Universe ASIC. 11553.00 9609 Figure 2-2.
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Operating Instructions 2 PCI Arbitration There are seven potential PCI bus masters on the MVME2603/2604 single board computer: ❏ Raven ASIC (MPU/PCI bus bridge controller) ❏ Winbond W83C553 PIB (PCI/ISA bus bridge controller) ❏ DECchip 21140 Ethernet controller ❏ SYM53C825A SCSI controller ❏ Universe ASIC (PCI/VME bus bridge controller) ❏ PMC Slot 1 (PCI mezzanine card) ❏ PMC Slot 2 (PCI expansion) The Winbond W83C553 PIB device supplies the PCI arbitration support for these seven types of d
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Programming Considerations Interrupt Handling 2 The Raven ASIC, which controls PHB (PCI Host Bridge) MPU/local bus interface functions on the MVME2603/2604, performs interrupt handling as well.
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Operating Instructions 2 INT INT_ PIB (8529 Pair) Processor MCP_ RavenMPIC SERR_& PERR_ PCI Interrupts ISA Interrupts 11559.00 9609 Figure 2-3.
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Programming Considerations DMA Channels 2 The PIB supports seven DMA channels. Channels 0 through 3 support 8-bit DMA devices. Channels 5 through 7 are dedicated to 16-bit DMA devices. The channels are allocated as follows: Table 2-3.
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Operating Instructions 4. ALT_RST∗ function controlled by the Port 92 register in the PIB (resets the VMEbus when the MVME2603/2604 is system controller) 2 5. PCI/ISA I/O Reset function controlled by the Clock Divisor register in the PIB 6. The VMEbus SYSRESET∗ signal 7. VMEbus Reset sources from the Universe ASIC (PCI/VME bus bridge controller): the System Software reset and Local Software Reset. The following table shows which devices are affected by the various types of resets.
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Programming Considerations Endian Issues 2 The MVME2603/2604 supports both little-endian (for example, Windows NT) and big-endian (for example, AIX) software. The PowerPC processor and the VMEbus are inherently big-endian, while the PCI bus is inherently little-endian. The following sections summarize how the MVME2603/2604 handles software and hardware differences in big- and little-endian operations.
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Operating Instructions PCI and SCSI 2 SCSI is byte-stream-oriented; the byte having the lowest address in memory is the first one to be transferred regardless of the endian mode. Since the Raven ASIC maintains address invariance in both little-endian and big-endian modes, no endian issues should arise for SCSI data. Big-endian software must still take the byte-swapping effect into account when accessing the registers of the PCI/SCSI device, however.
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3Functional Description 3 Introduction This chapter describes the MVME2603/2604 single board computer on a block diagram level. The General Description provides an overview of the MVME2603/2604, followed by a detailed description of several blocks of circuitry. Figure 3-1 shows a block diagram of the overall board architecture.
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Functional Description Table 3-1.
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General Description Table 3-1.
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Functional Description Block Diagram Figure 3-1 is a block diagram of the MVME2603/2604’s overall architecture. 3 PS/2 Floppy Processor L2 Cache Parallel Keyboard Mouse Async Serial 60X System Bus ISA SIO Sync Serial Falcon Dram Falcon ISA Local Resource Bus FLASH NVRAM Raven PIB ISA CSR RTC Sys CSR 33MHz 32/64-BIT PCI Local Bus PMC Slot 1 PMC/PCIX Slot 2 VME SCSI Ethernet 11540.00 96111 (3-3) Figure 3-1.
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Block Diagram SCSI Interface The MVME2603/2604 VME module supports mass storage subsystems through the industry-standard SCSI bus. These subsystems may include hard and floppy disk drives, streaming tape drives, and other mass storage devices. The SCSI interface is implemented using the Symbios 53C825A SCSI I/O controller at a clock speed of 40 MHz. The SCSI I/O controller connects directly to the PCI local bus.
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Functional Description Ethernet Interface The MVME2603/2604 VME module uses Digital Equipment’s DECchip 21140 PCI Fast Ethernet LAN controller to implement an Ethernet interface that supports both AUI (via MVME712M) and 10BaseT/100BaseTX (via MVME761) connections. The balanced differential transceiver lines are coupled via on-board transformers.
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Block Diagram map description in the MVME2600 Series Single Board Computer Programmer’s Reference Guide, listed in Appendix D, Related Documentation, for detailed programming information. 3 PCI Mezzanine Interface A key feature of the MVME2603/2604 family is the PCI (Peripheral Component Interconnect) bus. In addition to the on-board local bus devices (SCSI, Ethernet, graphics, etc.), the PCI bus supports an industrystandard mezzanine interface, IEEE P1386.1 PMC (PCI Mezzanine Card).
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Functional Description VMEbus Interface The VMEbus interface is implemented with the CA91C042 Universe ASIC. The Universe chip interfaces the 32/64-bit PCI local bus to the VMEbus. 3 The Universe ASIC provides: ❏ The PCI-bus-to-VMEbus interface ❏ The VMEbus-to-PCI-bus interface ❏ The DMA controller functions of the local VMEbus The Universe chip includes Universe Control and Status Registers (UCSRs) for interprocessor communications. It can provide the VMEbus system controller functions as well.
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Block Diagram Asynchronous Serial Ports The two asynchronous ports provided by the ISASIO device employ TTL-level signals that are buffered through EIA-232-D drivers and receivers and routed to the P2 connector. 3 Hardware initializes the two serial ports as COM1 and COM2 with ISA I/O base addresses of $3F8 and $2F8 respectively. This default configuration also assigns COM1 to PIB (PCI/ISA Bridge Controller) interrupt request line IRQ4 and COM2 to IRQ3.
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Functional Description Disk Drive Controller The ISASIO device incorporates a PS/2-compatible low- and high-density disk drive controller for use with an optional external disk drive. The drive interfaces with the ISASIO controller via base board connector J4, which relays both power and control signals. 3 The ISASIO disk drive controller is compatible with the DP8473, 765A, and N82077 devices commonly used to implement floppy disk controllers.
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Block Diagram The PIB controller provides the following functions: ❏ PCI bus arbitration for: – ISA (Industry Standard Architecture) bus DMA 3 – The PHB (PCI Host Bridge) MPU/local bus interface function, implemented by the Raven ASIC – All on-board PCI devices – The PMC (PCI Mezzanine Card) slot ❏ ISA (Industry Standard Architecture) bus arbitration for DMA devices ❏ ISA interrupt mapping for four PCI interrupts ❏ Interrupt controller functionality to support 14 ISA interrupts ❏ Edge/level contr
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Functional Description 3 ❏ A 28-pin 330mil SO device containing the real-time clock, the oscillator, power failure detection circuitry, timer logic, 8KB of static RAM, and gold-plated sockets for a battery ❏ A SNAPHAT® battery housing a crystal along with the battery The SNAPHAT battery package is mounted on top of the M48T59/T559 device. The battery housing is keyed to prevent reverse insertion. The clock furnishes seconds, minutes, hours, day, date, month, and year in BCD 24-hour format.
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Block Diagram ❏ Counter 2 provides the tone for the speaker output function on the PIB controller (the SPEAKER_OUT signal which can be cabled to an external speaker via the remote reset connector). The interval timers use the OSC clock input as their clock source. The MVME2603/2604 drives the OSC pin with a 14.31818 MHz clock source. 16-Bit Timers Four 16-bit timers are available on the MVME2603/2604. The PIB controller supplies one 16-bit timer; the Z8536 CIO device provides the other three.
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Functional Description Z8536 CIO Device The Z8536 CIO device complements the Z85230 ESCC by supplying modem control lines not provided by the Z85230 ESCC. In addition, the Z8536 CIO device has three independent 16-bit counters/ timers. The Z85230 receives a 5 MHz clock input. 3 Base Module Feature Register The Base Module Feature Register contains the details of the MVME2603/2604 single board computer’s configuration. It is an 8-bit read-only register located on the base board at ISA I/O address $0802.
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Block Diagram SCSIP∗ SCSI present. If set, there is no on-board SCSI interface. If cleared, on-board SCSI is supported. 3 P2 Signal Multiplexing Due to the limited supply of available pins in the P2 backplane connectors of MVME2603/2604 models that are configured for MVME761 I/O mode, certain signals are multiplexed through VMEbus connector P2 for additional I/O capacity. The signals affected are synchronous I/O control signals that pass between the base board and the MVME761 transition module.
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Functional Description Table 3-2. P2 Multiplexing Sequence (Continued) MXDO (From Base Board) 3 MXDI (From MVME761) Time Slot Signal Name Time Slot Signal Name 7 RLB4 7 DCD4 8 IDREQ∗ 8 TM4/MID2 9 DTR1 9 RI4 10 DTR2 10 RI1 11 Reserved 11 DSR1 12 Reserved 12 DCD1 13 Reserved 13 RI2 14 Reserved 14 DSR2 15 Reserved 15 DCD2 ABORT Switch (S1) The ABORT switch is located on the LED mezzanine.
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Block Diagram Front Panel Indicators (DS1 – DS6) There are six LEDs on the MVME2603/2604 front panel: CHS, BFL, CPU, PCI, FUS, and SYS. (DS1, yellow). Checkstop; driven by the MPC603/604 status lines on the MVME2603/2604. Lights when a halt condition from the processor is detected. ❏ CHS (DS2, yellow). Board Failure; lights when the BRDFAIL∗ signal line is active. ❏ BFL (DS3, green). CPU activity; lights when the DBB∗ (Data Bus Busy) signal line on the processor bus is active. ❏ CPU (DS4, green).
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Functional Description Polyswitches (Resettable Fuses) The MVME2603/2604 base board draws fused +5V DC, +12V DC, and –12V DC power from the VMEbus backplane through connectors P1 and P2. The 3.3V DC and the core processor voltage power is supplied by the on-board +5Vdc. The following table lists the fuses with the voltages they protect. 3 Table 3-3.
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Block Diagram module illuminates when SCSI terminator power is available. If the SCSI LED on the transition module flickers during SCSI bus operation, check fuse F1 on the P2 adapter board. 3 Note Because any device on the SCSI bus can provide TERMPWR, and because the FUS LED monitors the status of several voltages, the LED does not directly indicate the condition of any single fuse. If the LED flickers or goes out, check all the fuses (polyswitches).
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Functional Description The Raven bridge controller ASIC provides the bridge between the PowerPC microprocessor bus and the PCI local bus. Electrically, the Raven chip is a 64-bit PCI connection. Four programmable map decoders in each direction provide flexible addressing between the PowerPC microprocessor bus and the PCI local bus. 3 Flash Memory The MVME2603/2604 base board has provision for 1MB of 16-bit Flash memory in two 8-bit sockets.
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Block Diagram RAM200 modules of 16, 32, 64, 128, or 256MB are available for memory expansion. The ECC DRAM is controlled by the Falcon memory controller chip set. The Falcon ASICs perform two-way interleaving, with double-bit error detection and single-bit error correction. In addition to the ECC DRAM, the RAM200 module supplies 4MB or 8MB of additional soldered-in 64-bit Flash memory. A jumper header (J10) tells the Falcon chip set where in memory to fetch the board reset vector.
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Functional Description 3 ❏ Fused SCSI terminator power developed from the +5V DC present at connector P2 ❏ A 64-pin DIN connector to interface the EIA-232-D, parallel, SCSI, and Ethernet signals to the MVME712M MVME761 Transition Module The MVME761 transition module (Figure 1-12 on page 1-26) and P2 adapter board are used in conjunction with the MVME2603/2604 base board.
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Block Diagram a TTL-level port to the standard voltage levels needed by various industrystandard serial interfaces, such as EIA-232, EIA-530, etc. SIMs are available for the following configurations: 3 Table 3-4. SIM Type Identification Model Number Module Type SIM232DCE EIA-232 DCE SIM232DTE EIA-232 DTE SIM530DCE EIA-530 DCE SIM530DTE EIA-530 DTE SIMV35DCE V.35 DCE SIMV35DTE V.35 DTE SIMX21DCE X.21 DCE SIMX21DTE X.
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4Connector Pin Assignments 4 MVME2603/2604 Connectors This chapter summarizes the pin assignments for the following groups of interconnect signals for the MVME2603/2604: ❏ Connectors with pin assignments common to MVME712M, as well as MVME761-compatible versions of the base board Connector LED Mezzanine Connector J1 on page 4-3 Debug Connector J2 on page 4-4 Floppy/LED Connector J4 on page 4-7 PCI Expansion Connector J5 on page 4-8 Keyboard and Mouse Connectors J6, J8 on page 4-11 DRAM Mezzanine Connecto
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Connector Pin Assignments ❏ Connectors with pin assignments specific to MVME761compatible versions of the base board Connector VMEbus Connector P2 on page 4-25 Serial Ports 1 and 2 on page 4-26 4 Serial Ports 3 and 4 on page 4-27 Parallel Connector on page 4-28 Ethernet 10BaseT/100BaseTX Connector on page 4-29 The following tables furnish pin assignments only.
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Common Connectors Common Connectors The following tables describe connectors used with the same pin assignments by MVME712M, as well as MVME761-compatible versions of the base board. 4 LED Mezzanine Connector J1 A 14-pin connector (J1 on the base board) supplies the interface between the base board and the LED mezzanine module. On the base board, this connector is a 2x7 header. On the LED mezzanine, it is a 2x7 surfacemount socket strip.
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Connector Pin Assignments Debug Connector J2 A 190-pin connector (J2 on the MVME2603/2604 base board) provides access to the processor bus (MPU bus) and some bridge/memory controller signals. It can be used for debugging purposes. The pin assignments are listed in the following table. 4 Table 4-2.
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Common Connectors Table 4-2.
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Connector Pin Assignments Table 4-2.
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Common Connectors Table 4-2. Debug Connector (Continued) 171 L2TOE∗ 173 GND DRVMOD0 172 L2TWE∗ DRVMOD1 (N/C 174 175 L2TV NAPRUN (N/C 176 177 L2PRSNT1∗ QREQ∗ 178 179 SRESET∗ QACK∗ 180 181 HRESET∗ CPUTDO 182 183 GND CPUTDI 184 185 CPUCLK1 CPUTCK 186 187 CPUCLK2 CPUTMS 188 189 CPUCLK3 CPUTRST∗ 190 4 Floppy/LED Connector J4 A 50-pin high-density connector (J4 on the base board) supplies the interface between the base board and an optional external floppy disk drive.
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Connector Pin Assignments Table 4-3.
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Common Connectors Table 4-4.
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Connector Pin Assignments Table 4-4.
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Common Connectors Keyboard and Mouse Connectors J6, J8 The MVME2603/2604 has two 6-pin circular DIN connectors located on the front panel for the keyboard (J6) and mouse (J8). The pin assignments for those connectors are listed in the following two tables. Table 4-5. Keyboard Connector 1 K_DATA 2 No Connection 3 GND 4 +5VF 5 K_CLK 6 No Connection 4 Table 4-6. Mouse Connector http://www.motorola.
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Connector Pin Assignments DRAM Mezzanine Connector J7 A 190-pin connector (J7 on the MVME2603/2604 base board) supplies the interface between the processor bus (MPU bus) and the RAM200 DRAM mezzanine. The pin assignments are listed in the following table. Table 4-7.
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Common Connectors Table 4-7.
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Connector Pin Assignments Table 4-7.
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Common Connectors Table 4-7. DRAM Mezzanine Connector (Continued) 171 RDU52 173 GND RDU53 172 RDU54 RDU55 174 175 RDU56 RDU57 176 177 RDU58 RDU59 178 179 RDU60 RDU61 180 181 RDU62 RDU63 182 183 CDU0 CDU1 184 185 CDU2 CDU3 186 187 CDU4 CDU5 188 189 CDU6 CDU7 190 4 PCI Mezzanine Card Connectors Four 64-pin connectors (J11/12/13/14 on the MVME2603/2604) supply the interface between the base board and an optional PCI mezzanine card (PMC).
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Connector Pin Assignments Table 4-8. PCI Mezzanine Card Connector (Continued) 4 25 GND CBE3∗ 26 25 IDSEL AD23 26 27 AD22 AD21 28 27 +3.3V AD20 28 29 AD19 +5V 30 29 AD18 GND 30 31 +5V AD17 32 31 AD16 CBE2∗ 32 33 FRAME∗ GND 34 33 GND Not Used 34 35 GND IRDY∗ 36 35 TRDY∗ +3.3V 36 37 DEVSEL∗ +5V 38 37 GND STOP∗ 38 39 GND LOCK∗ 40 39 PERR∗ GND 40 41 SDONE∗ SBO∗ 42 41 +3.
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Common Connectors Table 4-8.
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Connector Pin Assignments VMEbus Connector P1 Two 160-pin connectors (P1 and P2) supply the interface between the base board and the VMEbus. P1 provides power and VME signals for 24-bit addressing and 16-bit data. Its pin assignments are set by the VMEbus specification. They are listed in the following table. 4 Table 4-9.
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MVME712M-Compatible Versions Table 4-9.
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Connector Pin Assignments Table 4-10.
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MVME712M-Compatible Versions SCSI Connector The SCSI connector for the MVME2603/2604 is a 50-pin connector located on the front panel of the MVME712M transition module. The pin assignments for the SCSI connector are listed in the following table. Table 4-11.
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Connector Pin Assignments Serial Ports 1-4 For the MVME2603/2604, the interface for asynchronous ports 1 and 2 and for synchronous/asynchronous ports 3 and 4 is implemented with four EIA-232-D DB25 connectors (J7-J10) located on the front panel of the MVME712M transition module. The pin assignments for serial ports 1-4 on the MVME712M are listed in the following table. 4 Table 4-12.
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MVME712M-Compatible Versions Table 4-12. Serial Connections—MVME712M Ports 1-4 22 No Connection 23 No Connection 24 ETTxC (Port 4 only) 25 No Connection 4 Parallel Connector Both versions of the base board provide parallel I/O connections. For MVME712M-compatible base boards, the parallel interface is implemented with a 36-pin Centronics-type socket connector located on the MVME712M transition module. The pin assignments are listed in the following table. Table 4-13.
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Connector Pin Assignments Table 4-13. Parallel I/O Connector (MVME712M) (Continued) 4 15 No Connection No Connection 33 16 GND No Connection 34 17 No Connection No Connection 35 18 No Connection No Connection 36 Ethernet AUI Connector The MVME2603/2604 provides both AUI and 10BaseT/100BaseTX LAN connections. For MVME712M-compatible base boards, the LAN interface is an AUI connection implemented with a DB15 connector (J6) located on the MVME712M transition module.
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MVME761-Compatible Versions MVME761-Compatible Versions The following tables summarize the pin assignments of connectors that are specific to MVME2603/2604 modules configured for use with MVME761 transition modules. 4 VMEbus Connector P2 Two 160-pin connectors (P1 and P2) supply the interface between the base board and the VMEbus. P1 provides power and VME signals for 24-bit addressing and 16-bit data. Its pin assignments are set by the VMEbus specification.
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Connector Pin Assignments Table 4-15.
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MVME761-Compatible Versions Table 4-16. Serial Connections—Ports 1 and 2 (MVME761) 6 SPnDSR 7 SPnRTS 8 SPnCTS 9 SPnRI 4 Serial Ports 3 and 4 For MVME761-compatible versions of the base board, the synchronous/asynchronous interface for ports 3 and 4 is implemented with a pair of HD26 connectors (J7 and J8) located on the front panel of the transition module. The pin assignments for serial ports 3 and 4 are listed in the following table. Table 4-17.
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Connector Pin Assignments Table 4-17. Serial Connections—Ports 3 and 4 (MVME761) 4 18 LLBn 19 SPn_P19 20 DTRn 21 RLBn 22 RIn 23 SPn_P23 24 TXCOn 25 TMn 26 No Connection Parallel Connector Both versions of the base board provide parallel I/O connections. For MVME761-compatible models, the parallel interface is implemented with an IEEE P1284 36-pin connector (J10) located on the MVME761 transition module. The pin assignments are listed in the following table. Table 4-18.
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MVME761-Compatible Versions Table 4-18. Parallel I/O Connector (MVME761) (Continued) 14 INPRIME∗ GND 32 15 PRSTB∗ GND 33 16 SELIN∗ GND 34 17 AUTOFD∗ GND 35 18 Pull-up No Connection 36 4 Ethernet 10BaseT/100BaseTX Connector The MVME2603/2604 provides both AUI and 10BaseT/100BaseTX LAN connections. For MVME761-compatible base boards, the LAN interface is a 10BaseT/100BaseTX connection implemented with a standard RJ-45 socket located on the MVME761 transition module.
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5PPCBug 5 Overview The PowerPC debugger, PPCBug, is a powerful evaluation and debugging tool for systems built around Motorola PowerPC microcomputers. Facilities are available for loading and executing user programs under complete operator control for system evaluation. The PowerPC debugger provides a high degree of functionality and user friendliness, and yet stresses portability and ease of maintenance.
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PPCBug Because PPCBug is command-driven, it performs its various operations in response to user commands entered at the keyboard. The flow of control in PPCBug is described in the PPCBug Firmware Package User’s Manual, listed in Appendix D, Related Documentation. When you enter a command, PPCBug executes the command and the prompt reappears.
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Using the Debugger Using the Debugger PPCBug is command-driven; it performs its various operations in response to commands that you enter at the keyboard. When the PPC1-Bug prompt appears on the screen, the debugger is ready to accept debugger commands. When the PPC1-Diag prompt appears on the screen, the debugger is ready to accept diagnostics commands. To switch from one mode to the other, enter SD. What you key in is stored in an internal buffer.
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PPCBug Debugger Commands The individual debugger commands are listed in Table 5-1. The commands are described in detail in the PPCBug Firmware Package User’s Manual. Note 5 You can list all the available debugger commands by entering the Help (HE) command alone. You can view the syntax for a particular command by entering HE and the command mnemonic, as listed below. Table 5-1.
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Using the Debugger Table 5-1.
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PPCBug Table 5-1.
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Using the Debugger Table 5-1.
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PPCBug Diagnostic Tests The individual diagnostic test sets are listed in the following table. The diagnostics are described in the PPC1Bug Diagnostics Manual, listed in Appendix D, Related Documentation. Table 5-2.
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6CNFG and ENV Commands 6 Overview You can use the factory-installed debug monitor, PPCBug, to modify certain parameters contained in the PowerPC board’s Non-Volatile RAM (NVRAM), also known as Battery Backed-up RAM (BBRAM). ❏ The Board Information Block in NVRAM contains various elements concerning operating parameters of the hardware. Use the PPCBug command CNFG to change those parameters. ❏ Use the PPCBug command ENV to change configurable PPCBug parameters in NVRAM.
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CNFG and ENV Commands CNFG – Configure Board Information Block Use this command to display and configure the Board Information Block, which is resident within the NVRAM. The board information block contains various elements detailing specific operational parameters of the PowerPC board.
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ENV – Set Environment ENV – Set Environment Use the ENV command to view and/or configure interactively all PPCBug operational parameters that are kept in Non-Volatile RAM (NVRAM). Refer to the PPCBug Firmware Package User’s Manual for a description of the use of ENV. Additional information on registers in the Universe ASIC that affect these parameters is contained in your PowerPC board programmer’s reference guide. Listed and described below are the parameters that you can configure using ENV.
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CNFG and ENV Commands Remote Start Method Switch [G/M/B/N] = B? The Remote Start Method Switch is used when the MVME2600/MVME3600/MVME4600 is cross-loaded from another VME-based CPU, to start execution of the cross-loaded program. G Use the Global Control and Status Register to pass and start execution of the cross-loaded program. This selection is not applicable to the MVME2600/MVME3600 boards.
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ENV – Set Environment Network PReP-Boot Mode Enable [Y/N] = N? Y Enable PReP-style network booting (same boot image from a network interface as from a mass storage device). N Do not enable PReP-style network booting. (Default) Negate VMEbus SYSFAIL* Always [Y/N] = N? Y Negate the VMEbus SYSFAIL∗ signal during board initialization. N Negate the VMEbus SYSFAIL∗ signal after successful completion or entrance into the bug command monitor.
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CNFG and ENV Commands NVRAM Bootlist (GEV.fw-boot-path) Boot Enable [Y/N] = N? Note Y Give boot priority to devices defined in the fw-bootpath global environment variable (GEV). N Do not give boot priority to devices listed in the fwboot-path GEV. (Default) When enabled, the GEV (Global Environment Variable) boot takes priority over all other boots, including Autoboot and Network Boot. NVRAM Bootlist (GEV.
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ENV – Set Environment Auto Boot Scan Enable [Y/N] = Y? Y If Autoboot is enabled, the Autoboot process attempts to boot from devices specified in the scan list (for example, FDISK/CDROM/TAPE/HDISK). (Default) N If Autoboot is enabled, the Autoboot process uses the Controller LUN and Device LUN to boot. Auto Boot Scan Device Type List = FDISK/CDROM/TAPE/HDISK? This is the listing of boot devices displayed if the Autoboot Scan option is enabled.
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CNFG and ENV Commands Auto Boot Abort Delay = 7? The time in seconds that the Autoboot sequence will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the key. The time value is from 0-255 seconds. (Default = 7 seconds) Auto Boot Default String [NULL for an empty string] = ? You may specify a string (filename) which is passed on to the code being booted. The maximum length of this string is 16 characters.
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ENV – Set Environment ROM Boot Direct Ending Address = FFFFFFFC? The last location tested when PPCBug searches for a ROMboot module. (Default = $FFFFFFFC) Network Auto Boot Enable [Y/N] = N? Y The Network Auto Boot (NETboot) function is enabled. N The NETboot function is disabled. (Default) Network Auto Boot at power-up only [Y/N] = N? Y NETboot is attempted at power-up reset only. N NETboot is attempted at any reset.
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CNFG and ENV Commands ! Caution If you use the NIOT debugger command, these parameters need to be saved somewhere in the offset range $00001000 through $000016F7. The NIOT parameters do not exceed 128 bytes in size. The setting of this ENV pointer determines their location. If you have used the same space for your own program information or commands, they will be overwritten and lost.
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ENV – Set Environment Processor/Memory Mezzanine Module User’s Manual, listed in Appendix D, Related Documentation, for appropriate values. The default value varies according to the system’s bus clock speed. Note ROM First Access Length is not applicable to the MVME2600/3600/4600. The configured value is ignored by PPCBug.
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CNFG and ENV Commands L2 Cache Parity Enable [On-Detection/Always/Never - O/A/N] = O? O L2 Cache parity is enabled upon detection. (Default) A L2 Cache parity is always enabled. N L2 Cache parity is never enabled. PCI Interrupts Route Control Registers (PIRQ0/1/2/3) = 0A0B0E0F? Initializes the PIRQx (PCI Interrupts) route control registers in the IBC (PCI/ISA bus bridge controller).
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ENV – Set Environment PCI Slave Image 0 Bound Address Register = 00000000? The configured value is written into the LSI0_BD register of the Universe chip. PCI Slave Image 0 Translation Offset = 00000000? The configured value is written into the LSI0_TO register of the Universe chip. PCI Slave Image 1 Control = C0820000? The configured value is written into the LSI1_CTL register of the Universe chip.
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CNFG and ENV Commands PCI Slave Image 3 Control = C0400000? The configured value is written into the LSI3_CTL register of the Universe chip. PCI Slave Image 3 Base Address Register = 2FFF0000? The configured value is written into the LSI3_BS register of the Universe chip. PCI Slave Image 3 Bound Address Register = 30000000? The configured value is written into the LSI3_BD register of the Universe chip.
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ENV – Set Environment VMEbus Slave Image 1 Base Address Register = 00000000? The configured value is written into the VSI1_BS register of the Universe chip. VMEbus Slave Image 1 Bound Address Register = 00000000? The configured value is written into the VSI1_BD register of the Universe chip. VMEbus Slave Image 1 Translation Offset = 00000000? The configured value is written into the VSI1_TO register of the Universe chip.
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CNFG and ENV Commands VMEbus Slave Image 3 Translation Offset = 00000000? The configured value is written into the VSI3_TO register of the Universe chip. PCI Miscellaneous Register = 10000000? The configured value is written into the LMISC register of the Universe chip. Special PCI Slave Image Register = 00000000? The configured value is written into the SLSI register of the Universe chip.
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ASpecifications A Specifications Table A-1 lists the general specifications for MVME2603/2604 base boards. Subsequent sections detail cooling requirements and FCC compliance. A complete functional description of the MVME2603/2604 base boards appears in Chapter 3, Functional Description. Specifications for the optional PCI mezzanines can be found in the documentation for those modules. Table A-1.
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A Specifications Cooling Requirements The Motorola MVME2603/2604 family of single board computers is specified, designed, and tested to operate reliably with an incoming air temperature range from 0° to 55° C (32° to 131° F) with forced air cooling of the entire assembly (base board and modules) at a velocity typically achievable by using a 100 CFM axial fan. Temperature qualification is performed in a standard Motorola VME system chassis.
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FCC Compliance FCC Compliance The MVME2603/2604 single board computer was tested in an FCC-compliant chassis and meets the requirements for Class A equipment. FCC compliance was achieved under the following conditions: ❏ Shielded cables on all external I/O ports. ❏ Cable shields connected to earth ground via metal shell connectors bonded to a conductive module front panel. ❏ Conductive chassis rails connected to earth ground. This provides the path for connecting shields to earth ground.
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BSerial Interconnections B Introduction As described in previous chapters of this manual, the MVME2603/2604 serial communications interface has four ports. Two of them are combined synchronous/asynchronous ports; the other two are asynchronous only. Both synchronous and asynchronous ports supply an EIA-232-D DCE/DTE interface via P2 and the MVME712M transition module.
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Serial Interconnections synchronous (SDLC/HDLC) and asynchronous protocols. The hardware supports asynchronous serial baud rates of 110B/s to 38.4KB/s and synchronous baud rates of up to 2.5MB/s. B Each port supports the CTS, DCD, RTS, and DTR control signals, as well as the TxD and RxD transmit/receive data signals and TxC/RxC synchronous clock signals. Since not all modem control lines are available in the Z85230, a Z8536 CIO device is used to provide the missing modem lines.
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EIA-232-D Connections B Table B-1. EIA-232-D Interconnect Signals Pin Number Signal Mnemonic 1 Signal Name and Description Not used. 2 TxD Transmit Data. Data to be transmitted; input to modem from terminal. 3 RxD Receive Data. Data which is demodulated from the receive line; output from modem to terminal. 4 RTS Request To Send. Input to modem from terminal when required to transmit a message. With RTS off, the modem carrier remains off.
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Serial Interconnections Table B-1. EIA-232-D Interconnect Signals (Continued) B Pin Number Signal Mnemonic 22 RI Signal Name and Description Ring Indicator. Output from modem to terminal; indicates that an incoming call is present. The terminal causes the modem to answer the phone by carrying DTR true while RI is active. 23 Not used. 24 TxC Transmit Clock (DTE). Input to modem from terminal; same function as TxC on pin 15. 25 BSY Busy.
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EIA-232-D Connections Interface Characteristics B The EIA-232-D interface standard specifies all parameters for serial binary data interchange between DTE and DCE devices using unbalanced lines. EIA-232-D transmitter and receiver parameters applicable to the MVME2603/2604 are listed in the following tables. Table B-2. EIA-232-D Interface Transmitter Characteristics Parameter Value Minimum Output voltage (with load resistance of 3000Ω to 7000Ω) Unit Maximum ±8.
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Serial Interconnections B EIA-530 Connections The EIA-530 interface complements the EIA-232-D interface in function. The EIA-530 standard defines the mechanical aspects of this interface, which is used for transmission of serial binary data, both synchronous and asynchronous. It is adaptable to balanced (double-ended) as well as unbalanced (single-ended) signaling and offers the possibility of higher data rates than EIA-232-D with the same DB-25 connector.
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EIA-530 Connections Table B-4. MVME761 EIA-530 Interconnect Signals (Continued) B Pin Number Signal Mnemonic Signal Name and Description 12 TxC_B Transmit Signal Element Timing—DCE (B). Control signal that clocks input data. 13 CTS_B Clear to Send (B). Input to DTE from DCE to indicate that message transmission can begin. 14 TxD_B Transmit Data (B). Data to be transmitted; output from DTE to DCE. 15 TxC_A Transmit Signal Element Timing—DCE (A). Control signal that clocks input data.
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Serial Interconnections B Interface Characteristics In specifying parameters for serial binary data interchange between DTE and DCE devices, the EIA-530 standard assumes the use of balanced lines, except for the Remote Loopback, Local Loopback, and Test Mode lines, which are single-ended.
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Proper Grounding B Table B-6. EIA-530 Interface Receiver Characteristics Parameter Value Minimum Maximum Unit Differential input voltage ±12 V Input offset voltage ±12 V Differential input high threshold voltage 200 mV Differential input low threshold voltage −200 V 7000 Ω Input hysteresis Input impedance (−15V < Vin < +15V) 1.0 3000 V Proper Grounding An important subject to consider is the use of ground pins. There are two pins labeled GND.
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CTroubleshooting CPU Boards: Solving Startup Problems C Introduction In the event of difficulty with your CPU board, try the simple troubleshooting steps on the following pages before calling for help or sending the board back for repair. Some of the procedures will return the board to the factory debugger environment. (The board was tested under these conditions before it left the factory.) The self-tests may not run in all user-customized environments. Table C-1.
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Troubleshooting CPU Boards: Solving Startup Problems Table C-1. Troubleshooting MVME2603/2604 Boards (Continued) C Condition Possible Problem Try This: II. There is a display on the terminal, but input from the keyboard and/or mouse has no effect. A. The keyboard or mouse may be connected incorrectly. Recheck the keyboard and/or mouse connections and power. B. Board jumpers may be configured incorrectly. Check the board jumpers per this manual. C.
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Introduction Table C-1. Troubleshooting MVME2603/2604 Boards (Continued) Condition IV. Continued Possible Problem Try This: 2. Type in: env;d This sets up the default parameters for the debugger environment. 3. When prompted to Update Non-Volatile RAM, type in: y 4. When prompted to Reset Local System, type in: y 5. After clock speed is displayed, immediately (within five seconds) press the Return key: or BREAK to exit to the System Menu.
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Troubleshooting CPU Boards: Solving Startup Problems Table C-1. Troubleshooting MVME2603/2604 Boards (Continued) C Condition Possible Problem Try This: V. The debugger is in system mode and the board autoboots, or the board has passed selftests. A. No apparent problems — troubleshooting is done. No further troubleshooting steps are required. VI. The board has failed one or more of the tests listed above, and cannot be corrected using the steps given. A.
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DRelated Documentation D Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual. You can obtain paper or electronic copies of Motorola Computer Group publications by: ❏ Contacting your local Motorola sales office ❏ Visiting MCG’s World Wide Web literature site, http://www.motorola.
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Related Documentation Manufacturers’ Documents For additional information, refer to the following table for manufacturers’ data sheets and user’s manuals. For your convenience, a source for the listed document is also provided. It is important to note that in many cases, the information shown is preliminary and the revision levels of the documents are subject to change without notice.
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Manufacturers’ Documents Document Title and Source PowerPC® Microprocessor Family: The Programming Environments for 32-Bit Microprocessors Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 Web Site: http://e-www.motorola.com/webapp/DesignCenter/ E-mail: ldcformotorola@hibbertco.com OR IBM Microelectronics Programming Environment Manual Web Site: http://www.chips.ibm.
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Related Documentation Publication Number Document Title and Source D SCC (Serial Communications Controller) User’s Manual (for Z85230 and other Zilog parts) Web Site: http://www.zilog.com/pdfs/serial/scc_escc_iscc_manual/contents.html Z8536 CIO Counter/Timer and Parallel I/O Unit Product Specification and User’s Manual (in Z8000® Family of Products Data Book) Web Site: http://www.zilog.com/products/zx80dev.
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Related Specifications Related Specifications For additional information, refer to the following table for related specifications. For your convenience, a source for the listed document is also provided. It is important to note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice.
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Related Documentation Publication Number Document Title and Source D Peripheral Component Interconnect (PCI) Local Bus Specification, Revision 2.0 PCI Special Interest Group Web Site: http://www.pcisig.com/ PowerPC Reference Platform (PRP) Specification, Third Edition, Version 1.0, Volumes I and II International Business Machines Corporation Web Site: http://www.ibm.com MPR-PPC-RPU-02 PowerPC Microprocessor Common Hardware Reference Platform: A System Architecture (CHRP), Version 1.
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Related Specifications Document Title and Source Publication Number PowerPC Reference Platform (PRP) Specification, Third Edition, Version 1.0, Volumes I and II; International Business Machines Corporation Web Site: http://www.ibm.com MPR-PPC-RPU-02 IEEE Standard for Local Area Networks: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications Institute of Electrical and Electronics Engineers, Inc. Web Site: http://standards.ieee.
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Index A Abort (interrupt) signal 3-16 abort (interrupt) signal 2-3 adapter board, P2 1-14, 1-25, 1-45, 1-49, 3-5, 3-21 adapter, P2 for MVME761 1-33 MVME712M 1-24 MVME761 1-32 ambient air temperature A-2 assembly language 5-2 Autoboot enable 6-6, 6-7 B backplane jumpers 1-43 base board layout 1-6 base module feature register 3-14 battery 3-12 block diagram MVME2603/2604 3-4 board configuration 1-5 board information block 6-2 board placement 1-43 board structure 6-2 C cables A-3 chassis rails, grounding A-
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Index disk drive controller 3-10, B-1 DMA channels 2-13 documentation, related D-1 DRAM base address 1-50 DRAM speed 6-10 E EIA-232-D interconnections B-2 EIA-530 interconnections B-6 interface characteristics B-8 endian issues function of Raven ASIC 2-15 function of Universe ASIC 2-16 PCI domain 2-15 processor/memory domain 2-15 VMEbus domain 2-16 ENV command 6-3 environmental parameters 6-1 ESD precautions 1-35 Ethernet 1-51, 3-18 station address 3-6 F I N D E X Falcon memory controller chip set 2-5,
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J17 (SP4 transmit clock) 1-10 J18 (SP3 transmit clock) 1-12 J20 (SP4 clock receiver buffer) 1-11 J22 (system controller) 1-13 J3 (cache mode) 1-7 jumpers, backplane 1-43 jumpers, setting 1-6, 1-13 K keyboard/mouse interface 3-8, 4-11 L L2 cache 1-1, 1-7, 3-1, 3-3 LAN transceiver 1-51, 3-18 LED mezzanine 1-14, 2-4, 3-19, 4-3 local reset (LRST) 2-3, 3-16 lowercase 5-3 M manufacturers’ documents D-2 memory capacities 3-21 memory map PCI local bus 2-6, 2-7 memory maps 2-5 memory size 6-10 multiplexing functi
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Index serial communications interface 3-13, B-1 serial interface 3-9 serial interface modules (SIMs) 3-22 serial interface parameters B-5 serial port configuration, base board 1-8, 1-10, 1-11, 1-12 serial port configuration, transition module 1-17, 1-27 serial ports 3-8, 3-13 set environment to bug/operating system (ENV) 6-3 SGS- Thomson MK48T559 timekeeper device 2-13 shielded cables (see also cables) A-3 signal multiplexing, P2 1-48 sources of reset 2-13 speaker output 1-52, 3-13, 3-19 specifications, ba