Freescale MOTOROLA Semiconductor, Inc. Metrowerks Freescale Semiconductor, Inc... SW/HW Dept MSC8101 ADS User’s Manual Revision B (Revision Release 1.2) Dragilev Lev SW/HW Dept Motorola Semiconductor Israel 1 Shenkar Street, Herzlia 46120, Israel TEL: 972-9-522-579 email: Lev.Dragilev@motorola.com FAX: 972-9-9562990 25/1/2004 For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSC8101ADS RevB User’s Manual For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. CONTENTS Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc. 5•11•1 5•11•2 5•11•3 5•11•4 7•1 7•1•1 7•1•2 7•1•3 Freescale Semiconductor, Inc... A•1 B•1 B•1•1 B•1•2 B•1•3 B•1•4 B•1•5 B•1•6 B•1•7 B•1•8 B•1•9 B•1•10 B•1•11 B•1•12 B•1•13 C•1 C•1•1 C•1•2 C•1•3 MOTOROLA BCSR0 - Board Control / Status Register 0 BCSR1 - Board Control / Status Register 1 BCSR2 - Board Control / Status Register 2 BCSR3 - Board Status Register 3 Power rails. 5V Bus 3.3V Bus 1.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. VI MSC8101ADS RevB User’s Manual For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. VIII MSC8101ADS RevB User’s Manual For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... LIST OF TABLES TABLE 1-1. TABLE 4-1. TABLE 4-2. TABLE 4-3. TABLE 4-4. TABLE 5-1 TABLE 5-2. TABLE 5-3. TABLE 5-4. TABLE 5-5. TABLE 5-6. TABLE 5-7. TABLE 5-8. TABLE 5-9. TABLE 5-10. TABLE 5-11. TABLE 5-12. TABLE 5-13. TABLE 5-14. TABLE 5-15. TABLE 5-16. TABLE 5-17. TABLE 5-18. TABLE 6-1. TABLE 7-1. TABLE A-1. TABLE B1-2. TABLE B1-3. TABLE B1-4. TABLE B1-5. TABLE B1-6. TABLE B1-7. TABLE B1-8. TABLE B1-9. TABLE B1-10. TABLE B1-11.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. T-X MSC8101ADS RevB User’s Manual For More Information On This Product, Go to: www.freescale.
FreescaleGeneral Semiconductor, Inc. Information 1 - General Information 1•1 Introduction This document describes the engineering specifications of the MSC8101ADS board based on the MSC8101- first member of the family of programmable DSP based around the SC100 DSP cores.
FreescaleGeneral Semiconductor, Inc. Information [5] PMC-SIERRA 5350 Long Form Data Sheet [6] PMC-SIERRA 5350 Errata Notice [7] PMC-SIERA 5350 Reference Design [8] LXT970A (by Level One) Data Sheet [9] LXT970 Demo Board User’s Guide 1•4 Specification The MSC8101ADS specifications are given in TABLE 1-1. "MSC8101ADS Specifications" below TABLE 1-1. MSC8101ADS Specifications Freescale Semiconductor, Inc...
FreescaleGeneral Semiconductor, Inc. Information Freescale Semiconductor, Inc... 1•5 MOTOROLA ADS Features o 64-bit MSC8101, running up to @ 100MHz external bus frequency. o 8 MByte, 80 pin Flash SIMM reside after buffer. Support for up to 32 MByte, controlled by GPCM, 5V Programmable, with Automatic Flash SIMM identification, via BCSR. o 16 MByte unbuffered SDRAM on PPC bus, controlled by SDRAM machine, soldered directly on the board. Data bus width 64/32 bits is controlled by Jumper Array.
FreescaleGeneral Semiconductor, Inc. Information On-board 1.2V - 2.2V adjustable for MSC8101 Internal Logic Operation and 3.3V±10% fixed Voltage Regulators for other circuits. May be bypassed in case of external power supplying. o Software Option Switch provides 8 S/W options via BCSR. o LED’s for power supply, module enables, timer expired and SW indications. Freescale Semiconductor, Inc... o 14 MSC8101ADS RevB User’s Manual For More Information On This Product, Go to: www.freescale.
FreescaleGeneral Semiconductor, Inc. Information FIGURE 1-1 MSC8101ADS Block Diagram 2 PPC (non-buffered) 1 SDRAM D[0:59] 2Megx32 Address Mux for variable Port Size 64/32 36pin HOST Buffers Clock Host PORT 28 D[32:59] 16.4/25MHz * 16Mbyte @ 64bit 3.3V HOST I/F Reset,Config Interrupts DATA Transceivers & Address Buffers 5V PPC Bus (buffered) D[0:31] Control & Status Register Altera 3.
Freescale Semiconductor, Inc. Hardware Preparation 2 - Hardware Preparation 2•1 INTRODUCTION This chapter provides unpacking instructions, hardware preparation, and installation instructions for the MSC8101ADS. 2•2 UNPACKING INSTRUCTIONS NOTE If the shipping carton is damaged upon receipt, request carrier’s agent to be present during unpacking and inspection of equipment. Freescale Semiconductor, Inc... Unpack equipment from shipping carton.
FreescaleHardware Semiconductor, Inc. Preparation Freescale Semiconductor, Inc... FIGURE 2-1 MSC8101ADS Top Side Part Location diagram Host SW MOTOROLA EE SW 64/32 Select Boot Mode SW Config SW MSC8101ADS RevB User’s Manual S/W Opt For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. Hardware Preparation 2•3•1 Setting The Core Supply Voltage Level The internal Logic & PLL’s of the MSC8101 is powered separately through a supply bus named 1V5. The voltage level over this power bus may vary between 0.9V - 2.1V. In the lower voltage level, the Processor will operate at lower frequency range, consuming a smaller amount of power and vice-versa for the higher voltage level. 1V5 power level is factory set for 1.5V, but may be changed by RP2.
Freescale Semiconductor, Inc. Installation Instructions 3 - Installation Instructions The MSC8101ADS may be configured according to the required working environment as follows: • Host Controlled Operation through OnCE Port • Host Interface Operation through HDI16 Port • Stand-Alone Mode 3•1 OnCE Connection Scheme In this configuration the MSC8101ADS is controlled by a host computer via the OnCE Port, which is a subset of the JTAG port.
Freescale Semiconductor, Inc. Installation Instructions FIGURE 3-2 Host System Debug Scheme B Host Computer Media I/F Command Converter 14 Wire Flat Cable To JTAG/OnCE 36Wire Flat Cable Host Device Freescale Semiconductor, Inc... 5V Power Supply 3•3 Stand Alone Operation In this mode, the ADS is not controlled by the host via the OnCE port. It may connect to host via one of its other ports, e.g., RS232 port, Fast Ethernet port, ATM155 port etc.
Freescale Semiconductor, Inc. Installation Instructions FIGURE 3-3 Stand Alone Configuration et rn he ork t E etw N ATM155(Opt ic) Host Computer Freescale Semiconductor, Inc... T1/E1 four ch. RS 5V Power Supply 232 Audio Stereo 3•4 +5V Power Supply Connection The MSC8101 requires +5V DC @ 4A max, power supply for operation.
Freescale Semiconductor, Inc. Installation Instructions supplied with the Command Converter obtained from Macraigor Systems. FIGURE 3-5 "P6 JTAG/OnCE Port Connector" below shows the pin configuration of the connector. FIGURE 3-5 P6 - JTAG/OnCE Port Connector TDI TDO TCK N.C. RESET 3.3V Freescale Semiconductor, Inc... N.C. 3•6 1 2 3 4 5 6 7 8 9 10 TMS 11 12 13 14 GND GND GND KEY (NO PIN) N.C.
Freescale Semiconductor, Inc. Installation Instructions FIGURE 3-6 P4 - Host I/F Connector GND HD0 HD2 HD4 HD6 HD8 HD10 Freescale Semiconductor, Inc... HD12 HD14 GND HA0 HA2 HCS1 HRRQACK HRDRW HRESET 3.3V GND 3•7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 GND HD1 HD3 HD5 HD7 HD9 HD11 HD13 HD15 GND HA1 HA3 HCS2 HREQ HDS PORST N.C.
Freescale Semiconductor, Inc. Installation Instructions FIGURE 3-7 P27A - Upper RS-232 Serial Port Connector CD TX 1 2 RX DTR 3 4 5 GND 6 7 8 9 DSR N.C. CTS N.C. Freescale Semiconductor, Inc... FIGURE 3-8 P27B - Lower RS-232 Serial Port Connector N.C. TX 1 2 RX N.C. 3 4 5 GND 3•8 6 7 8 9 N.C. N.C. N.C. N.C. 10/100-Base-T Ethernet Port Connection The 10/100-Base-T port connector - P12, is an 8-pin, 90o, receptacle RJ45 connector.
Freescale Semiconductor, Inc. Installation Instructions CAUTION The memory SIMMs have alignment nibble near their # 1 pin. It is important to align the memory correctly before it is twisted, otherwise damage might be inflicted to both the memory SIMM and its socket. FIGURE 3-9 Flash Memory SIMM Insertion (1) Insert Freescale Semiconductor, Inc... (2) Turn Metal Lock Clip Flash SIMM SIMM Socket SIMM MOTOROLA MSC8101ADS RevB User’s Manual For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. Operating Instructions 4 - Operating Instructions 4•1 INTRODUCTION This chapter provides necessary information to use the MSC8101-ADS in host-controlled and stand-alone configurations. This includes controls and indicators, memory map details, and software initialization of the board. 4•2 SWITCHES The MSC8101ADS has the following switches: 4•2•1 Host I/F Setting - SW1 Freescale Semiconductor, Inc... This switch is using for manually set a Host Bus parameters.
Freescale Semiconductor, Inc. Operating Instructions FIGURE 4-2 Switch SW2 - Description SW2 8 EED 7 EE5 6 EE4 5 EE3 4 EE2 3 EE1 2 EE0 ON Freescale Semiconductor, Inc... RESERVED 1 Set to ‘0’ <= 4•2•3 => Set to ’1’ ABORT Switch - SW3 The ABORT switch is normally used to abort program execution, this by issuing a level 0 nonmaskable interrupt to the Processor.
Freescale Semiconductor, Inc. Operating Instructions FIGURE 4-3 DIP-Switch 64/32 Bit Setting SW6 64 BIT 32 SW5 4•2•6 HARD RESET (HRESET) - Switch - SW7 Freescale Semiconductor, Inc... HARD reset is generated when switch SW7 is pressed. When the Processor executes HARD reset sequence, all its configuration is lost, including data stored in the SDRAMs and the Processor has to be re-initialized.
Freescale Semiconductor, Inc. Operating Instructions FIGURE 4-4 Switch SW9 MODCK - Description SW9 HOST CFG 8 FCFG 7 MODCK6 6 5 MODCK4 4 MODCK3 3 MODCK2 2 MODCK1 ON Freescale Semiconductor, Inc... MODCK5 1 => Set to ’1’ Set to ‘0’ <= TABLE 4-1. Available Clock Mode Setting MODCK-1 -2 -3 -4 -5 -6 0 0 1 1 1 1 0 0 1 0 0 1 Clock Mode Clock In MHz CPM MHz PPC Bus MHz SC140 Core MHz 57a 55 137.5 55a 275 20 200 100 300 b 9 a. Factory setting. b.
Freescale Semiconductor, Inc. Operating Instructions FIGURE 4-5 Switch SW10 BOOT MODE - Description RESERVED 4 BTM1 3 BTM0 2 ON BOOT SW10 DBG 1 => Set to ’1’ Freescale Semiconductor, Inc... Set to ‘0’ <= 4•2•10 Software Options Switch - SW11 SW11 is a 4-switch Dip-Switch with three poles in use. This switch is connected over SWOPT(0:2) lines which are available at BCSR2 via bus driver U16, S/W options may be manually selected, according to SW11 state. SW11 is factory set to all ON.
Freescale Semiconductor, Inc. Operating Instructions DLL. See TABLE 4-2. summarized available modes. . Default set is JP3-OPEN (DLL disable). TABLE 4-2. JP1/JP2 Settings 4•3•3 J1 J2 Clock Driver U44 MSC8101 Mode OPEN OPEN PLL Mode DLL disable CLOSE CLOSE Buffer Mode DLL enable JP3 - 50 Ohm Enable. 4•3•4 JP4 - VPP Source Selector JP4 selects the source for VPP - programming voltage for the Flash SIMM.
Freescale Semiconductor, Inc. Operating Instructions FIGURE 4-8 JP9 - 5V CODEC Source Selection JP9 JP9 1 1 5V Internal +5V GND External Factory Set 4•3•8 JS1-5 - Current Consumption Measurement Freescale Semiconductor, Inc... JS1-5 reside on I/O-pins, core & PLL main flow. To measure current consumption, the corresponding JS should be removed using a solder tool and a current meter (shunt) should be connected instead, with as shorted and thicker wires as possible.
Freescale Semiconductor, Inc. Operating Instructions The green Ethernet Receive LED indicator blinks whenever the LXT970 is transmitting data via the 10/100-Base-T port. 4•4•4 Ethernet LINK Indicator - LD4 The yellow Ethernet Twisted Pair Link Integrity LED indicator - LINK, lights to indicate good link integrity on the 10/100-Base-T port. LD4 is off when the link integrity fails.
Freescale Semiconductor, Inc. Operating Instructions Note Application S/W should always seek to match the state of LD13 to the status of the LXT970, so that, this indication is made reliable as to the correct status of the LXT970. 4•4•14 ATM ON - LD14 When the yellow ATM ON LED is lit, it indicates that the ATM-UNI transceiver - the PM5350, is active and enables communication via that medium.
Freescale Semiconductor, Inc. Operating Instructions 2) • PPC Bus SDRAM Controller • GPCM (Flash, BCSR, ATM, Ext. Tools) • UPM (QFALC, Ext. Tools) Communication functions which include: • ATM SAR • Fast Ethernet controller. • TDMs for T1/E1 and CODEC support • UART for terminal or host computer connection. The internal registers of the MPC must be programmed after Hard reset as described in the following paragraphs. The addresses and programming values are in Hexadecimal base.
Freescale Semiconductor, Inc. Operating Instructions Warning The initialization in TABLE 4-4. "Memory Controller Initialization for 100(50) MHz" below are based on design and are not verified yet, due to silicon availability problems. TABLE 4-4. Memory Controller Initialization for 100(50)a MHz Reg. Freescale Semiconductor, Inc... BR0 Device Type Bus FF801801 Base at FF800000, 32 bit port size, no parity, GPCM SM73248XG2JHBG0 by Smart Modular Tech.
Freescale Semiconductor, Inc. Operating Instructions TABLE 4-4. Memory Controller Initialization for 100(50)a MHz Reg. BR5 Device Type PM5350 - ATM UNI Buffered PPC OR5 BR6 User’s peripheral Freescale Semiconductor, Inc... OR6 BR7 User’s peripheral OR7 BR10 DSPRAM Buffered PPC Buffered PPC Local PPC OR10 BR11 DSP Peripherals Local PPC OR11 PSDMR PSRT Init Value [hex] Bus 14600801 Base at 14600000, 8 bit port size, no parity, GPCM on PPC bus.
Freescale Semiconductor, Inc. Operating Instructions TABLE 4-4. Memory Controller Initialization for 100(50)a MHz Reg. MBMR Device Type QFALC - 4ch. T1/E1 Read Access Init Value [hex] Description 10015400 60x bus select, refresh disable, write to UPM RAM, Read loop execute 5 times, first RAM address. 10015418 60x bus select, refresh disable, write to UPM RAM, Write loop execute 5 times, RAM address begins at 18H. Exception Access 1001543c RAM address begins at 0x3c.
Freescale Semiconductor, Inc. Functional Description 5 - Functional Description In this chapter the ADS block diagram is described in detail. 5•1 Reset & Reset - Configuration Freescale Semiconductor, Inc... There are available reset sources on the MSC8101ADS: 1) Power-On-Reset and manual 2) Manual Hard-Reset 3) Manual Soft-Reset 4) JTAG/ONCE - Reset 5) MSC8101 internal Resets. See [4].
Freescale Semiconductor, Inc. Functional Description Hard-Reset configuration word. This configuration may be taken from an internal default, in case RSTCONF is negated during HRESET asserted or taken from the Flash memory (MS 8 bits of the data bus) or Altera deviceA in case RSTCONF signal is asserted along with HRESET.
Freescale Semiconductor, Inc. Functional Description TABLE 5-2. Hard Reset Configuration Word Data Bus Bits Prog Value [Bin] IRPC 8:9 ’00’ Interrupt pin configuration. NC/BADDR(29)/ IRQ2,NC/BADDR(30)/IRQ3,NC/BADDR(31)/ IRQ5 are selected as NC (not connect) DPPC 10:11 ‘00’ Data Parity Pin configuration as IRQ[1:7]. 12 ’0’ NMI interrupt is serviced by the core. ISB 13:15 ’000’ BMS 16 ’0’ Non-functional cleared bit.
Freescale Semiconductor, Inc. Functional Description 5•1•5 MSC8101 Internal Hard Reset Sources The MSC8101 has internal sources which generate Hard / Soft Resets. Among these sources are: 1) Loss of Lock Reset (Hard) 2) S/W Watch Dog Reset (Hard) 3) Bus Monitor (Hard) 4) JTAG/ONCE Reset (Hard) In general, the MSC8101 asserts a reset line HARD or SOFT for a period 512 clock cycles after the reset source has been identified.
Freescale Semiconductor, Inc. Functional Description FIGURE 5-1 Clock Distribution Scheme CY2309 A1 Zero Delay A2 Buffer MSC8101 CLOCK OSC. 55MHz/ 20MHz CLKIN CLKOUT VCC DLL_IN JP2 S2 VCC/ GND S1 SDRAM1 SDRAM2 B1 BCSR B2 MICTOR B3 EXPANSION A4 Freescale Semiconductor, Inc... U44 The Zero Delay Buffer CY2309 distributes high speed clock with skew less 250ps when internal PLL is ON.
Freescale Semiconductor, Inc. Functional Description ceivers are disabled during access to that region, avoiding possibleA contention over data lines. The MSC8101 chip-selects assignment to the various memories / registers on the MSC8101ADS are shown in TABLE 5-3. Freescale Semiconductor, Inc... TABLE 5-3.
Freescale Semiconductor, Inc. Functional Description assigned to a CS line according to TABLE 5-3. "MSC8101ADS Chip Select Assignments" on page 44. FIGURE 5-2 SDRAM Connection Scheme MT48LC2M32B2 x 2 CS2 RAS CAS WE Address MUX BNK1 A29 A0 A28 A27 Freescale Semiconductor, Inc... A(29:19) A2 A26 A(0:9) A3 A20 A19 BNK0 A1 PSDA10 3.
Freescale Semiconductor, Inc. Functional Description b. Two clocks latency setting is programmed for 50MHz Bus Clock c. 8 beat burst is programmed for 32bit Data Bus width (Host Interface is active) 5•6•2 SDRAM Refresh The SDRAM is refreshed using its auto-refresh mode. I.e., using SDRAM machine 1’s periodic timer, an auto-refresh command is issued to the SDRAM every 14 µsec, so that all 4096A SDRAM rows are refreshed within spec’d 57.3 msec, while leaving a 6.
Freescale Semiconductor, Inc. Functional Description FCS0 FCS1 FCSb BA7 FCS2 FCS3 BA8 Flash Type Detect Freescale Semiconductor, Inc... FIGURE 5-3 FLASH SIMM Connection Scheme FLASH SIMM BD(0:31) D(31:0) BA(9:29) A(22:0) BA(7:8) ADR Ext. BWE0 WE0 BWE1 WE1 BWE2 WE2 BWE3 WE3 BPOE OE BCSR FPD1 FPD2 FPD3 FPD4 FPD5 FPD6 FPD7 CS0 CS1 CS2 CS3 PD1 PD2 PD3 PD4 PD5 PD6 PD7 As can be seen in FIGURE 5-3, the FLASH CS is distributed to four CS signals.
Freescale Semiconductor, Inc. Functional Description 5•8 Communication Ports The MSC8101ADS is include several communication ports, to allow convenient evaluation of CPM "Highlights". Obviously, it is not possible to provide all types of communication interfaces supported by the CPM, but it is made convenient to connect communication interface devices to the MSC8101 via the CPM Expansion connectors, residing on the edge of the board.
Freescale Semiconductor, Inc. Functional Description TABLE 5-6. Ports Function Enable ADS On-Board Peripherals MSC8101 I/O Ports/Name QFALC on CODEC on T1/E1 T1/E1 T1/E1 T1/E1 TDMA1 TDMA1 TDMB2 TDMC2 TDMD2 PA6/TDMA1-L1RSYNC Fast Et ATM8 on on FCC2 FCC1 DMA Ext. Tool Possible Collision - - + + D + + + + D PA7/TDMA1-L1TSYNC PA8/TDMA1-L1RXD0 PA9/TDMA1-L1TXD0 D + + + + + + + + + + + + + + PA14/MIIRXD3/ATM8-RXD4 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Functional Description TABLE 5-6. Ports Function Enable ADS On-Board Peripherals MSC8101 I/O Ports/Name QFALC on CODEC on T1/E1 T1/E1 T1/E1 T1/E1 TDMA1 TDMA1 TDMB2 TDMC2 TDMD2 Fast Et ATM8 on on FCC2 FCC1 PC30/TDMA1-TXCLK(CLK2) + PC31/TDMA1-RXCLK(CLK1) + PD30/IDMA2-DRACK/IDMA2-DONE PD31/IDMA1-DRACK/IDMA1-DONE 5•8•1 DMA Ext. Tool Possible Collision - - + + + + D ATM Port Freescale Semiconductor, Inc... To support the MSC8101 ATM controller, a 155.
Freescale Semiconductor, Inc. Functional Description ethernet transceiver may be Disabled / Enabled at any time via the MII’s MDIO port. The LXT970 is able to interrupt the MSC8101, this via IRQ7~ line. This line is shared also with the CPM expansion connectors. Therefore, any tool that is connect to IRQ7 or IRQ6~ for that matter, should drive these lines only with an Open Drain buffer.
Freescale Semiconductor, Inc. Functional Description TABLE 5-7. CS4221 Programming Byte Num. Function Value 6 Converter Status 7 Master Clock 5•8•4 Meaning: - Read only ‘0’ Default. Crystal frequency is equal to 256x Fs T1/E1 Ports The QFALC framer supports four T1/E1 and contains analog and digital function blocks, which are configured and controlled by MSC8101.
Freescale Semiconductor, Inc. Functional Description to detect if a terminal is connected to the MSC8101ADS board. • DSRA ( O ) - Data Set Ready. This line is always asserted by the MSC8101ADS. • RTS ( I ) - Request To Send. This line is not connected in the MSC8101ADS. • CTS ( O ) - Clear To Send. This line is always asserted by the MSC8101ADS. 5•9 Host I/F Buffer/transceivers are 5V compliant. Host Port is also available via two row header 36 pins.
Freescale Semiconductor, Inc. Functional Description pansion Connector is using for off-board tools (ECOM,DMA e.g.) it’s necessary to avoid signal collisions. For this purpose Host I/F buffers should be disabled for external non-dedicated tools. The placement Host I/F signals is shown in the following table. TABLE 5-8. Host I/F Interconnect signals Freescale Semiconductor, Inc... Con/Pin No.
Freescale Semiconductor, Inc. Functional Description 4) 5) Freescale Semiconductor, Inc... 6) • Buffers Enable/Disable. • Device Reset. Host Interface which includes: • Buffers Enable/Disable • Host Acknowledge Enable ATM Port Control which includes: • Transceiver Enable / Disable • Device Reset. Fast Ethernet Port Control which includes: • Transceiver Initial Enable • Device Reset 7) RS232 port 1 Enable / Disable. 8) RS232 port 2 Enable / Disable.
Freescale Semiconductor, Inc. Functional Description TABLE 5-9. BCSR0 Description Freescale Semiconductor, Inc... BIT MNEMONIC Function PON DEF ATT. 2 HOSTTRI Host Request or Acknowledge Enable. When high host request/ acknowledge I/O obtains high impedance and external buffer is HI-Z if low this signal is enable via external buffer. 1 R,W 3 T1_1ENa T1/E1 channel 1 Enable. When asserted (low) T1/E1 QFALC framer channel 1 lines are connected to the CPM TDMA1 ports.
Freescale Semiconductor, Inc. Functional Description TABLE 5-10. BCSR1 Description Freescale Semiconductor, Inc... BIT MNEMONIC Function PON DEF ATT. 3 ATM_RST ATM Port Reset. When asserted (low), the ATM port transceiver is in reset state. This line is driven also by HRESET~ signal of the MSC8101. 1 R,W 4 FETHIEN Fast Ethernet Port Initial Enable. When asserted (low) the LXT970’s MII port, residing on FCC2, is enabled after Power-Up or after FETH_RST is negated.
Freescale Semiconductor, Inc. Functional Description TABLE 5-11. Peripheral’s Availability Decoding. BCSR Control Bits Freescale Semiconductor, Inc... Enable to: FETHIEN 1.4 T1_1EN 0.3 T1_234EN 0.4 CODEC_EN 1.1 CODECa x x x 0 T1/E1 channels 2-4 1 x 0 x FETH 0 x x x T1/E1 channel 1 x 0 x 1 a. Power-on default mode is enable for CODEC and disable for the rest peripherals.
Freescale Semiconductor, Inc. Functional Description TABLE 5-12. BCSR2 Description BIT 20 - 23 Function DEF SET ATT. BREVN(0:3) Board Revision Number (0:3). This field represents the revision code, hard-assigned to the ADS. See TABLE 5-18. "ADS Revision Encoding" on page 61, for revisions’ encoding. 0 R SWOPT2 Software Option 2. This is the LSB of the field. Shows the state of a dedicated dip-switch providing an option to manually change a program flow. For the setting of dip-switch see.
Freescale Semiconductor, Inc. Functional Description tion" on page 60. TABLE 5-15. BCSR3 Description Freescale Semiconductor, Inc... BIT MNEMONIC Function DEF SET ATT. 0 EE0 Emulation Enable 0. Shows the apropriate bit state of the emulation dipswitch providing an option to manually program debugging. 0 R 1 EE1 Emulation Enable 1. Same as EE0. 0 R 2 EE2 Emulation Enable 2. Same as EE0. 0 R 3 EE3 Emulation Enable 3. Same as EE0. 0 R 4 EE4 Emulation Enable 4. Same as EE0.
Freescale Semiconductor, Inc. Functional Description TABLE 5-16. EXTOOLI(0:3) Assignment EXTTOOLI(0:3) [hex] Freescale Semiconductor, Inc... 0 External Tool T/ECOM - Communication tool 1-C Reserved D DMA Tool E Future Host I/F Tool F External Tool is Not Present TABLE 5-17. External Tool Revision Encoding TOOLREV(0:3) [hex] External Tool Revision 0 ENGINEERING 1 PILOT 2 A 3 B 4-F Reserved TABLE 5-18.
Freescale Inc. PPCSemiconductor, Bus Memory Map 6 - PPC Bus Memory Map Freescale Semiconductor, Inc... All accesses to MSC8101 memory slaves is controlled by the its memory controller. Therefore, the memory map is reprogrammable to the desire of the user. After Hard Reset is performed by the debug station, the debugger checks for existance, size, delay and type of the FLASH memory SIMM mounted on board and initializes the memory controller accordingly.
Freescale Semiconductor, Inc. PPC Bus Memory Map and DMA. This memory map is a recommended memory map and since it is a "soft" map devices’ TABLE 6-1. MSC8101ADS Memory Map Device Name ADDESS RANGE Memory Type Freescale Semiconductor, Inc...
Freescale Inc. PPCSemiconductor, Bus Memory Map TABLE 6-1. MSC8101ADS Memory Map Device Name ADDESS RANGE Memory Type Host Interface Enable FE000000 - FFFFFFFF FF000000 - FFFFFFFF Freescale Semiconductor, Inc... FF800000 - FFFFFFFF Host Interface Disable (Default) Port Size 32M SIMM SM73288 or Flash SIMM 32 16M SIMM SM73248 or 8M SIMM SM73228 a. Mapped to fixed addresses in the SC140 core. Refer to the MSC8101 spec for complete description of the SC140’s Core internal memory map [4]. b.
Freescale Semiconductor, Inc. Power 7 - Power 7•1 Power rails. There 3 power buses with the MSC8101: 1)I/O -3.3V nominal 1)Internal Logic - 1.5V nominal. 2)PLL - 1.5V nominal. and there are 3 power buses on the MSC8101ADS: 1)5V bus 2)3.3V bus FIGURE 7-1 ADS Power Scheme P1 ADS Logic & Peripherals 5VExt JP3 Expansion Con. CODEC 5V0 3V3 F1 4A 0.9-2.2.V 5V P26 1V5 JS4 JS5 JS3 JS2 JS1 3V3IO 3.3+-10%V 1V5CR Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Power cation Maximum Current Consumption" below: TABLE 7-1. Off-Board Application Maximum Current Consumption Power Bus Max. Current 5V0 2A 3V3 1.5A To protect on-board devices against supply spikes, decoupling capacitors (typically 0.1µF) are provided between the devices’ power leads and GND, located as close as possible to the power leads, while 47 µF bulk capacitors are spread around. 7•1•1 5V Bus Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. APPENDIX A - MSC8101 Bill of Material MOTOROLA MSC8101ADS RevB User’s Manual For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. A•1 BOM In this section the MSC8101ADS’s RevB bill of material is listed according to their reference designation TABLE A-1. MSC8101ADS Bill Of Material Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. TABLE A-1. MSC8101ADS Bill Of Material Freescale Semiconductor, Inc... Reference Designation Part Description Manufacturer Part # C117 Capacitor 10uF, 10V, 10% SMD Size A, SPRAGUE 293D106X9010A2T C185,C186 Capacitor 47pF, 50V, 5% COG SMD Size 1206, Ceramic AVX 12065A470JATJ C188,C191,C204 Capacitor 1µF, 16V, 10%, X7R SMD Size 1206, Ceramic AVX 1206YC105KAT1A C209 Capacitor 100uF, 16V, 10% SMD Size D ,Tantalum AVX TAJD107K016R C22,C202 Capacitor 15uF, 6.
Freescale Semiconductor, Inc. TABLE A-1. MSC8101ADS Bill Of Material Freescale Semiconductor, Inc... Reference Designation Part Description Manufacturer Part # P12 Connector 8 pin, RJ45 Receptacle, Shielded, 90o MOLEX 43202_8110 P15,P16 Connector SMB Straight PCB Jack SUHNER 82SMB-50-0-1/111 P17,P18 Connector 6 pin, double, RJ45 Receptacle, Shielded, 90o MOLEX 43223-8128 P19,P21,P24 Connector Stereo Phone Jack I.
Freescale Semiconductor, Inc. TABLE A-1. MSC8101ADS Bill Of Material Freescale Semiconductor, Inc... Reference Designation Part Description Manufacturer Part # R34,R39,R48,R54,R63,R66, R67,R72,R73,R93,R96,R103, R108,R111,R119,R121,R209 Resistor 1 KΩ, 1%, SMD 0603, 0.1W DRALORIK D11 001KFCS R41,R42,R43,R44,R45,R46,R47 Resistor 1.5KΩ, 1%, SMD 1206, 1/4W RODERSTEIN D25 01K5FCS R49,R129,R135,R167 Resistor 22.1Ω, 1% SMD 0603, 0.1W RODERSTEIN D11 22R1FCS R50,R132,R229 Resistor 2.
Freescale Semiconductor, Inc. TABLE A-1. MSC8101ADS Bill Of Material Freescale Semiconductor, Inc... Reference Designation Part Description Manufacturer Part # R200 Resistor 8.45 KΩ, 1% SMD 1206, 1/4W RODERSTEIN D25-8K45FCS R201,R220 Resistor 5KΩ, 5% SMD 1206, 1/4W RCD BLU1206 5K (4.99K) 0.1% R97,R102,R105,R116,R126 Resistor 2.7 Ω, 1% SMD 1206, 1/4W RCD MC1206 2R74FT R211 Resistor 750 Ω, 1% SMD 1206, 1/4W RODERSTEIN D25 750RFCS R222 Resistor 47.5 KΩ 1% SMD 0603, 0.
Freescale Semiconductor, Inc. TABLE A-1. MSC8101ADS Bill Of Material Freescale Semiconductor, Inc... Reference Designation Part Description Manufacturer Part # U2 EPM7256A - 120 I/O, 256 Macrocell, 7 nsec propagation delay, EEPROM Based In System Programmable Logic Device, 144-pin TQFP ALTERA EPM7256ATC144 U3,U4,U11,U13,U21,U22,U23,U24, U48 Quad CMOS buffer with individual Output Enable. TSSOP pkg.
Freescale Semiconductor, Inc. TABLE A-1. MSC8101ADS Bill Of Material Reference Designation Freescale Semiconductor, Inc... U26 Part Description Manufacturer Part # Clock Generator 1.544MHz, 3.3V Supply, 4-pin M-TRON 1.544MHz. M3H16FCD Socket 8-pin SMD PRECIDIP 110-93-308-41-105 U27 Quad E1/T1 Framer PEB22554-HTV1.3, 144-pin QFP pkg. SIEMENS PEB22554-HT-V1.3 U28 Eight Transformers for Quad E1/T1 Ports, SMD PULSE ENG. T1142 U29,U30,U32 Rail-to-Rail Output Audio Amp.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MOTOROLA MSC8101ADS RevB User’s Manual For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. APPENDIX B - Support Information MOTOROLA MSC8101ADS RevB User’s Manual For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. 10 10 In this chapter all information needed for support, maintenance and connectivity to the MSC8101ADS is provided. B•1 Interconnect Signals Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. Expansion - Interconnect Signals" below: TABLE B1-2. P1 - System Expansion - Interconnect Signals Freescale Semiconductor, Inc... Pin No. Signal Name Attribute Description O Expansion Address (16a:31). This is a Latched-Buffered version of the MSC8101’s PPC Address lines (16:31), provided for external tool connection. To avoid reflection these lines are series terminated with 43 Ω resistors. N.C. - Not connected. A19 EXPDVALb I/O, T.S.
Freescale Semiconductor, Inc. TABLE B1-2. P1 - System Expansion - Interconnect Signals Pin No. A26 Signal Name 5V0 Attribute P A27 Description +5V Supply. Connected to ADS’s 5V plane. Provided as power supply for external tool. For allowed current draw, see TABLE 7- 1. "Off-Board Application Maximum Current Consumption" on page 66. A28 A29 A30 A31 Freescale Semiconductor, Inc... A32 B1 GND P Digital Ground. Connected to main GND plane of the ADS. B4 TSTAT0 I,P.U.
Freescale Semiconductor, Inc. TABLE B1-2. P1 - System Expansion - Interconnect Signals Pin No. B21 Signal Name V3.3 Attribute P B22 B23 3.3V Power Out. These lines are connected to the main 3.3V plane of the MSC8101ADS, this, to provide 3.3V power where necessary for external tool connected. The amount of current allowed to be drawn from this power bus is found in TABLE 7-1. "Off-Board Application Maximum Current Consumption" on page 66. B24 B25 N.C. - Not Connected B26 5V0 P 5V Supply.
Freescale Semiconductor, Inc. TABLE B1-2. P1 - System Expansion - Interconnect Signals Freescale Semiconductor, Inc... Pin No. Signal Name Attribute Description C11 IRQ6b I,P.U. Interrupt Request 6 . Connected to MSC8101‘s DP6//IRQ6b/ DACK3 signal. Pulled up on the ADS with a 10 KΩ resistor. This line is shared with the ATM UNI’s interrupt line and therefore, when driven by an external tool, MUST be driven with an Open Drain gate.
Freescale Semiconductor, Inc. TABLE B1-2. P1 - System Expansion - Interconnect Signals Pin No. Signal Name Attribute Description C32 N.C. - Not Connected D1 GND P Digital Ground. Connected to main GND plane of the ADS. D4 EXPWE0b O D5 EXPWE1b Expansion Write Enable (0:1) (L). This are buffered GPCM Write Enable lines (0:1). They are meant to qualify writes to GPCM controlled 8/16 data bus width memory devices. This to provide eased access to various communication transceivers.
Freescale Semiconductor, Inc. TABLE B1-2. P1 - System Expansion - Interconnect Signals Pin No. D16 Signal Name Attribute GND P Description Digital Ground. Connected to main GND plane of the ADS. D17 D18 D19 D20 D21 Freescale Semiconductor, Inc... D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 a. MS Bit. B•1•2 MSC8101ADS’s P2 - CPM Expansion Connector P4 is a 128 pin, 900 , DIN 41612 connector, which allows for convenient expansion of the MPC8101’s serial and host ports.
Freescale Semiconductor, Inc. TABLE B1-3. P2 - CPM Expansion - Interconnect Signals Freescale Semiconductor, Inc... Pin No. Signal Name Attribute Description A13 SPISELb(PD19) I/O, T.S. When SPI port is enabled, this signal is the select input line for that port. When this port is disabled, this signal may be used to any available alternate function for PD19. In fact, for the ADS application using as GPIO output pin. A14 SPICLK(PD18) I/O, T.S.
Freescale Semiconductor, Inc. TABLE B1-3. P2 - CPM Expansion - Interconnect Signals Freescale Semiconductor, Inc... Pin No. Signal Name Attribute Description B2 ATMTCAb (PA30) I/O, T.S. ATM Transmit Cell Available (H). When this signal is asserted (High), while the ATM port is enabled, it indicates that the transmit FIFO of the PM5350 is empty and ready to except a new cell. When negated, it may show either that the transmit FIFO is Full or close to Full, depending on PM5350 internal programming.
Freescale Semiconductor, Inc. TABLE B1-3. P2 - CPM Expansion - Interconnect Signals Freescale Semiconductor, Inc... Pin No. Signal Name Attribute Description I/O, T.S. ATM Receive Data (7c:0). When the ATM port is enabled, this bus carries the cell octets, read from the PM5350 receive FIFO. This lines are updated on the rising edge of ATMRFCLKb. When the ATM port is disabled, these lines are tristated and may be used for any available respective function.
Freescale Semiconductor, Inc. TABLE B1-3. P2 - CPM Expansion - Interconnect Signals Freescale Semiconductor, Inc... Pin No. Signal Name Attribute Description C3 FETHTXEN (PB29) I/O, T.S. Fast-Ethernet Transmit Enable (H). The MSC8101 will assert (High) this line, to indicate data valid on the FETHTXD(3:0) lines. When the Fast-Ethernet port is disabled, this line may be used for any available function of PB29. C4 FETHRXER (PB28) I/O, T.S. Fast-Ethernet Receive Error (H).
Freescale Semiconductor, Inc. TABLE B1-3. P2 - CPM Expansion - Interconnect Signals Freescale Semiconductor, Inc... Pin No. Signal Name Attribute Description I/O, T.S. Host Interface Bidirectional Data Port D0-D13. Present as well as at P4 connector. C15 HD0 C16 HD1 C17 HD2 C18 HD3 C19 HD4 C20 HD5 C21 HD6 C22 HD7 C23 HD8 C24 HD9 C25 HD10 C26 HD11 C27 HD12 C28 HD13 C29 ATMRCLK O, T.S. ATM Receive Clock.
Freescale Semiconductor, Inc. TABLE B1-3. P2 - CPM Expansion - Interconnect Signals Freescale Semiconductor, Inc... Pin No. Signal Name Attribute Description D5 CLK5 (PC27) I/O, T.S. Clock 5 input. When TDMB is enabled this pin is an input clock. When TDMB port is disabled this line may be used for any available function of PC27 Port C. D6 ATMFCLK (PC26) I/O, T.S. ATM Transmit FIFO Clock.
Freescale Semiconductor, Inc. TABLE B1-3. P2 - CPM Expansion - Interconnect Signals Freescale Semiconductor, Inc... Pin No. Signal Name Attribute Description D20 FETHMDIO (PC12) I/O, T.S. Fast-Ethernet Port Management Data I/O. This signal serves as bidirectional serial data line, qualified by FETHMDC, to allow read / write the LXT970’s internal registers. When the Ethernet port is disabled, this line may be used for any available function of PC12. D21 HREQTRQ O, T.S.
Freescale Semiconductor, Inc. B•1•3 P3 - Altera’s In System Programming (ISP) This is a 10 pin generic 0.100" pitch header connector, providing In System Programming capability for Altera CPLD devices made programmable logic on board. The pinout of P3 is shown in TABLE B1-4. "P3 - ISP Connector - Interconnect Signals" below: TABLE B1-4. P3 - ISP Connector - Interconnect Signals Freescale Semiconductor, Inc... Pin No. Signal Name Attribute Description 1 TCK I ISP Test port Clock.
Freescale Semiconductor, Inc. TABLE B1-5. P4 - Host Interface Connector - Interconnect Signals Freescale Semiconductor, Inc... Pin No. Signal Name 3 HD0 4 HD1 5 HD2 6 HD3 7 HD4 8 HD5 9 HD6 10 HD7 11 HD8 12 HD9 13 HD10 14 HD11 15 HD12 16 HD13 17 HD14 18 HD15 19 Attribute Description I/O, T.S. Host Interface Bidirectional Data Port HD(0:15). GND P Digital GND. Main GND plane. 21 HA0 I Host Interface Address Line HA(0:3).
Freescale Semiconductor, Inc. TABLE B1-5. P4 - Host Interface Connector - Interconnect Signals Pin No. Signal Name Attribute 30 HDS I 31 HRESETb I/O, P.U Description Host Data Strobe or Host Write Data Strobe. For further explanation see P2/A24 in TABLE B1-3. "P2 - CPM Expansion - Interconnect Signals" above. MSC8101’s Hard Reset. For further explanation see P1/C10 in TABLE B1-2. "P1 - System Expansion - Interconnect Signals" above. 32 PORSTb I/O, P.U Power-On-Reset.
Freescale Semiconductor, Inc. TABLE B1-6. P6 - JTAG/ONCE Connector - Interconnect Signals Freescale Semiconductor, Inc... Pin No. Signal Name Attribute Description 9 RST I/O,P.U. In fact, HRESETb. When asserted by an external H/W, generates Hard-Reset sequence for the MSC8101. During that sequence, asserted by the MSC8101 for 512 system clocks. Pulled Up on the ADS using a 1KΩ resistor. When driven by an external tool, MUST be driven with an Open Drain gate.
Freescale Semiconductor, Inc. Connectors Interconnect Signals" below TABLE B1-8. P17,P18 - T1/E1 Line Connectors Interconnect Signals Freescale Semiconductor, Inc... Pin No. Signal Name Description A1 RX1+ Twisted-Pair Receive Data 1-ch. positive input from the MSC8101ADS. A2 RX1- Twisted-Pair Transmit Data 1-ch. positive input from the MSC8101ADS. A3 GND Digital Ground plane. A4 TX1+ Twisted-Pair Transmit Data 1-ch. positive output from the MSC8101ADS.
Freescale Semiconductor, Inc. B•1•12 P26 - 5V Power Supply Connectors See FIGURE 3-4, "P26: +5V Power Connector" on page 21 . B•1•13 P27A,B - RS232 Ports’ Connectors The RS232 ports’ connectors - PA3 and PB3 are 9 pin, 90o, female D-Type Stacked connectors, signals of which are presented in TABLE B1-10. "P27A Interconnect Signals" and TABLE B1-11. "P27B Interconnect Signals" TABLE B1-10. P27A Interconnect Signals Freescale Semiconductor, Inc... Pin No.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. B-96 MSC8101ADS RevB User’s Manual For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. APPENDIX C - Program Information MOTOROLA MSC8101ADS RevB User’s Manual For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. The MSC8101 has one programmable logic device - Altera CPLD, serving control and stasus function on the ADS. It implemented an U2 EPM7128ATC144-7. The design is done in AHDL program format and is listed below: Freescale Semiconductor, Inc... 20 20 C-98 MSC8101ADS RevB User’s Manual For More Information On This Product, Go to: www.freescale.
Freescale Semiconductor, Inc. C•1 Logic Equations C•1•1 First Include File %*********************bcsrA.inc ************************************% % TITLE % Written by Yehuda Palchan - November , 1999 “MSC8101 ADS Board Control and Status Register.”; % % % This file defines the Constant declarations used by the BCSR % %*******************************************************************% -- The reserved lines are granted with ACTIVE/NOT ACTIVE states.
Freescale Semiconductor, Inc. C•1•2 Second Include file %*********************ResetEnsure.tdf ******************************% % TITLE % Written by Yehuda Palchan - February , 2000 “MSC8101 ADS Board Control and Status Register.”; % % % This file defines the Reset Ensure State Machine % %*******************************************************************% SubDesign Reset_Ensure ( Clk: INPUT; Reset: INPUT; PushBtn : INPUT; Rst_True: OUTPUT; ) Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. C•1•3 Main File %*********************bcsr.tdf ***************************************% TITLE % “MSC8101ADS Board Control and Status Register.”; Written by Dragilev Lev, MSIL % % Rev B Version Release 1.0 31/10/2002 % % This file declares the BCSR registers and their functions % % It also controlls the Codec, Flash, RS232, T1/E1 Framer,Host % % Interface and ATM devices. % % Modifid from rev2.1 (MSC8101revA source) % Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc. CONSTANT TCPC_DEFAULT0 = 1; CONSTANT TCPC_DEFAULT1 = 0; CONSTANT BC1PC_DEFAULT0 = 0; CONSTANT BC1PC_DEFAULT1 CONSTANT RSVHR26 = 0; = 0; -- CONSTANT DLLDIS_DEFAULT= 0; CONSTANT RSVHR31 SUBDESIGN -- Get value from DIP-Switch = 0; bcsr ( clock, ExtClk, -- External/Osc clock for EEinit (BCSR3) CS1~, -- BCSR SELECT From DSP W_R~, A[27..29], A7,A8 -- Flash address Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. SBOOTEN_OUT~, -- Enable Boot to serial EEPROM F_CS1~, F_CS2~, F_CS3~, F_CS4~, -- External FLASH memory chip-selects 1,2,3,4 SPARE1 : OUTPUT; %****************************% % Host Interface Definition % %****************************% HDI_EN~, Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. D[0..7] : BIDIR; -- Bidirectional 8-bit wide Data Bus DUMMY : BIDIR; -- Blank - Schematic’s bug workaround ) VARIABLE Bcsr0[0..SIZE0], Bcsr1[0..SIZE1], Bcsr4[2..SIZE4], -- BCSR4 is utilized for MODCK reconfig - Service Register 1 Bcsr5[0..SIZE5], -- BCSR5 is utilized to program synthesizer - Service Register 2 Bcsr6[0..
Freescale Semiconductor, Inc. SCND_CFG_BYTE_READ, THIRD_CFG_BYTE_READ, FOURTH_CFG_BYTE_READ, F_PD[4..1], T1_EN_OUT_NODE, T234_EN_OUT_NODE, CODECEN_OUT_NODE, FETHIEN_OUT_NODE, CONF_ADD[0..1],-- CONFIGURATION ADDRESS CFG_BYTE0[0..7], CFG_BYTE1[0..7], CFG_BYTE2[0..7], CFG_BYTE3[0..7], END_OF_FLASH_READ,-- “1” if DSP has ended Flash reading Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. * BCSR3 * ********************************************************************************% EE0_node, EE1_node, EE2_node, EE3_node, EE4_node, EE5_node, EED_node, RSV3_7, %******************************************************************************** * BCSR4 - Write Register * Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. SoftReset~, -- Soft Reset internal HRD_HRWd -- Delayed Host RD/WR : NODE; BEGIN DEFAULTS Data_Buff[].oe = GND; -- Data Bus Output disable DivEn.clrn = VCC; END DEFAULTS; RESETi = !HARD_RESET_ACTIVE~ or REGULAR_POWER_ON_RESET; ( HOSTCSP,HOSTRQAC,HOSTTRI, T1_1EN~,T1_234EN~,FrmRst~,SIGNAL_LAMP_0~,SIGNAL_LAMP_1~) = Bcsr0[0..SIZE0].q; ( SBOOT_EN~,CODEC_EN~,ATM_EN~,ATM_RST~,FETHIEN~,FETH_RST~,RS232EN_1~,RS232EN_2~) = Bcsr1[0..SIZE1].q; ( Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. ATM_RST_PON_DEFAULT,FETHIEN_PON_DEFAULT,FETH_RST_PON_DEFAULT, RS232_1_ENABLE_PON_DEFAULT,RS232_2_ENABLE_PON_DEFAULT); ------------------- BCSR3 -- -----------------BCSR3_PON_CONST[] = (EE0_PON_DEFAULT,EE1_PON_DEFAULT,EE2_PON_DEFAULT, EE3_PON_DEFAULT,EE4_PON_DEFAULT,EE5_PON_DEFAULT, EED_PON_DEFAULT,RSV3_7_PON_DEFAULT); FOR i IN 0 to SIZE0 GENERATE IF(BCSR0_PON_CONST[i]) THEN BCSR0_PON_DEF[i] = VCC; ELSE BCSR0_PON_DEF[i] = GND; END IF; Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. WE0Spare.clk = GLOBAL(clock); SyncTEA.d = VCC; -- for optional use TEA~ = OPNDRN(SyncTEA.q); FlashOE.d= VCC; BPOE~= OPNDRN(FlashOE); PSDVAL~ = OPNDRN(VCC); WE0Spare.d= VCC; WE0 = OPNDRN(WE0Spare); %************************************* EE PINS *************************************% EE0_HOLD.aclr = !HRESET~; EE0_HOLD_END = (EE0_HOLD.q[] == EE0_HOLD_VALUE); -- terminal count Freescale Semiconductor, Inc... IF(EE0_HOLD_END & HRESET~) THEN EE0_HOLD.
Freescale Semiconductor, Inc. ELSE HRD_SHIFT.aclr = GND; END IF; HRD_SHIFT.shiftin= HRD_HRW;--LOAD SHIFT REGISTER HRD_HRWd= HRD_SHIFT.
Freescale Semiconductor, Inc. END IF; % ************************* ** BCSR1 Write Operation ** ************************* % IF (RESETi) THEN Bcsr1[].d = BCSR1_PON_DEF[]; --Load default values when Reset ELSIF (MPC_WRITE_BCSR_1) THEN Bcsr1[0..SIZE1].d = D[0..SIZE1]; --Read the Data Bus ELSE Bcsr1[].d = Bcsr1[].q; END IF; % ********************************************* Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. -- Assign Configuration Word: FROM_FLASH_CNFG_WORD = (F_CFG_EN~ == GND); FROM_HOST_CNFG_WORD -- Config word was loaded from data bus = (HOSTCFG~ == GND); CFG_BYTE0[0..7]= (EARB_DEFAULT,EXMC_DEFAULT,IRQ7INT~_DEFAULT,EBM_DEFAULT,BPS_DEFAULT0,BPS_DEFAULT1, SCDIS_DEFAULT,ISPS_DEFAULT); CFG_BYTE1[0..7]= (IRPC_DEFAULT0,IRPC_DEFAULT1,DPPC_DEFAULT1,DPPC_DEFAULT0,NMIOUT_DEFAULT,ISB_DAFAULT0, ISB_DAFAULT1,ISB_DAFAULT2); CFG_BYTE2[0..
Freescale Semiconductor, Inc. (EE0_node,EE1_node,EE2_node,EE3_node,EE4_node,EE5_node,EED_node ,RSV3_7); ELSIF (MPC_READ_BCSR_4) THEN Data_Buff[].oe = VCC; Data_Buff[0..SIZE4].in = ((!F_CFG_EN~),DLLDIS,Bcsr4[2..SIZE4].q); ELSIF (MPC_READ_BCSR_5) THEN Data_Buff[].oe = VCC; Data_Buff[0..SIZE5].in = Bcsr5[0..SIZE5].q; ELSIF (MPC_READ_BCSR_6) THEN Data_Buff[].oe = VCC; Data_Buff[0..SIZE6].in = Bcsr6[0..SIZE6].q; -- Assign Default Configuration Word onto Data Bus: ELSIF (FIRST_CFG_BYTE_READ) THEN Data_Buff[].
Freescale Semiconductor, Inc. * Buffers Enable & ATM Chip Select ****************************************************************************** % DATA_HOLD_END = (DATA_HOLD.q[] == DATA_HOLD_VALUE); -- terminal count IF(DATA_HOLD_END & DSyncHardReset) THEN DATA_HOLD.cnt_en = GND; -- Disable count after term value ELSE DATA_HOLD.cnt_en = VCC; END IF; END_OF_FLASH_READ = !PSDVal~ & !F_CS0~ & !W_R~ & DSyncHardReset; -- end of flash read cycle.
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc. -- with default MODCK setting from DIP-Switch -- PONRESET pulse resets while WD. -- Implemented as ripple counter with 30 stages -- WDEn.s = GND; WDEn.r = GND; -- WDEn.prn = !(MPC_WRITE_BCSR_4 & (D[0..1] == B”10”)); -- Preset to FF when write b’10 bit to BCSR4 -- WDEn.clrn = !END_OF_WD_TIMER & !MPC_READ_BCSR_4 & PRST~; CLEAR_TO_WD_CTRL = LCELL (PRST~); StartStopWD.clrn = CLEAR_TO_WD_CTRL; StartStopWD.clk = !(MPC_WRITE_BCSR_4 & (D[0..1] == B”01”)); StartStopWD.