MSC8101 USER’S GUIDE 16-Bit Digital Signal Processor MSC8101UG/D Revision 1, June 2001
EOnCE is a registered trademark of Motorola, Inc. StarCore, PowerQUICC II, Motorola, and the Motorola logo are trademarks of Motorola, Inc. The PowerPC name is a trademark of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. Motorola reserves the right to make changes without further notice to any products herein.
MSC8101 Overview 1 Reset Configuration and Boot 2 Optimizing Memory on the SC140 Core 3 Connecting External Memories and Memory-Mapped Devices 4 Balancing Between the PowerPC System and Local Buses 5 DMA Channels 6 Interrupts and Interrupt Priorities 7 Host Interface (HDI16) 8 Enhanced Filter Coprocessor (EFCOP) 9 Multi-Channel Controllers (MCCs) 10 Serial Peripheral Interface (SPI) 11 EOnCE/JTAG 12 Programming Reference A Glossary B Bootloader Program C Acronyms and Abbreviati
1 MSC8101 Overview 2 Reset Configuration and Boot 3 Optimizing Memory on the SC140 Core 4 Connecting External Memories and Memory-Mapped Devices 5 Balancing Between the PowerPC System and Local Buses 6 DMA Channels 7 Interrupts and Interrupt Priorities 8 Host Interface (HDI16) 9 Enhanced Filter Coprocessor (EFCOP) 10 Multi-Channel Controllers (MCCs) 11 Serial Peripheral Interface (SPI) 12 EOnCE/JTAG A Programming Reference B Glossary C Bootloader Program D Acronyms and Abbrevia
Contents Preface Before Using This Manual—Important Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx Audience and Helpful Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx Notational Conventions and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi Other MSC8101 Documentation .
Contents 1.3.7.6 1.3.7.7 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.5 RxBD Processing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TxBD Processing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSC8101 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Media (Voice/Fax/Data) Over Packet Gateway (ATM/FR/IP) . . . . . . . . . . . . . . 3G Infrastructure Cellular BTS . . . . . . . . . . . . . .
Contents 4.3.1 4.3.2 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.5 4.5.1 4.5.2 4.6 GPCM Hardware Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Single-Bus Mode GPCM-Based Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Connecting the Bus to the SDRAM Memory Interface. . . . . . . . . . . . . . . . . . . . . . . . 4-7 Single-Bus Mode SDRAM Hardware Interconnect . . . . . . . . . . . . . . . . . . . . . . .
Contents 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.6 DMA Internal/External Mask Registers (DIMR/DEMR) . . . . . . . . . . . . . . . . . . . 6-9 DMA Channel Parameters RAM (DCPRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 FIFO Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Multiple Pending DMA Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 8.3.1.3 8.3.1.4 8.3.2 8.3.3 8.3.4 8.4 8.5 Host Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Ready bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSP Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.4 10.4.1 10.4.2 10.5 10.6 Set Up the Global MCC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Up the MCC Configuration and Control Registers . . . . . . . . . . . . . . . . . . . Set Up Channel-Specific Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set Up the Channel Extra Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialize Circular Interrupt Queues . . . . . .
Contents APPENDIXES: Appendix A Programming Reference A.1 A.2 Interrupt Sources and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents xii MSC8101 User’s Guide
Figures Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 1-6. Figure 1-7. Figure 1-8. Figure 1-9. Figure 1-10. Figure 1-11. Figure 1-12. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 3-1. Figure 3-2. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 4-8. Figure 4-9. Figure 4-10. Figure 4-11. Figure 4-12. Figure 4-13. MSC8101 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures Figure 4-14. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6. Figure 5-7. Figure 5-8. Figure 6-1. Figure 6-2. Figure 6-3. Figure 6-4. Figure 6-5. Figure 6-6. Figure 6-7. Figure 6-8. Figure 6-9. Figure 7-1. Figure 7-2. Figure 8-1. Figure 8-2. Figure 8-3. Figure 8-4. Figure 8-5. Figure 9-1. Figure 9-2. Figure 10-1. Figure 10-2. Figure 10-3. Figure 10-4. Figure 10-5. Figure 10-6. Figure 10-7. Figure 10-8. Figure 10-9. Figure 11-1. Figure 11-2.
Figures Figure 11-3. Figure 11-4. Figure 11-5. Figure 12-1. Figure 12-2. Figure 12-3. Figure 12-4. Figure 12-5. Figure 12-6. Figure 12-7. Figure 12-8. Figure 12-9. Figure 12-10. SPI as a Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 SPI as Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 SPI Response to Multi-Master Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures xvi MSC8101 User’s Guide
Tables Table 1-1. Table 1-2. Table 1-3. Table 1-4. Table 1-5. Table 1-6. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 4-1. Table 4-2. Table 4-3. Table 5-1. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 7-1. Table 7-2. Table 7-3. Table 7-4. Table 8-1. Table 8-2. Table 8-3. Table 8-4. Table 8-5. Table 8-6. MSC8101 Serial Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables Table 8-7. Table 8-8. Table 8-9. Table 8-10. Table 8-11. Table 8-12. Table 8-13. Table 8-14. Table 8-15. Table 8-16. Table 8-17. Table 8-18. Table 8-19. Table 8-20. Table 8-21. Table 9-1. Table 9-2. Table 10-1. Table 10-2. Table 10-3. Table 10-4. Table 11-1. Table 11-2. Table 12-1. Table 12-2. Table 12-3. Table 12-4. Table 12-5. Table 12-6. Table A-1. Table A-2. Table A-3. Table A-4. xviii Transfer Control in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About This Book The MSC8101 device is the first Motorola product based on the SC140 DSP core introduced by the StarCoreTM Alliance. It addresses the challenges of the networking market. The benefits of the MSC8101 include not only a very high level of performance but also a product design that enables effective software development and integration.
Before Using This Manual—Important Note Before Using This Manual—Important Note This manual explains how to program the MSC8101. The information in this manual is subject to change without notice, as described in the disclaimers on the title page of this manual. Before using this manual, determine whether it is the latest revision and whether there are errata or addenda.
Organization Active low signals Signal names of active low signals appear in small capital letters in a sans serif typeface, with an overbar: DBG, AACK, and EXT_BG[2]. x A lowercase italicized x in a register or signal name indicates that there are multiple registers or signals with this name. For example, BRCGx refers to BRCG[1–8], and MxMR refers to the MAMR/MBMR/MCMR registers. On the MSC8101, the SC140 core is a 16-bit DSP processor and the CPM contains a 32bit RISC processor.
Organization ■ Chapter 4, Connecting External Memories and Memory-Mapped Devices. Memory interconnection options for the bus and memory controller; hardware connections and memory register settings for the MSC8101 when the PowerPC system bus is connected to Flash EPROM, Synchronous DRAM, or an MSC8101 HDI16 slave ■ Chapter 5, Balancing Between the MSC8101 PowerPC System and Local Buses. The functions of these two buses and the interaction of these buses. ■ Chapter 6, DMA Channels.
Other MSC8101 Documentation Other MSC8101 Documentation ■ MSC8101 Programmer’s Quick Reference. A hands-on reference to the pins, registers, and instructions of the MSC8101; includes a memory-map table, interrupt flow diagram, and port error exceptions. ■ MSC8101 Programmer’s Reference Manual. Describes the MSC8101 architecture and functionality in detail, with a chapter on each of the MSC8101 blocks. ■ MSC8101 Data Sheet.
Further Reading xxiv MSC8101 User’s Guide
Chapter 1 MSC8101 Overview The Motorola MSC8101 is a versatile, one-chip integration of a high-performance StarCore SC140 core, large on-device memory (0.5 MB), a communications processor module (CPM), a very flexible system interface unit (SIU), and a 16-channel DMA controller. The MSC8101 is the first member of the family of programmable digital signal processors (DSPs) based on the SC100 DSP cores. The SC140 core is the four-ALU flavor of the StarCore SC100 DSP core family.
MSC8101 Overview (ATM, Ethernet, IP). The MSC8101 performs digital signal processing tasks such as speech compression, echo cancellation, fax or modem data pump, error correction/data compression (ECDC), or even real-time protocol (RTP). Furthermore, the MSC8101 performs the network interface task (using the CPM), thus removing bottlenecks in these systems. 1.2 Features The following sections give an overview of MSC8101 features. 1.2.
Features 1.2.2 On-Device Memories ■ Total of 512 KB (256 K × 16-bit words) unified on-device RAM ■ 2 KB bootstrap ROM 1.2.
MSC8101 Overview 1.2.6 On-Device Peripherals ■ Enhanced 16-bit parallel host interface (HDI16) supports a variety of buses and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs ■ Enhanced filter coprocessor (EFCOP) is a 300 MHz 32 x 32 bit filtering and echo-cancellation coprocessor that runs in parallel to the SC140 core 1.2.
Features ■ Four full-duplex serial communication controllers (SCCs) supporting IEEE 802.3/Ethernet, high-level synchronous data link control, HDLC, local talk, UART, Synchronous UART, BISYNC, and transparent operations. Two SCCs have dedicated pins; the other two can operate only in TDM mode.
MSC8101 Overview 1.2.11 Packaging ■ 332-pin 0.8 mm pitch ■ 17 × 17 mm flip chip plastic ball grid array (FCPBGA) 1.2.
Architecture contains two address arithmetic units (AAUs), one bit mask unit (BMU), and one branch unit. Overall, the SC140 can issue and execute up to six instructions per clock—for example, four independent arithmetic instructions and two pointer-related instructions (such as moves or other operations on addresses). At its initial clock speed of 300 MHz, the SC140 can therefore execute 1200 true DSP MIPS—1.
MSC8101 Overview • • • Other Peripherals ‘MCC’ / UART / HDLC / Transparent / Ethernet / FastEthernet / ATM / SCCs TDMs Serial Interface and TSA UTOPIA Interface MII PowerPC™ System 64-bit Bus CPM Interrupt Controller 3 x FCC MEMC Timers Parallel I/O 2 x MCC DMA Engine Baud Rate Generators 4 x SCC PIT System Protection Reset Control Clock Control PowerPC 64/32-bit System Bus Dual Ported RAM 2 x SMC Bridge SPI SIU 2 x SDMA I2 C ® RISC Extended Core Address Register File Program Seq
Architecture ■ A memory controller supporting eight external memory banks. The memory controller, which is based on the MPC8260 memory controller, supports UPMs as well as an SDRAM machine with page mode and address data pipeline. ■ A bus monitor that prevents PowerPC system bus lock-ups, a real-time clock, a periodic interrupt timer, and other system functions useful in embedded applications. 1.3.
MSC8101 Overview 1.3.6 Enhanced Filter Coprocessor (EFCOP) The EFCOP performs filtering operations vital to such DSP tasks as echo cancellation. These filtering operations include both adaptive and non-adaptive FIR and IIR filtering with 32-bit precision (the EFCOP contains a 32-bit × 32-bit multiply unit and 72-bit accumulator). The EFCOP’s hardwired circuitry performs one FIR filter tap per clock cycle, drawing very little power. The EFCOP can also update coefficients in an adaptive filter.
Architecture The MCC also supports super channels of rates higher than 64 Kbps and subchanneling of the 64 Kbps channels. ■ Four full-duplex serial communication controllers (SCCs) supporting IEEE802.3/Ethernet, synchronous data link control, high-level data link control protocol (HDLC), local talk, UART, Synchronous UART, BISYNC, and transparent mode. Two SCCs have dedicated pins; the other two can operate only in TDM mode.
MSC8101 Overview 1.3.7.2 CPM Configurations The CPM comprises many different functional blocks and offers flexibility in configuring the device for specific applications. The functions described in the preceding sections are all available in the device, but not all of them can be used at the same time. This does not mean that the device is not fully activated in any given implementation. The CPM architecture uses common hardware resources for many different protocols and applications.
Architecture 1.3.7.3 Buffer Descriptors If you are programming the CPM serial controllers, you need to know how the serial controllers use buffer descriptors to define buffer allocation. A buffer descriptor (BD) contains the essential information about each buffer in memory. Each buffer is referenced by a BD that can reside anywhere in dual-port RAM.
MSC8101 Overview BD.bd_cstat.bit Table 1-3. Buffer Descriptor Naming Conventions BD RxBD/TxBD Field Example bd_cstat TxBD.bd_cstat. R refers to the ready bit in the TxBD’s status and control field. Refer to the MSC8101 Reference Manual for the protocol’s status and control field bit definition. bd_length RxBD.bd_length refers to RxBD’s data length field. bd_addr RxBD.bd_addr refers to RxBD’s buffer pointer field.
Architecture these channels. The exact definition of the parameter RAM, which differs for each protocol, is provided in the MSC8101 Reference Manual. Table 1-5 shows the MSC8101 parameter RAM structure. The parameters for the SCCs, FCCs, and MCCs are stored in the parameter RAM. The parameters for the SMCs, SPI, and I2C are stored in locations to which the user-programmable values in the parameter RAM point. For example, IMM+$8200 contains the SCC3 parameters.
MSC8101 Overview Table 1-5. MSC8101 Parameter RAM Structure (Continued) Offset from IMM Peripheral Size (Bytes) Offset from IMM Peripheral Size (Bytes) 0x8800 MCC2 128 0x8B00 Reserved 1280 0x8880 Reserved 124 0x88FC SMC2_BASE 2 0x88FE Reserved 2 Table 1-6 shows the parameter RAM for all SCC protocols. You must initialize entries with boldfaced names before the SCC can be enabled. Refer to the MSC8101 Reference Manual for the protocol-specific parameters. Table 1-6.
Architecture Table 1-6. SCC Parameter RAM (Continued) Offset from SCC Base1 Name Width 0x24 — 32-bits Tx temp. For CP use only. 0x28 RCRC 32-bits 0x2C TCRC 32-bits Temp receive/transmit cyclic redundancy check (CRC). Does not need to be accessed for normal operation but may be helpful for debugging. 0x30 — NOTES: 1. Description Protocol-specific area. SCC base is IMM+0x8000. Refer to Table 1-5 1.3.7.
MSC8101 Overview RxBDs IMM+0x0000 Dual-Port RAM SCC2 RxBD Table RxBD.bd_cstat SCC2 TxBD Table RxBD.bd_length External Memory RxBD.bd_addr TxBDs Rx Buffer TxBD.bd_cstat TxBD.bd_length SCC2 Parameters TxBD.bd_addr Tx Buffer RBASE IMM+0x8100 SCC2 Parameter RAM TBASE RFCR TFCR MRBLR RSTATE RBPTR TSTATE TBPTR RCRC TCRC protocolspecific Figure 1-3. Example SCC2 BD and Buffer Memory Structure 1.3.7.6 RxBD Processing Example Figure 1-5 shows how the RxBD is processed in SCC UART mode.
Architecture RxBDs Dual-Port RAM IMM+0x0000 SPI RxBD Table RxBD.bd_cstat SPI TxBD Table RxBD.bd_length External Memory RxBD.bd_addr TxBDs SPI Parameter Table Rx Buffer TxBD.bd_cstat TxBD.bd_length SPI Parameters TxBD.bd_addr Tx Buffer RBASE IMM+0x8100 TBASE SPI_BASE RFCR TFCR MRBLR RSTATE RBPTR TSTATE TBPTR Figure 1-4. Example SPI BD and Buffer Memory Structure If RxBD.bd_cstat.E is cleared, the current buffer is not empty, and it reports a busy error.
MSC8101 Overview SCC UART RxBD.bd_cstat MRBLR=8 bytes 0 E 1 2 3 4 5 W I C A Byte 1 8000 xxxx RxBD 1 0001 2020 RxBD 2 xxxx Idle time-out occurred 0055 4750 8000 RxBD 3 xxxx FF07 F000 RxBD n 8 CM ID AM 9 10 11 12 13 14 BR FR PR 15 OV CD 2. Clears RxBD.bd_cstat.E after buffer is full (8 bytes received). Byte 8 3. Writes 0x08 to RxBD.bd_length. Byte 1 4. Proceeds to next RxBD since RxBD.bd_cstat.W=0. Byte 2 RxBD 2 1.
MSC8101 Application Examples SCC UART TxBD.bd_cstat 0 R 1 2 3 W I 4 5 CR A 6 7 CM P 8 9 10 11 12 13 14 NS 15 CT CPM Action: TxBD Table TxBD 1 TxBD 1 TxBD.bd_cstat 8000 TxBD.bd_length 0027 1. Transmits 0x27 characters from the buffer at 0x12020. TxBD.bd_addr 0001 2020 2. Clears TxBD.bd_cstat.R after the buffer is sent. 9000 TxBD 2 TxBD 2 0104 1. Transmits 0x104 characters from the buffer at 0x554750. 0055 4750 8200 3. Proceeds to the next TxBD since TxBD.bd_cstat.W=0.
MSC8101 Overview 1.4.1 Media (Voice/Fax/Data) Over Packet Gateway (ATM/FR/IP) Figure 1-7 shows the media (voice/fax/data) over packet gateway (ATM/FR/IP) configuration. MSC8101 Quad System Bus TDM T1/E1 SDRAM/DRAM/SRAM (optional) Channelized Data Framer 155 Mbps ATM PHY UTOPIA Multi PHY or MII Transceiver 10/100BaseT or Framer E3 clear channel (takes one TDM) HDI16 Interface / Control from External Host (MPC860, MPC8260, and so on) Comm PHY SMC/I2C/SPI/SCC Figure 1-7.
MSC8101 Application Examples supports many types of memories, including EDO DRAM and page-mode as well as pipeline SDRAM for efficient burst transfers. 1.4.2 3G Infrastructure Cellular BTS Figure 1-8 shows a 3G infrastructure cellular BTS configuration.
MSC8101 Overview SDRAM/DRAM/SRAM MPC8260 Quad TDM0 T1 Framer PowerPC System Bus Channelized Data (up to 256 channels) TDM7 SDRAM/DRAM/SRAM 155 Mbps ATM PHY UTOPIA Multi PHY PowerPC Local Bus or MII Transceiver ATM Connection Tables (optional) 10/100BaseT or Framer E3 clear channel (takes one TDM) MSC8101 Slaves Slow Comm DSP Bank SMC/I2C/SPI/SCC Optional Distributed Comms PHY Figure 1-9. Centralized DSP Architecture 1.4.
MSC8101 Application Examples Serial Backplane(s) (TDM, Ethernet, ATM) DSP Bank MSC8101 or MPC8260 PowerPC System Bus or Local Bus on MPC8260 16 PPC PowerPC bus HI16 CPM CPM MSC8101 32 Optional SRAM/ SDRAM SDRAM Flash Figure 1-10. Distributed DSP Architecture Connected Through the HDI16 Port In the configuration depicted in Figure 1-11, the PowerPC bus port can be used in both master and slave mode, eliminating the need for a separate HDI16 connection.
MSC8101 Overview 1.5 Software Development Figure 1-12 shows the typical software development flow for the MSC8101.
Software Development window-based and provides multiple views of the code. You can use it to debug C source code, assembly code, or mixed code. It provides effective debug capabilities even within tight DSP loops that have undergone significant optimization by the compiler. The MSC8101 hardware provides non-intrusive real-time tracing for use by the profiler. Another key element of the tool chain, the profiler provides detailed information on deficiencies and hot spots in the code.
MSC8101 Overview 1-28 MSC8101 User’s Guide
Chapter 2 Reset Configuration and Boot This chapter describes the MSC8101 reset and boot process illustrated with examples of different system configurations. It also describes the device clocking system, as it pertains to the reset and boot process. The MSC8101 communicates with other devices in a system either through the PowerPC system bus or the host port (HDI16). The chosen f communication mode defines the reset configuration and the boot method. 2.
Reset Configuration and Boot 2.1.1 Bootloader Program The MSC8101 bootloader program resides in the on-device ROM, starting at location 0xF80000, and executes after reset. This bootloader program loads and executes the source code that initializes the MSC8101 after the device completes a reset sequence. It also programs the MSC8101 registers for the required mode of operation. The bootloader program can receive the source program from either a host processor or an external standard memory device.
Reset Configuration and Boot Basics multiplication factor is determined by the values of the SPLL pre-division factor and the SPLL multiplication factor. The SPLL provides the input clock to the frequency divider for the PowerPC 60x buses. The bus multiplication factor is therefore determined by the combination of the SPLL pre-division factor, the SPLL multiplication factor, and the bus post-division factor. The bus clock is the input reference clock to the CPLL predivider.
Reset Configuration and Boot Six bits map the MSC8101 clocks to one of 64 configuration mode options. Each option determines the CLKIN, PowerPC system bus, SC140 core, and CPM frequency ratios. The six bits comprise three dedicated pins (MOSCK[1-3]) and three bits from the reset configuration word (MODCK_H). For information on clock configuration modes and examples, see the clocks chapter in the MSC8101 Reference Manual. 2.
Configuring a Single MSC8101 Table 2-1. Pin Connectivity for a Reset Configuration From Boot EPROM Pin/Function Connection PORESET External reset HRESET Pulled up DBREQ/EE0 To GND for normal operation of the SC140 core HPE/EE1 To GND to disable the host port BTM[0–1]/EE[4–5] To GND to enable boot from external memory MODCK[1–3] To GND to enable the desired clock frequency RSTCONF To GND Boot EPROM To the address (A[0–31]) and data (D[0–63]) buses 2.2.
Reset Configuration and Boot 2.2.3 Default Configuration With No EPROM The default MSC8101 reset configuration is the simplest configuration scenario (see Figure 2-3 and Table 2-3). The MSC8101 does not access the boot EPROM; it is assumed that the default configuration is used when exiting hard reset. PORESET Vcc Configuration Slave MSC8101 HRESET A[0–31] Vcc D[0–31] PORESET RSTCONF Figure 2-3. Configuring a Single Chip With the Default Configuration Table 2-3.
Configuring a Multi-MSC8101 System, PowerPC Bus Connected 2.3 Configuring a Multi-MSC8101 System, PowerPC Bus Connected This section describes a system of up to eight MSC8101s that connect to a PowerPC bus. The reset configuration and boot process occur via the PowerPC bus. In such a system, an EPROM or other standard memory device usually serves the reset and the boot process. This memory device also connects to the PowerPC bus.
Reset Configuration and Boot PORESET Configuration Master MSC8101 HRESET Boot EPROM A[..] A[0–31] D[0–31] HPE D[0–7] RSTCONF Data Bus PORESET HRESET Address Bus EPROM Control Signals VCC Configuration Slave MSC81011 HPE D[0–31] PORESET HPE HRESET RSTCONF A0 Configuration Slave MSC8101 2 D[0–31] PORESET HPE RSTCONF A1 Configuration Slave MSC8101 7 HRESET PORESET D[0–31] HPE RSTCONF A6 Figure 2-4.
Configuring a Multi-MSC8101 System, PowerPC Bus Connected 2.3.1 Reset Configuration Sequence The reset configuration sequence supports a system with up to eight MSC8101 devices, each configured differently. It needs no additional glue logic for reset configuration. In a typical multi-MSC8101 system, one MSC8101 acts as the configuration master while all other MSC8101s act as configuration slaves.
Reset Configuration and Boot Table 2-6.
Configuring a Multi-MSC8101 System, PowerPC Bus Connected Table 2-7.
Reset Configuration and Boot 2.4 Configuring a Multi-MSC8101 System Connected Via the Host Port This section presents an example of a system with three MSC8101s controlled by one MSC8101 that serves as a host. The host exits reset and boots, and then it writes the reset configuration word to each of the other two MSC8101 devices. After the last MSC8101 hard reset configuration word is written, the MSC8101s exit reset and the boot process starts.
Configuring a Multi-MSC8101 System Connected Via the Host Port Table 2-9. Multi-MSC8101 System Connected Via Host Port (Continued) Pin/Function RSTCONF Connection Connects to VCC NOTE: Ensure that the ISPS bit 7 of the hard reset configuration word is set (1) when the Host Port (HDI16) is in use. This changes the PowerPC data bus from 64 to 32 bits wide. Failure to set this bit results in data bus conflicts and errors.
Reset Configuration and Boot 2.4.1 Host Reset Configuration Sequence This section describes how the reset configuration word is applied to a host-controlled MSC8101. Host reset configuration allows the host to program the reset configuration word via the host port after PORESET is deasserted. If HPE is sampled high at the rising edge of PORESET, the host port is enabled. In this mode the RSTCONF pin must be pulled up deasserted.
Configuring a Multi-MSC8101 System Connected Via the Host Port 2.4.2 Boot Through Host Port The MSC8101 host interface supports bootloading from hosts with 8-bit or 16-bit ports. The system in the example discussed here uses a 16-bit port. The MSC8101 host treats all accesses as address accesses. Single-data strobe or dual-data strobe access and data strobe polarity are configured via external pins. The MSC8101 host interacts with the host port of the MSC8101 slave in polling mode.
Reset Configuration and Boot Table 2-11.
Related Reading checksum. The checksum is calculated by XORing the current word bit by bit with the result of XORing previous words. The value of bit i of the current result is equal to XORing bit i of the current word with bit i of the previous result. After the entire block is loaded, the calculated checksum is compared to the loaded checksum to verify that the code loading completed correctly. Note that the checksum is calculated on all the block words, starting from the address.
Reset Configuration and Boot 2-18 MSC8101 User’s Guide
Chapter 3 Optimizing Memory on the SC140 Core This chapter describes the memory mechanism of the SC140 core and explains how to allocate the memory efficiently for an application running on the MSC8101. The recommended SC140 application development methodology involves significant use of a C compiler, which reduces development time and results in high-performance code.
Optimizing Memory on the SC140 Core ■ The SC140 core does not support accesses to a non-existent memory location. If required, the memory subsystem detects these occurrences and generates non-maskable interrupts (NMIs) to the SC140 core. 3.2 Partitioning Memory The SC140 core is flexible in its support for various memory structures, including different division into submemories.
Memory Configuration . . . . . . . . . . . . . . . . Row 127 . . . . . . MODULE 9 4 KB Module . . MODULE 8 4 KB Module MODULE 15 4 KB Module . Row 1 . . . . . . . . . Row 0 32K . . . . . . . . . . . . . . . . 32543 32512 . 32575 32544 MODULE 0 MODULE 1 4 KB Module 4 KB Module . . 32767 32736 GROUP 0 . . . . . . . . Row 127 . Optimizing Memory on the SC140 Core Figure 3-1.
Optimizing Memory on the SC140 Core 3.4 Avoiding Memory Contentions Contentions occur when there are multiple requests for access to a memory group in the same cycle. A contention event is followed by a stall cycle per conflict in which the contention is resolved.
Related Reading use the addresses 0..0x7FFF (group0) for data storage and addresses 0x8000..0xFFF for program memory. A memory contention is also caused if the DMA and data bus attempt to access the memory within the same group. For information on how to avoid this type of contention, see Section 6.5, Avoiding DMA and SC140 Core Contentions, on page 6-25.
Optimizing Memory on the SC140 Core 3-6 MSC8101 User’s Guide
Chapter 4 Connecting External Memories and Memory-Mapped Devices This chapter illustrates several memory interconnection options for the MSC8101 bus and memory controller. It outlines the hardware connections and memory register settings for the MSC8101 when the PowerPC system bus connects to EPROM, Flash memory, Synchronous DRAM (SDRAM), or an MSC8101 HDI16 slave. 4.1 Memory Controller Basics The MSC8101 has three integrated memory controllers tailored to suit a variety of bus control profiles.
Connecting External Memories and Memory-Mapped Devices granularity. Developers commonly use this flexibility for user-defined interfaces to ASICs or DSPs. Any or all of the eight external chip selects (CS[0–7) can use the same UPM timing. To illustrate the UPM’s capabilities, this chapter discusses a UPM-defined interface that gives a programmable port size and strobe generation matching that of the MSC8101 HDI16 host port.
External Bus Basics Bank 0 MSEL Bank 1 MSEL Bank 2 MxMR[BS] User-Programmable Machine MSEL 60x SDRAM Machine Bank 7 PowerPC System Bus Internal DSP SRAM PowerPC System Bus MSEL Banks 8 and 9 are reserved for future expansion. This bank is used for internal DSP SRAM. Bank 10 MSEL This bank is used for internal DSP peripherals. Bank 11 MSEL 60x General-Purpose Chip-Select Machine Internal Local General-Purpose Chip-Select Machine PowerPC System Bus Internal DSP Peripheral Figure 4-1.
Connecting External Memories and Memory-Mapped Devices 4.3 Connecting the Bus to the Flash Memory Interface In most embedded systems, Flash memory is the standard way to store the non-volatile bootstrap code for the system at power-up. In a DSP environment, typically at least one device connects to flash to configure the system and then bootload real-time firmware code into other devices. The MSC8101 supports such a Flash memory boot operation, as follows: 1. Use Chip-Select 0 (CS0) programmed as a GPCM.
Connecting the Bus to the Flash Memory Interface 4.3.2 Single-Bus Mode GPCM-Based Timings The timing characteristics of the MSC8101 chip select must meet the worst-case timing needs of the selected Flash memory device to assure operation over full temperature and voltage range. Valid data is driven from the Flash memory on a read access based on the combined address and CE and OE timings. During a write, such data is latched into the memory on the rising WE (or CE) edge.
Connecting External Memories and Memory-Mapped Devices CLKin 0 1 2 3 4 5 6 7 8 9 10 0 ~CLK A[0-31] 29lv160:tCS CSx 29lv160:tDS 29lv160:tWP 8101:sp34 29lv160:tWPH 29lv160:tDH WE MSC8101:sp33 D[0-16] PSDVAL Figure 4-4. Flash Memory Write, Single Master For the AMD AM29LV160D-70ns device, the 70 ns access timing implies that around seven to eight 10 ns clock accesses should be possible.
Connecting the Bus to the SDRAM Memory Interface more time at the beginning and end of cycles, so a buffered solution can use exactly the same settings. See the Option Register settings of Table 4-1. Table 4-1. GPCM ORx Settings Register Setting Description OR[BCTLD] = 1 Buffering disabled OR[CSNT] = 1 Early WE negation relative to address negation (and chip select with ACS = 00) OR[ACS] = 00 CS asserted with new address OR[RSV] = 0 Reserved OR[SCY] = 100 4 x 2 = 8 wait states.
Connecting External Memories and Memory-Mapped Devices 4.4.1 Single-Bus Mode SDRAM Hardware Interconnect When the MSC8101 operates in Single-Master MSC8101 Bus mode, the MSC8101 is the only master on the bus and typically connects directly to memory and/or slave peripherals. The MSC8101 SDRAM controller provides the address, data, and control signals for a direct, glueless interconnect to the SDRAM.
Connecting the Bus to the SDRAM Memory Interface two least significant addresses from the MSC8101 are not connected to the SDRAM because of the 32-bit port size. Two registers configure the main SDRAM. The 60x-Bus SDRAM Mode Register (PSDMR) defines the timing and control related parameters, and the Option Register (OR) defines size parameters for the SDRAM.
Connecting External Memories and Memory-Mapped Devices Table 4-2 summarizes the control settings of the MSC8101 SDRAM controller. Table 4-2. SDRAM Control Settings Register Setting Description PSDMR[PBI] = 0b1 Page-based interleaving is used. PSDMR[SDAM] = 0b010 Addresses A[5–21] are multiplexed on the physical address pins A[15–31].
Connecting the Bus to the SDRAM Memory Interface MSC8101:sp12 MSC8101:sp10 ACT READ PRE ACT CLKIN A[0–31] Row Column Row CS DQM[0–7] SDA10 Row Row SDRAS SDCAS SDWE TA SDRAM:Trac D[0 - 31] Figure 4-7. SDRAM Burst Read Page Miss, Single Master SDRAM:Tras SDRAM:Tsh SDRAM:Tss SDRAM:Tsh ACT WRITE PRE ACT CLKin A[0–31] Row Col Row CS DQM[0–7] SDA10 Row Row SDRAS SDCAS SDWE TA MSC8101:sp31 D[0–31] Figure 4-8.
Connecting External Memories and Memory-Mapped Devices For write accesses, the SDRAM controller Activate to R/W = 2 and Write Recovery = 3 clocks. The write recovery period defines the earliest time a precharge can occur after the last data output in a write cycle. For a single-cycle access, this write recovery period must be three cycles to meet the overall SDRAM cycle time needs, assuming an Activate to R/W of 2. Table 4-3 lists the SDRAM timing control values. Table 4-3.
Connecting the Bus to the SDRAM Memory Interface 4.4.5 PowerPC 60x Bus Mode SDRAM Hardware Interconnection In PowerPC Multi-Master Bus mode, there are separate address and data tenure phases in which the address is not driven for the entire bus transaction, so internal address multiplexing is not used. Therefore, external logic must latch the address and multiplex the column and row addresses to the SDRAM at the appropriate time.
Connecting External Memories and Memory-Mapped Devices 4.5 Connecting the Bus to the HDI16 Memory Interface The HDI16 host port is a programmable 8-bit or 16-bit wide parallel port that gives an external host device an access window for data transactions. A parallel interface between the PowerPC system bus of an MSC8101 host and a target HDI16 slave port is often used as a control and data path. One use of the HDI16 interface is to download bootstrap code at start-up.
Connecting the Bus to the HDI16 Memory Interface Note: The standard MSC8101 GPCM can gluelessly meet the timings required by the HDI16 where ACS = 00 and CSNT = 1. However, this ACS setting requires that the address and chip select be driven active on the first rising clock edge of the bus cycle. This requirement may cause an issue in some systems that use data buffering, in that slower devices may not have stopped driving data from the one access before the next.
Connecting External Memories and Memory-Mapped Devices IRQy HREQ IRQx CS4 HCS1 CS5 HCS2 GPL2 HRD BS0 HWR HDI16 UPM CS3 MSC8101 DSP1 HA[0–3] HD[0–15] D[0–15] HREQ HCS1 HCS2 A[27–30] HWR HA[0–3] HDDS = VCC for Dual Data Strobe mode HDSP = GND for active low data strobes HCSP = GND for active low chip selects H8BIT = GND for 16-bit mode MSC8101 DSP2 HRD HDI16 PowerPC System Bus MSC8101 HD[0–15] Single-Master MSC8101 Bus Figure 4-11.
Connecting the Bus to the HDI16 Memory Interface IRQx CS3 CS4 HREQ CS5 GPL2 HCS2 HRD MC74LCX244 HWR HA[0-3] HD[0-15] BS0 OE BCTL1 BCTL0 MSC8101 HDI16 HCS1 MSC8101 DSP1 HDI16 UPM IRQy MSC8101 DSP2 ALE DIR OE 60x bus D[0–15] MC74LCX245 HREQ HCS1 HCS2 HRD A[27–30] LE HWR MC74LCX373 HA[0–3] HDDS = VCC for Dual Data Strobe mode HDSP = GND for active low data strobes HCSP = GND for active low chip selects H8BIT = GND for 16-bit mode HD[0–15] Multi-master 60x Bus Figure 4-12.
Connecting External Memories and Memory-Mapped Devices effect. The DLT3 bit must be set in the corresponding UPM word to indicate the data latch point on the falling clock, and MxMR[GPL4DIS] must be set to enable this mode. Furthermore, the read and write strobe deassertion times are readily met with the illustrated UPM configuration, and this is difficult to achieve with a competitive memory access profile in the alternative GPCM-controlled case.
Related Reading 4.
Connecting External Memories and Memory-Mapped Devices 4-20 MSC8101 User’s Guide
Chapter 5 Balancing Between the PowerPC System and Local Buses The MSC8101 combines the SC140 core with the PowerPC bus and the PowerQUICC II Communications Processor Module (CPM). The PowerPC system bus (a 60x-compatible bus) makes it possible to place an MSC8101 device directly on an existing system PowerPC bus. The MSC8101 has two 64-bit PowerPC buses: the PowerPC system bus and the PowerPC local bus. The PowerPC system bus accesses external memory and any external PowerPC bus resources.
Balancing Between the PowerPC System and Local Buses MII TDMs • • • Other Peripherals Serial Interface and TSA UTOPIA Interface ‘MCC’ / UART / HDLC / Transparent / Enet / FastEnet / ATM / SCCs CPM 2 x FCC 2 x MCC 2 x SCC 2 x SMC PowerPC™ System Bus (64-bit) MEMC Interrupt Controller Timers DMA Engine Parallel I/O Baud Rate Generators PIT System Protection Reset Control Clock Control Dual Ported RAM Internal BIU 2 x SDMA Bridge PowerPC 64/32-bit System Bus SIU SPI I2 C ® RISC PowerPC Lo
PowerPC System Bus (UPM) memory controllers. Since the PowerPC local bus does not have access external to the MSC8101, any external memory accesses must use the PowerPC system bus. MSC8101 GPCM EPROM Address CE OE WE Data CS0 PGPL2 PBS/PWE[0–7] Address Data DRAM Address RAS CAS[0–7] W Data CS1 UPMA PGPLx Figure 5-2.
Balancing Between the PowerPC System and Local Buses Access from the SC140 core to the QBus goes through a QBus switch. Since the QBus is part of the extended core and is clocked at the same speed as the core, accesses to banks on the QBus are fast. However, there is some latency inherent in accessing the QBus banks. For example, it takes three DSP core clocks to access an EFCOP register from the SC140 core.
Bus Interaction 5.3 Bus Interaction The PowerPC buses reside in the SIU portion of the MSC8101. The PowerPC local bus is synchronous to the PowerPC system bus and runs at the same frequency as the PowerPC system bus. Three SIU components interact with the two buses: the PowerPC bridge, the memory controllers for each bus, and the DMA engine. Figure 5-5 shows a block diagram of the SIU.
Balancing Between the PowerPC System and Local Buses allocated to the PowerPC system bus. User-Programmable Machine C (UPMC) controls Bank 10, which is assigned for the internal DSP RAM. The GPCM controls Bank 11 which is assigned to the DSP peripherals EFCOP and HDI16. The GPCM can also control external memories on the PowerPC system bus. Bank 8 and Bank 9 are reserved for future use.
Bus Interaction External PowerPC System bus BRx[MSEL] = 100 Bank 0 BRx[MSEL] = 101 Bank 1 Bank 2 UPMA MxMR[BSEL]=0 PowerPC System Bus UPMB MxMR[BSEL]=0 PowerPC System Bus SDRAM PowerPC System Bus External 60x GPCM PowerPC System Bus UPMC MxMR[BSEL]=1 Internal DSP SRAM Internal Local GPCM Internal DSP Peripheral BRx[MSEL] = 010 BRxMSEL] = 000 Bank 7 Internal PowerPC local bus BRx[MSEL] = 110 Bank 10 BRx[MSEL] = 001 Bank 11 Figure 5-7.
Balancing Between the PowerPC System and Local Buses 5.3.1 DMA Controller The multi-channel DMA controller connects to both the PowerPC system bus and the PowerPC local bus. Data from the extended core transfers from the PowerPC local bus to the PowerPC system bus and vice versa. 5.3.1.1 Selecting a Bus The DMA Channel Configuration Register DCHCRx[PPC] bit selects the PowerPC bus associated with the channel.
Bus Interaction 5.3.1.4 Bus Errors A non-maskable interrupt is generated and the DMA TEA Status Register (DTEAR) is updated whenever a PowerPC system bus or a PowerPC local bus error occurs on a DMA access. The DTEAR[DBER_P] bit is set when a PowerPC system bus error occurs. The DMA transfer error address is read from the PowerPC DMA Transfer Error Address (PDMTEA) Register. The channel that caused the error is read from the PowerPC DMA Transfer Error Requestor Number Register, PDMTER[RQNUM].
Balancing Between the PowerPC System and Local Buses External RAM 1 Dual-Port RAM CP System External ROM SDMA 2 Local 2 MCCs 3 FCCs 4 SCCs 2 SMCs 1 PowerPC system bus = Path 1 2 PowerPC local bus = Path 2 SPI I2C Internal SRAM Figure 5-8. SDMA Data Paths On a path 1 access, the SDMA channel must acquire the PowerPC system bus. On a path 2 access, the PowerPC local bus is acquired and the access is not seen on the external system bus.
Related Reading Registers, PDTEM and LDTEM. If an SDMA bus error occurs on a CP-related transaction, all CPM activity stops and the entire CPM must be reset in the CP Command Register (CPCR). 5.3.2.2 SDMA Bus Arbitration and Bus Transfers On the MSC8101, the SC140 core and SDMA can become external bus masters. Therefore, any SDMA channel can arbitrate for the bus against the other internal devices and any external devices present.
Balancing Between the PowerPC System and Local Buses 5-12 MSC8101 User’s Guide
Chapter 6 DMA Channels The on-device direct memory access (DMA) controller channels transport data between the various modules of the MSC8101 so that the data is available for processing when needed. The DMA controller can transfer data to and from memory or enable communication between peripherals directly without passing through memory.
DMA Channels PowerPC System 64-bit MEMC PowerPC bus 64/32-bit DMA Engine SIU MEMC PowerPC Local 64-bit Host I/F 16-bit HDI16 EFCOP SRAM 512 KB Figure 6-1. DMA Engine Interfaces 6.1.1 Operating Modes The DMA controller operates in two modes: Normal (dual-access) mode and Flyby (single-access) mode. 6.1.1.1 Normal Mode (Dual Access) In Normal mode, data is read from the source and written to the destination through the DMA FIFO.
DMA Programming Basics PowerPC System 64-bit PowerPC bus 64/32-bit MEMC DMA Transfer Steps, Normal Mode DMA Controller 1) Read from source, write to DMA FIFO SIU 2) Read from DMA FIFO, write to Destination MEMC PowerPC Local 64-bit Host I/F 16-bit HDI16 EFCOP SRAM 512 KB Figure 6-2. Normal Mode Example 6.1.1.2 Flyby Mode (Single Access) Flyby mode does not require two DMA channels to complete a data transfer between a peripheral and a memory module.
DMA Channels 6.1.2.1 Memory to DMA FIFO A memory transfer to the DMA FIFO can occur from either external or internal memory. Figure 6-3 shows both possibilities. Note that in memory/DMA FIFO transactions, both directions, the channel is programmed to internal request mode (DCHCRx[25]:INT=1). PowerPC System PowerPC System MEMC MEMC DMA DMA FIFO FIFO SIU External Memory SIU MEMC MEMC PowerPC Local PowerPC Local SRAM 512 KB Internal Memory Transfer External Memory Transfer Figure 6-3.
DMA Programming Basics 6.1.2.3 Peripheral to DMA FIFO The DMA controller transfers data from the internal peripherals HDI16 and EFCOP, which reside on the PowerPC local bus, to the DMA FIFO. It also transfers data from peripherals on the external PowerPC system bus to the DMA FIFO. Figure 6-5 shows both of these options. The relevant DMA channel can be programmed either to external or internal request mode, depending on the peripheral type.
DMA Channels PowerPC System PowerPC System MEMC DMA FIFO DMA SIU SIU FIFO MEMC PowerPC Local External Peripheral MEMC MEMC PowerPC Local HDI16 EFCOP Internal Peripheral Transfer External Peripheral Transfer Figure 6-6. DMA FIFO to Peripheral Transfers 6.1.2.5 Memory to Peripheral, Flyby Mode Flyby transactions can be executed from memory connected to the PowerPC system bus to a peripheral connected to the same bus and to the DMA request/acknowledge lines.
Initializing the DMA PowerPC System External Peripheral MEMC PowerPC System DMA FIFO SIU MEMC DMA FIFO MEMC PowerPC Local SIU External Memory MEMC HDI16 PowerPC Local EFCOP SRAM 512 KB Internal Memory to Internal Peripheral External Memory to External Peripheral Figure 6-8. Peripheral to Memory, Flyby Mode Data Transfer 6.2 Initializing the DMA The DMA controller uses registers and DMA Channel Parameters RAM (DCPRAM) to configure each DMA channel.
DMA Channels 6.2.1 DMA Channel Configuration Registers (DCHRx) Each DMA channel has a DCHCR that defines whether the channel is active (ACTV), the active bus (PPC), settings of the DMA request/acknowledge signals, Flyby mode (FLY), active requestor (INT, RQNUM), and channel priority (PRIO). Since bit 0 of this register activates the DMA channel, it should be set to 1 only after all registers are programmed.
Initializing the DMA will not be serviced further. On the other hand, if the peripheral requires the DMA channel to terminate before the DMA transfer completes, the peripheral generates the DONE signal to alert the DMA that the channel must be terminated. Instead of using the DONE signal, an external peripheral can use the DRACK signal. In this case, it receives acknowledgment when the DMA samples its DMA request, and the peripheral either asserts a new request or resumes other processes. 6.2.
DMA Channels Table 6-3.
Initializing the DMA Table 6-4. Buffer Descriptor Parameters (Continued) Parameter Description BD_SIZE Size A transfer byte size down counter. BD_SIZE is always the number of bytes left to transfer even though the transfer size parameter may vary between eight bits to one burst. BD_BSIZE Base Size Required only for programming continuous buffers.
DMA Channels Another grouping of bits that relate to each other are the BP, TC, and GBL bits. These bits all regulate bus action for the DMA transfer. BP defines the priority for a given transfer on the bus. This priority value goes into effect when the DMA arbitrates for mastership of the bus. DMA bus priority 0 corresponds to BP = 00. This is the highest bus priority level. BP=10 is DMA bus priority 2, the lowest DMA bus priority level.
Initializing the DMA 6.2.8 Buffering and Bursting The MSC8101 DMA module supports five types of buffering: simple, cyclic, chained, incremental, and dual cyclic. For details regarding these buffer types, consult the DMA chapter in the MSC8101 Reference Manual. For programming examples of cyclic and chained buffers, refer to Example 6-2, External Memory to External Memory, Burst Mode, Cyclic Buffer, on page 6-18 and Example 6-4, External Flash Memory to External SDRAM Memory, Dual Access Mode, on page 6-22.
DMA Channels BDx 0x1000 0x1000 0x11F8 Interrupt BDx Interrupt 0x11F8 Cyclic Buffer Simple Buffer BDx 0x1000 0x1000 BDx 0x2000 0x1018 BDx 0x10F8 0x1100 Interrupt 0x11F8 0x1200 Interrupt 0x12F8 Interrupt 0x21F8 Interrupt Chained Buffer 0x1000 BDx 0x2000 0x11F8 BDx 0x21F8 Interrupt Interrupt Dual Cyclic Buffer Incremental Buffer Figure 6-9. DMA Buffer Types 6.
DMA Programming Examples DREQ[3–4] and DACK[3–4] are multiplexed with IRQ lines on the MSC8101 pins, as shown in the external signals chapter of the MSC8101 Reference Manual. The remaining DMA signals are multiplexed on the CPM ports C and D. Since there are four groupings of DMA signals, up to four external devices can request DMA service via DMA request lines. However, only two of the devices can use the DONE/DRACK protocol.
DMA Channels 1. Channel 0 reads data from internal memory to the DMA FIFO. The DMA control registers for channel 0 are programmed as follows: a. The address location of the data, IN_ADDR, is written to the DMA buffer address pointer field (BD_ADDR0). Note that the buffer descriptor is associated to the channel by the DCHCR[10–15]:BDPTR bits. 2. b. The total number of bytes to transfer, SIZE, is written to the DMA buffer size field (BD_SIZE0).
DMA Programming Examples Example 6-1. Internal Memory to External Memory, Simple Buffer ;DMA0 init to input DATA to DMA Buffer move.l #IN_ADDR,d0 ;Init source address move.l d0,M_BDADDR0 move.l #SIZE,d0 ;Init transfer size move.l d0,M_BDSIZE0 move.l #ATTR0,d0 ;Init channel 0 attrib move.l d0,M_BDATTR0 ;DMA1 init to output DATA from DMA Buffer move.l move.l move.l move.l move.l #OUT_ADDR,d0 d0,M_BDADDR1 #SIZE,d0 d0,M_BDSIZE1 #ATTR1,d0 DMA_START move.l d0,M_BDATTR1 moveu.l #dchcr0,d0 move.
DMA Channels 2. c. The buffer is a continuous cyclic buffer. The buffer size to be reloaded, BSIZE0, is written to the DMA buffer base size field (BD_BSIZE0) d. To configure channel 0 for burst cyclic read transactions, the value 0xe0400210 is written to the DMA attribute field (BD_ATTR0). e. To enable channel 0 as a dual transaction initiated by the DMA, the value 0xc0000040 is written to the DCHCR0. Channel 1 writes data from the DMA FIFO to external SDRAM.
DMA Programming Examples move.l move.l move.l move.l #SIZE1,d0 d0,M_BDSIZE1 #ATTR1,d0 d0,M_BDATTR1 DMA_START moveu.l #dchcr0,d0 move.l d0,M_DCHCR0 moveu.l #dchcr1,d0 move.l d0,M_DCHCR1 CONT move.l M_DSTR,d5 bmtsts #0xc000,d5.h jf CONT ;Init transfer size ;Init channel 1 attrib ;Init channel 0 config ;Init channel 1 config 6.4.
DMA Channels 3. c. To configure channel 0 to perform 16-bit read transactions with no increment of the address and a flush of the FIFO, the value 0x08000130 is written to the DMA attribute field (BD_ATTR0). d. To enable channel 0 as a dual transaction initiated by an HDI16 read request, the value 0x81800005 is written to DCHCR0. Channel 1 writes data from the DMA FIFO to external SDRAM. The DMA control registers for channel 1 are programmed as follows: a.
DMA Programming Examples ;DMA1 init to output DATA from DMA Buffer move.l move.l move.l move.l move.l move.l #BUFF_START,d0 d0,M_BDADDR1 #PATT_SIZE,d0 d0,M_BDSIZE1 #ATTR1,d0 d0,M_BDATTR1 DMA_START moveu.l #dchcr0,d0 move.l d0,M_DCHCR0 moveu.l #dchcr1,d0 move.l d0,M_DCHCR1 CONT move.l M_DSTR,d5 bmtsts #0xc000,d5.h jf CONT ;Init destination address ;Init transfer size ;Init channel 1 attrib ;Init channel 0 config ;Init channel 1 config 6.4.
DMA Channels initialized for any of the transfers because the code is not implementing cyclic buffers. a. The DMA buffer descriptor 2 address is initialized to an SDRAM memory location for a 32-bit transfer size, transferring a total of 100 bytes. Once the buffer descriptor 2 read transfer is complete, it invokes the buffer descriptor 8 transfer. 3. b. The DMA buffer descriptor 3 address is initialized to another SDRAM memory location for a 32-bit transfer size, transferring a total of 100 bytes.
DMA Programming Examples ; initialize interrupts bmclr #$00e0,sr.h move.l #M_ELIRE,r7 nop move.w #$0500,(r7) move.l move.l ei INIT_DMA1 move.l move.l move.l #$10000000,d7 d7,M_DIMR ; allow all interrupt levels ; set IRQ18 interrupt to ; level 5 ; enable DMA channel 3 interrupt to PIC ; enable interrupts #SDRAM_DATA1,d0 d0,BD_ADDR2 #$204801B0,d0 move.l d0,BD_ATTR2 move.l #100,d0 move.l d0,BD_SIZE2 move.l #SDRAM_DATA2,d0 move.l d0,BD_ADDR3 move.l #$200901A0,d0 move.l move.l move.l INIT_DMA2 move.l move.
DMA Channels core using IRQ18. Once this interrupt is triggered, the processor jumps to the appropriate interrupt vector address and begins processing. The interrupt vector code, shown in Example 6-5, uses an equate level, I_IRQ18, to define the offset from the vector base address for the interrupt request. All DMA interrupts generate an IRQ18 interrupt trigger. The interrupt service routine must determine which DMA channel triggered the interrupt and respond accordingly.
Avoiding DMA and SC140 Core Contentions 6.5 Avoiding DMA and SC140 Core Contentions The DMA and the SC140 core can access internal memory and peripheral registers independently of each other. Thus, potential contention between the DMA controller and the SC140 core can occur if both are trying to access the same memory location or peripheral register at the same time. Here are some helpful hints to avoid contention: ■ Internal Memory.
DMA Channels channel is active. The DMA can also change the BDPTR and ACTV fields. To prevent the SC140 core from conflicting with the DMA logic and overwriting the DMA modifications, use byte access to the fields when the channel is active. Modifying fields other than the DCHCR[INT, PRIO, FRZ, PPC, ACTV] bits may result in erroneous results. For a chained buffer, if the DCHCR[BDPTR] bits are written while the PRIO field is modified, the incorrect buffer may be selected. 6.
Chapter 7 Interrupts and Interrupt Priorities This chapter describes a step-by-step procedure for handling MSC8101 interrupts. The main steps in this procedure are the software configuration phases for setting up the information in the interrupt controller registers and the interrupt subroutines to be executed. An example driver implementation illustrates both the hardware and software configurations for connecting to a peripheral (the EFCOP) and interrupting it.
Interrupts and Interrupt Priorities External IRQ[2–3] SDMA + CPM Peripherals INT_OUT SIC_EXT NMI_OUT SIU External NMI SIC SIC Port C Pins External IRQ[1,4–7] DMA HOST QBC EFCOP Q2PPC Bridge EOnCE SC140 Core PIC PIC IRQ[0–23] and PIC NMI[0–7] Figure 7-1. MSC8101 Interrupt Structure 7.2 Programmable Interrupt Controller (PIC) The MSC8101 PIC is a peripheral module that serves all the IRQs and non-maskable interrupts (NMIs) received from MSC8101 peripherals and I/O pins.
Programmable Interrupt Controller (PIC) ■ Support for software acknowledgment of all edge-triggered IRQ and NMI. ■ Visibility to all pending IRQ. ■ Support for nine priority levels: — Interrupt disabled (level 0). — Interrupt enabled (levels 1-7, where 7 is the highest priority). — NMI level (8 inputs only). ■ Support for location-dependent priority for equi-level IRQ and NMI. ■ Ability to work with slow peripherals in edge-triggered/level-triggered modes.
Interrupts and Interrupt Priorities 7.3 Programming MSC8101 Interrupts When the PIC detects an IRQ on one or more of its inputs, it arbitrates each IRQ according to its priority level and location and then generates the following: ■ An IRQ signal to the SC140 core, indicating that an IR input has requested interrupt service from the SC140 core. ■ An RIPL[2–0] signal indicating the priority of the IRQ. ■ An entry in the predefined Vector Address Bus (VAB), determined by the location of the IR.
Programming MSC8101 Interrupts Table 7-1. Edge-Triggered/Level-Triggered Interrupt Priority Registers (Continued) Register Name Description Bank IR Inputs ELIRE PIC Edge/Level-Triggered Interrupt Priority Register E E 16–19 ELIRF PIC Edge/Level-Triggered Interrupt Priority Register F F 20–23 Each register defines the interrupt trigger mode and IPL for four inputs. For each input, three bits define the priority level, and one bit specifies the trigger mode for the interrupt.
Interrupts and Interrupt Priorities When the corresponding IR is configured as edge-triggered, its IP bit is set for every new negative edge detected on the IR. A value of “1” written to the IP bit indicates that the corresponding IR has been acknowledged.
Programming MSC8101 Interrupts Table 7-4 summarizes the routing of MSC8101 interrupts. Unless stated otherwise, all IRQ are level-triggered. Table 7-4.
Interrupts and Interrupt Priorities Table 7-4.
Interrupt Programming Examples ... ;Programming the VBA register to address 0x5000 move.l #$5000,vba ;Initializing the stack pointer to address 0x68000 move.l #$68000,r0 nop tfra r0,sp ... ... ; Masking interrupts of priority 0,1,2. bmclr #$00a0,sr.h ... 7.4.1 PIC Programming In the PIC ELIRA–ELIRF registers, you can configure the priority level and select the trigger mode for each interrupt. On reset, all IRs are masked (set to priority 0) and configured as level-triggered.
Interrupts and Interrupt Priorities service routines to accommodate unlimited code size. The following example illustrates a typical interrupt routine that uses a service routine. This example also demonstrates the use of the ei and di instructions, which enable and disable IRs, respectively. IPRB equ $00f01c38 ... org p:IRQ16 ; interrupt routine for SIC di ; disable any IR jsr SIC_IRQ nop ei ; enable IR rte ... org p:SIC_IRQ ; clear pending interrupt in IRPB move.
Interrupt Programming Examples rte ;; ---------------------------------------------------------------;; interrupt handle subroutine (input buffer empty) ;; ---------------------------------------------------------------org p:IRQ1 irqs 1 jsr IRQ1_SUB rte ;; ---------------------------------------------------------------;; interrupt handle subroutine (output buffer full) ;; ---------------------------------------------------------------org p:IRQ2 irqs 2 jsr IRQ2_SUB rte ;; ------------------------------------
Interrupts and Interrupt Priorities ;; ---------------------------------------------------------------;; interrupt handle subroutine (input buffer not full) ;; ---------------------------------------------------------------org p:IRQ0_SUB write_l (r8)+,(r5) nop deceq d3 jf IBNF move.l EFCTL,d5 nop bmclr #$0800,d5.l nop move.
Interrupt Programming Examples loop1 ; ; ; decrement the DST_COUNT ; ; ; ; ; ; ; ; ; clear FOFIE bit ; ; ; OBF ; rts ; ; ;; ---------------------------------------------------------------; ;; interrupt handle subroutine (output buffer not empty) ; ;; ---------------------------------------------------------------; org p:IRQ3_SUB ; write_l EFDOR,(r6)+ ; read single word from FDOR ; deceq d4 ; jf OBNE ; move.l EFCTL,d5 ; clear FONEIE bit ; bmclr #$2000,d5.l ; move.
Interrupts and Interrupt Priorities ;; irq num from 0-23 nop if irq_num<16 move.l #irq_num,d6 move.l #1,d7 lsll d6,d7 nop move.w d7,IPRA else move.l #irq_num-16,d6 move.l #1,d7 lsll d6,d7 nop move.w d7,IPRB endif nop ENDM Following is an nmis macro to clear the edge-triggered interrupt request: nmis MACRO nmi_num ;; nmi num from 0-7 nop move.w PICSR,d6 nop move.l #nmi_num+8,d6 move.l #1,d7 lsll d6,d7 nop move.w d7,IPRB nop ENDM 7.4.4.1 Examples of SIC Interrupts #include"Sic.
Interrupt Programming Examples void SPI_InitInterrupt() { //create entry in SIC branch table: SIC_BranchTable[SIC_SPI].Interrupt = SPI_Interrupt; //the interrupt routine for the SPI must be called SPI_Interrupt SIC_BranchTable[SIC_SPI].Serial=NULL; //temp //Configure SPI: IMM->spi_spie = 0xFF; //clear any previous SPI interrupt events in SPI-reg.
Interrupts and Interrupt Priorities SIC_RESV05, SIC_FCC1, SIC_MCC1, SIC_SCC1, SIC_RESV12, SIC_PC15, SIC_PC11, SIC_PC07, SIC_PC03, }; void SIC_InitInterrupt(); void PIC_Code(); void SIC_IrqHandler(); SIC_RESV06, SIC_FCC2, SIC_MCC2, SIC_SCC2, SIC_RESV13, SIC_PC14, SIC_PC10, SIC_PC06, SIC_PC02, SIC_RESV07, SIC_FCC3, SIC_RESV10, SIC_SCC3, SIC_RESV14, SIC_PC13, SIC_PC09, SIC_PC05, SIC_PC01, SIC_RESV08, SIC_RESV09, SIC_RESV11, SIC_SCC4, SIC_RESV15, SIC_PC12, SIC_PC08, SIC_PC04, SIC_PC00 7.4.4.
Interrupt Programming Examples memcpy((void*)(VBA + 0x0c00), &PIC_Code,0x50); //clear whole SIC branch table memset(SIC_BranchTable, 0 , sizeof(SIC_BranchTable)); //clear any previous SIC interrupt in Irq Pending Register B: QMM->Iprb = 0x0001; //Configure Edge/Level-Triggered Irq Priority Register E to enable IRQ16: //Irq16 (SIC), level-triggered, Irq priority level=3 QMM->Elire = (QMM->Elire & 0xFFF0) | 0x0003; IMM->ic_sipnr_l IMM->ic_simr_l = 0xFFFFFFFF; //clear any previous interrupts in SIC-reg.
Interrupts and Interrupt Priorities asm("nop"); asm("adda r1,r0"); asm("nop"); asm("moveu.b (r0),r1"); source asm("move.l #_SIC_BranchTable,r0"); asm("nop"); asm("adda r0,r1"); asm("nop"); asm("move.
Chapter 8 Host Interface (HDI16) The HDI16 host port is a Motorola MSC8101 DSP peripheral featuring a 16-bit-wide parallel port for communication with a host processor. This parallel port is a full-duplex and double-buffered slave interface. It transfers data between a host or DMA controller and the DSP, and it transfers commands from the host to the DSP. The 16-bit-wide HDI16 data bus handles 16-bit, 32-bit, 48-bit, and 64-bit data transfers.
Host Interface (HDI16) As Figure 8-1 shows, the HDI16 peripheral has two register banks: ■ Host-side register bank. Accessible only to the host from the external HDI16 bus. ■ DSP-side register bank. Accessible only to the DSP internal resources. For host-to-DSP transfers, the host writes the host-side registers and the DSP reads the DSP-side registers; for DSP-to-host transfers, the DSP writes the DSP-side registers and the host reads the host-side registers.
Operating in Different Data Transfer Modes Table 8-1.
Host Interface (HDI16) The Host DMA Mode Enable bit in the Host Port Control Register, HPCR[14]:DMA, defines the mode of operation as shown in Table 8-3. The hardware can be set up so that both transfer modes, Normal and DMA, can be used on the same bus, though not simultaneously. In Normal mode, the host transfers data one access at a time, with each access requiring an address and data transaction on the host bus.
Operating in Different Data Transfer Modes Table 8-5. Single- and Dual-Strobe Bus Pin Functionality ■ HDI16 Pin Single-Strobe Bus Dual-Strobe Bus HRW/HRD HRW HRD/HRD HDS/HWR HDS/HDS HWR/HWR Polarity of the read/write strobes. Signals can be programmed as active high or active low, as indicated by an ORing of the HPCR[6]:HDSP bit and the HDSP pin. The HDI16 can be programmed to use a single host request line or dual host request lines. Table 8-6.
Host Interface (HDI16) Table 8-8. Host-Defined Normal Mode Data Size ICR[9]:HDM0 ICR[10]:HDM1 Data Size Last Address 0 0 64-bit 0x7 0 1 48-bit 0x6 1 0 32-bit 0x5 1 1 16-bit 0x4 Conversely, if the DSP defines the data size of the Normal mode transfer (HCR[4]:HICR=0), the DSP-side HCR[6–7]: HDM bits select the data size, as indicated in Table 8-9. The HCR[6–7]:HDM bits are reflected on the host-side ICR[9–10]:HDM bits, allowing the host side to determine the DMA data transfer size.
Operating in Different Data Transfer Modes The minimum hardware set-up necessary for using the HDI16 port in Normal mode is a chip select, four address lines to access the eleven HDI16 host-side registers, sixteen data lines (in 16-bit mode), and two data strobe lines. Figure 8-2 shows a simple hardware set-up that supports Normal mode. The host bus performs the following actions: 1. Selects the HDI16 device (HCS1). 2. Indicates the direction of the transfer (HRD or HWR) 3.
Host Interface (HDI16) active low, read (HRD) and write (HWR) strobes by setting HPCR[3]:HDDS and clearing HPCR[6]:HDSP. Active low Chip Select (HCS1) is programmed by clearing HPCR[2]:HCSP. The HPCR[8]:HEN bit is initially cleared, disabling the HDI16 port. To assure proper operation, the HPCR[HAP, HRP, HCSP, HDDS, HDSP, and H8BIT] bits should be set only when HPCR[8]:HEN is cleared. After these bits are set as required, the HDI16 port is enabled by setting the HPCR[8]:HEN bit.
Operating in Different Data Transfer Modes If the host (external DMA controller) defines the DMA (HCR[4]:HICR=1), the host-side ICR[RREQ] bit defines the direction of the DMA transfers (see Table 8-11) and the ICR[9–10]:HM[0–1] bits select the DMA data size (see Table 8-12). The HM[0–1] bits are reflected on the DSP-side HCR[6–7]:HM bits, allowing the DSP side to determine the DMA data transfer size. The RREQ bit is reflected in the HCR[5]:RREQ bit, so the DSP side can determine the DMA direction.
Host Interface (HDI16) There are two ways to set up the hardware connection for DMA transfers, depending on the method of acknowledging that valid data is on the host bus. Data always transfers over the HD[0–15] data lines (HD[0–7] in 8-bit mode). The HREQ output pin is always used to request DMA transfers from the host or DMA controller. However, valid data on the host bus can be acknowledged in two different ways, using the HACK input pin or the host address 0x4, as defined in Table 8-14. Table 8-14.
Operating in Different Data Transfer Modes The assembly language equate listed in Example 8-3 defines the initial register values to set up the HDI16 for the hardware set-up represented in Figure 8-3. Example 8-3. Register Values for Example Shown in Figure 8-3 INIT_HPCR EQU 0xC002 ; [0] = HAP = 1 -> HACK pin active high ; [1] = HRP = 1-> HREQ pin active high ; [2] = HCSP = 0 -> Not used. Write to 0 ; [3] = HDDS = 0-> Not used. Write to 0 ; [4:5] = reserved = 00 ; [6] = HDSP = 0 -> Not used.
Host Interface (HDI16) Example 8-4. Initializing the HDI16 Port move.w #HPCR_ADDR,r1 ; r1 = HPCR address move.l #HCR_ADDR,r2 ; r2 = HCR address move.w #INIT_HPCR,(r1) ; initialize HPCR bmset.w #8,(r1) ; enable HDI16 move.w #INIT_HCR,(r2) ; initialize HCR The following list summarizes the steps the DSP follows to initialize the HDI16 port in DMA mode: 1. Initialize the Host Port Control Register (HPCR), ensuring that the HPCR[8]:HEN bit is clear. 2. Enable the HDI16 by setting HPCR[8]:HEN. 3.
Managing Data Transfers Via Handshaking Protocols A similar situation occurs when the host performs multiple reads from the HDI16 port Receive Word Registers (RX[0–3]). The DSP side uses an appropriate handshaking protocol to determine whether the 64-bit Host Transmit Register (HOTX) FIFO is not full. If HOTX is not full, the DSP writes the data to this register. Data is transferred to the host-side Receive Word Registers (RX[0–3]) only if they are empty (that is, the host has previously read them).
Host Interface (HDI16) ■ If HTFE is clear, the HOTX FIFO is not empty (it is either partially empty or full). ■ If HTFE is set, the HOTX FIFO is empty. To determine whether HOTX is full, the DSP core polls the Host Transmit Not Full bit in the Host Status Register (HSR[12]:HTFNF): ■ If HTFNF is clear, the HOTX FIFO is full, and the core should not write to it. ■ If HTFNF is set, the HOTX FIFO is not full (it is either partially full or empty).
Managing Data Transfers Via Handshaking Protocols 8.3.1.2 Host Polling A polling mechanism similar to that for the DSP is available for host use. When data is transferred to the DSP (host writes), the host polls the Transmit Data Empty bit in the Interface Status Register (ISR[14]:TXDE). If TXDE is set, the Transmit Data Registers (TX[0–3]) are empty, and the host can write to them. Otherwise, it must wait until the data in these registers is transferred to the DSP-side HORX.
Host Interface (HDI16) Table 8-15.
Managing Data Transfers Via Handshaking Protocols Enable 15 0 HCIE HTFIE HTEIE HRFIE HREIE HCR Core Interrupts IRQ5: Receive FIFO Full IRQ6: Receive FIFO Not Empty IRQ7: Transmit FIFO Empty IRQ8: Transfer FIFO Not Full IRQ9: External Host Command NMI0: HDI16 External Host NMIHost N 0 15 HTFNF HTFE HRFF HRFNE HSR Status 0 15 HCVR HCP Status 0 7 NMI 8 15 HC CVR Figure 8-4.
Host Interface (HDI16) Example 8-7. Receive Interrupt Set-up Code ; setup HI16 registers move.l #M_HPCR,r1 ; r1 = HPCR address move.l #M_HCR,r0 ; r0 = HCR address move.w #INIT_HPCR,(r1) ; init HI16 HPCR bmset.w #M_HEN,(r1) ; enable HI16 move.w #INIT_HCR,(r0) ; init HI16 HCR move.w #BUFF,r3 ; r3 = pointer to buffer in memory ; set-up and enable interrupt di move.l #I_ELIRB,r1 bmclr #$00e0,sr.h ; enable all IPLs move.w #INIT_ELIRB,(r1) ; set hi16 rxne IPL bmset.
Managing Data Transfers Via Handshaking Protocols The host enables host requests using the Interface Control Register (ICR) as follows: 1. Configure the HDI16 for single (HREQ) or double (HRRQ and HTRQ) requests using the ICR Host Double Request bit as indicated in Table 8-17. This bit is available only in Normal transfer modes. Table 8-17. Single or Double Request Configuration 2.
Host Interface (HDI16) Table 8-19. HTRQ and HRRQ Pins In Double Request Mode (ICR[13]:HDRQ=1) ICR[14]=TREQ ICR[15]=RREQ HTRQ Pin HRRQ Pin 0 0 No interrupts No interrupts 0 1 No interrupts ISR[15]:RXDF request enabled 1 0 ISR[14]:TXDE Request enabled No interrupts 1 1 ISR[14]:TXDE Request enabled ISR[15]:RXDF request enabled The request signal lines from the DSP normally connect to the host’s interrupt request pins (IRQx), which generate an interrupt in the host.
Managing Data Transfers Via Handshaking Protocols The details of the MSC8101 internal DMA are beyond the scope of this chapter. The overall steps involved in programming a DMA channel for access of the HDI16 in flyby mode are as follows: 1. Initialize a DMA Channel Configuration Register (DCHCRx) for the selected DMA.
Host Interface (HDI16) Example 8-9 shows the code necessary to set up a dual DMA to receive BUFF_SIZE 16-bit data elements from the HDI16 and place them into a buffer in the internal SRAM located at BUFF_START. An interrupt is generated when the DMA is finished. Example 8-9. Receive Interrupt Service Routine INIT_ATTR0 EQU $08000010 INIT_ATTR1 EQU $80000000 INIT_DCHCR0 EQU $80000005 INIT_DCHCR1 EQU $80010045 INIT_DIMR EQU $40000000 INIT_ELIRE EQU $0c00 ; setup source DMA DCPRAM move.
Issuing Host Commands and Non-Maskable Interrupts move.l #M_DCHCR1,r0 moveu.l #INIT_DCHCR1,d0 move.l d0,(r0) ; set DCHCR1 ; setup PIC registers move.l bmclr move.w #M_ELIRE,r3 #$00a0,sr.h #INIT_ELIRE,(r3) ; mask priorities < 2 ; init PIC ELIRE reg The internal MSC8101 DMA controller does not access the host bus, so the host must determine when data is available in the host-side data registers using an appropriate polling mechanism. 8.
Host Interface (HDI16) determine when the PIC accepts this command. The ISR must also clear the interrupt request in the PIC Interrupt Pending Registers (IPRx). The operation is very similar for non-maskable interrupts (NMIs), except that the ISR cannot be masked in the HCR. Typically, the host writes the CVR[HV] bits with the pointer to the pre-programmed function and also sets the HC and NMI bits. This causes the PIC on the MSC8101 extended core to execute the External Host NMI ISR at VBA offset 0xE00.
Chapter 9 Enhanced Filter Coprocessor (EFCOP) The MSC8101 EFCOP module is a general-purpose, fully programmable filter with 32-bit resolution. It has optimized modes of operation to perform real and complex finite impulse response (FIR) filtering, infinite impulse response (IIR) filtering, adaptive FIR filtering, and multichannel FIR filtering. EFCOP filter operations complete concurrently with SC140 core operations, with minimal CPU intervention.
Enhanced Filter Coprocessor (EFCOP) : Table 9-1. EFCOP Control Registers Register Name Description Filter Count Register (FCNT) A 16-bit read/write register that specifies the number of filter taps. The count stored in the FCNT register is used by the EFCOP address generation logic to generate correct addressing to the filter data memory (FDM) and filter coefficient memory (FCM). EFCOP Control Register (FCTL) A 16-bit read/write register used by the SC140 core to program the EFCOP.
Specifying the Operating Modes for the FIR Filter Type 9.2 Specifying the Operating Modes for the FIR Filter Type This section discusses the various operating modes that are available for the FIR filter type. The FIR filter type is selected by clearing the FCTL[14]:FLT bit, and it performs the processing shown in Figure 9-1 using the following equation: N ∑ Bi x ( n – i ) w( n ) = i=0 For each sample to be filtered, the EFCOP completes the following steps: 1. Take an input, x(n), from the FDIR. 2.
Enhanced Filter Coprocessor (EFCOP) 9.2.1 Real Mode Real mode performs FIR type filtering with real data and is selected by clearing both FCTL[10–11]:FOM bits. For each sample (the real input) written to the FDIR, one sample (the real output) is read from the FDOR. In Real mode, the number written to the FCNT register should be one minus the number of filter coefficients. Two other options are available with the real FIR filter type: Adaptive and Multichannel modes.
Specifying the Operating Modes for the FIR Filter Type to be from 1 to 64. For each time period, the EFCOP expects to receive the samples for each channel sequentially. This process repeats for consecutive time periods. Filtering is performed with the same filter or different filters for each channel using the FACR[8]:FSCO bit. If this bit is set, the same set of coefficients is used for all channels.
Enhanced Filter Coprocessor (EFCOP) 9.2.
Specifying the Operating Modes for the FIR Filter Type The Data Initialization mode is selected via the FCTL[8]:FPRC bit: ■ If FCTL[8]:FPRC is set, initialization is disabled and the EFCOP assumes that the SC140 core wrote the initial input values to the FDM before the EFCOP was enabled. Thus, the first value written to FDIR is the first sample to be filtered.
Enhanced Filter Coprocessor (EFCOP) mode, two times the decimation ratio number of samples must be written to the FDIR (one for the real part and one for the imaginary part of the input) before two output samples (one for the real part and one for the imaginary part of the output) can be read from the FDOR.
Specifying the ALU Modes FDM FCM y(n-1) A0 y(n-2) A1 y(n-3) A2 Scale here if FISL = 1 Scale here if FISL = 0 FDOR FDIR w(n) y(n-N) AN Figure 9-2. IIR Filter Block Diagram Multichannel mode for the IIR filter type works exactly the same way as for FIR filter type as explained in Section 9.2.1.2, Multichannel Mode, on page 9-4. Decimation and Adaptive modes are not available with the IIR filter type.
Enhanced Filter Coprocessor (EFCOP) 9.4.2 Input Scaling The Input Scaling mode affects only IIR filtering and the coefficient update session of adaptive FIR filtering. The FACR[9]:FISL and FACR[14–15]:FSCL bits, determine how the outputs are scaled. The result can be scaled up by the following values: ■ One, that is, no scaling (FACR[14–15]:FSCL = 00) ■ Eight (FACR[14–15]:FSCL = 01) ■ Sixteen (FACR[14–15]:FSCL = 10) For IIR type filtering, FACR[9]:FISL determines whether the IIR input is scaled.
Transferring Data In and Out of the EFCOP 9.5 Transferring Data In and Out of the EFCOP When the EFCOP is programmed and enabled, it waits until input data is written to the Filter Data Input Register (FDIR). The FDIR is an 8-element deep FIFO, so up to eight 32-bit wide data samples can be written into FDIR at the same address. When the EFCOP finishes processing the input data from the FDIR, it sends the results to the FDOR.
Enhanced Filter Coprocessor (EFCOP) ■ FSTR[10]:FDOBF is set when the FDOR is full (that is, all eight of the locations are full). Thus, when this bit is set, the SC140 core can read up to eight samples of data from the FDOR. For an example of EFCOP programming with polling, see Section 9.6.1, Complex FIR Filter with Polling, on page 9-14. 9.5.2 Interrupts The EFCOP provides five interrupts.
Transferring Data In and Out of the EFCOP d. Clear the Interrupt Trigger Mode (PEDxx) bits of the ELIRx registers because all peripheral interrupts are level triggered. e. Enable the interrupts by issuing an ei (enable interrupts) instruction. For an example of EFCOP programming with interrupts, see Section 9.6.2, Adaptive Filter With Interrupts, on page 9-16. 9.5.
Enhanced Filter Coprocessor (EFCOP) this mode when the DMA is programmed to transfer single 32-bit long samples from the FDOR (DMA BD_ATTR field TSZ bits equal to 011). Burst or single transfers of more than 32-bits cause an error when FCTL[0]:FDOM is clear. — When FCTL[0]:FDOM is set, the EFCOP issues transfer request from the DMA when the output buffer is full (when FSTR[9]:FOBNE is set). Use this mode when the DMA is programmed to transfer more than one 32-bit long sample from the FDOR.
Programming Examples resolution and that memory is addressed in one byte resolution. Therefore, the FDM and FCM are located at 0x400 multiplied by four plus the base address, which is memory location 0x71000 for the FDM and 0x79000 for the FCM. b. The FCNT constant defines the filter length and is equal to twice the number of complex filter coefficients (that is, if there are five complex filter coefficients, FCNT should be 10). FCNT –1 is written to the filter count register. c.
Enhanced Filter Coprocessor (EFCOP) empty dosetup0 empty loopstart0 move.w M_FSTR,d4 bmtstc #$0040,d4.l jt empty doen0 #NSAMP ;Wait until out not empty move.2l (r3),d2:d3 move.2l d2:d3,(r1)+ move.2l d0:d1,(r2) move.2l (r0)+,d0:d1 loopend0 ;Read output ;Write input endempty move.w M_FSTR,d4 bmtstc #$0040,d4.l jt endempty move.2l (r3),d2:d3 move.
Programming Examples uses Adaptive mode and the data output not empty interrupt (IRQ3) to update the coefficients as shown in Section 9.2.1.1, as follows: 1. Address register pointers are initialized for the filter input and output data (INPUT and OUTPUT). 2. The EFCOP control parameters are written to the appropriate memory mapped control registers as follows: a. FDM and FCM are located at the beginning of the shared memory, so the FDBA and FCBA registers are written with zero. b.
Enhanced Filter Coprocessor (EFCOP) Example 9-3. Adaptive Filter Code move.w #INPUT,r0 move.w move.w move.w move.w move.w move.w move.w move.w move.w #OUTPUT,r1 #0,d0 d0,M_FDBA #0,d0 d0,M_FCBA #FCNT-1,d0 d0,M_FCNT #$2105,d0 d0,M_FCTL ;Init data pointers ;Init FDBA ;Init FCBA ;Init FCNT ;Init FCTL bmclr #$00E0,sr.h move.w #$7000,d0 move.w d0,M_ELIRA ei ;Enable all IPL ;Out not empty IPL 6 ;Enable interrupts doensh0 #FCNT loopstart0 move.l (r0)+,d0 move.l d0,M_FDIR loopend0 ;Init data taps move.
Programming Examples The interrupt service routine code, shown in Example 9-5, completes the processing as follows: 1. The code moves the filter output from FDOR to the output data buffer. 2. The step parameter is loaded into FKIR. Once FKIR is loaded, the EFCOP performs the coefficient update session, as discussed in Section 9.2.1.1, and replaces the filter coefficients with the updated coefficients. 3.
Enhanced Filter Coprocessor (EFCOP) through the UPMC and to access the EFCOP registers through the GPCM, respectively. The memory buffers to which the IN_ADDR, TMP_ADDR, and OUT_ADDR equates point must be within the memory range of bank 10. The FDIR_ADDR and FDOR_ADDR equates must point to the EFCOP input and output register locations in bank 11. The code in Example 9-6 shows the code for the FIR session using dual-access DMA transactions.
Programming Examples c. To configure channel 1 for 32-bit write transactions without incrementing the buffer address (always transfers to the FDIR), the value 0x08000180 is written to the DMA attribute field (BD_ATTR1). d. To enable channel 1 in dual access mode triggered by an EFCOP write request, the value 0x80010305 is written to the DMA Channel Configuration Register (DCHCR1). 4. DMA Channel 2 transfers the data from the FDOR to the DMA FIFO.
Enhanced Filter Coprocessor (EFCOP) Example 9-6. FIR Filter Session move.w move.w move.w move.w move.w move.w move.w move.w #FIR_FDBA,d0 d0,M_FDBA #FIR_FCBA,d0 d0,M_FCBA #FIR_FCNT-1,d0 d0,M_FCNT #$0081,d0 d0,M_FCTL ;DMA0 init to transfer Memory to DMA FIFO move.l #IN_ADDR,d0 move.l d0,M_BDADDR0 move.l #NSAMP,d0 move.l d0,M_BDSIZE0 move.l #$00000190,d0 move.l d0,M_BDATTR0 move.l #$80000045,d0 move.l d0,M_DCHCR0 ;DMA1 init to transfer DMA FIFO to FDIR move.l #FDIR_ADDR,d0 move.l d0,M_BDADDR1 move.
Programming Examples empty and channel 1 transfers eight 32-bit samples from the FDOR whenever the FDOR is full. The IIR session proceeds as follows: 1. The EFCOP is disabled by clearing the FCTL before the IIR session parameters are programmed into the FCTL. 2. The following control parameters are written to the EFCOP control registers: a. The FDM and FCM are located at an offset from the beginning of the shared memory defined by the IIR_FDBA and IIR_FCBA constants. b.
Enhanced Filter Coprocessor (EFCOP) d. The value 0x80014204 is written to the DMA Channel Configuration Register (DCHCR1). This value enables DMA channel 1 in flyby mode triggered by an EFCOP read request. Example 9-7. IIR Filter Session move.w #0,d0 move.w d0,M_FCTL ;Disable EFCOP move.w move.w move.w move.w move.w move.w move.w move.w move.w move.
Related Reading 9.7 Related Reading MSC8101 User’s Guide (This manual) Chapter 1, MSC8101 Overview Section 1.3.7.
Enhanced Filter Coprocessor (EFCOP) 9-26 MSC8101 User’s Guide
Chapter 10 Multi-Channel Controllers (MCCs) This chapter describes a step-by-step procedure for setting up a 32-channel T1/E1 link using one of the MSC8101 multi-channel controllers (MCCs). The main steps in this procedure are three software configuration phases for setting up MCC and CPM parameters. An example driver implementation illustrates both hardware and software configuration for connecting to an industry-standard T1/E1 line transceiver.
Multi-Channel Controllers (MCCs) Communications Processor Module (CPM) PowerPC 64-bit Bus . Serial Interface and TSA 2xFCC 2xMCC 2xSCC 2xSMC MEMC Interrupt Controller Timers Parallel I/O Baud Rate Generators PowerPC 64-bit System Bus SIU Dual-Port RAM SPI I2C SDMA RISC CP Other Peripherals 4 x TDMs MII UTOPIA I/F The main MCC configuration is through MCC-specific parameters in the on-device Dual Port RAM (DPRAM).
MCC Configuration Basics 3. Configure the external interface: a. Set up the parallel I/O pins. b. Enable the TDM. These steps map to the functionality flow of the software driver discussed in this chapter. See Figure 10-2 for a listing of the driver functions.
Multi-Channel Controllers (MCCs) 10.1.2 Driver Memory Map All values in the driver memory map are set up as offsets to the Internal Memory Map Register (IMMR), indicated in Figure 10-3 as the DPRAM Base. These values are changed via the mcc.h header file, with these exceptions: the MCC2 parameter RAM, in which the global parameters are stored, and the channel-specific parameters, which both have fixed locations.
MCC Configuration Basics MCCBASE DPRAM Base MCC1 ChannelSpecific Parameters Buffer Descriptors MCC2 Channel-extra parameters MCC1 XTRABASE MCC2 Buffers MCC1 MCC global parameters MCC2 DPRAM TINTBASE RINTBASE Circular Interrupt Tables External Memory (512 KB) Figure 10-4. Internal and External Memory Usage 10.1.3 Memory Usage Memory resources can become scarce as the number of MCC channels increases.
Multi-Channel Controllers (MCCs) Table 10-2.
Connect the TDM Interface to T1/E1 MSC8101 Memory Controller MCC2 L1TSYNCB L1RSYNCB L1RXDB L1TXDB L1RCLKB L1TCLKB PM6388 Microprocessor Interface EFP[6] IFP[6] ID[6] ED[6] ICLK[6] RLCLK[6] RLD[6] TLCLK[6] TLD[6] Receive PMC Line Interface Unit PM4314 Transformer RJ45 Figure 10-5. T1/E1 Transceiver Interface Example The TDM interface connection is relatively simple, consisting of a transmit and receive clock, synchronization signals, and data signals.
Data Frame 1 L1RSYNCB Multi-Channel Controllers (MCCs) 32 Time Slots slot 4 slot 5 ------- ------- ------- MCC MCC MCC MCC MCC MCC MCC Ch160 Ch161 Ch162 Ch163 Ch164 Ch165 Ch--- MCC Ch--- MCC Ch--- slot 0 slot 1 slot 2 slot 3 ------- slot29 slot30 slot31 MCC MCC MCC MCC Ch--- Ch189 Ch190 Ch191 L1RCLKB L1RSYNCB (RFSYNC) L1TXDB bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 L1RXDB bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 8 Bit Slot Figure 10-6. T1/E1 Data Frame 10.
Connect the TDM Interface to T1/E1 ■ External PHY loopback. The full external Transmit-to-Receive path tests the physical interface between the MSC8101 and the physical (PHY) device. Figure 10-7 summarizes the three system-level loopback options: (1) SI-level internal loopback, (2) TDM-level internal loopback, and (3) external PHY loopback.
Multi-Channel Controllers (MCCs) Line Clock (TLCLK) sourcing L1TCLK and the Ingress Clock (ICLK) connected to L1RCLK (see Figure 10-5). The PM6388 T1/E1 PHY transceiver is initialized in software through the Init_PHY() function. The driver code sets up the PHY to be in internal loopback mode to enable external PHY loopback. 10.3 Configure the Channels Channel configuration proceeds in two steps: ■ Configure the global MCC resources applicable to all the channels supported by the MCC.
Configure the Channels ■ GRFTHR and GRFCNT. Two parameters relating to the reception of frames. GRFTHR is a threshold value after which an interrupt is generated. ■ XTRABASE. Defines the offset in the dual-port RAM (DPRAM) that points to the location holding the extra channel-specific parameters. Each channel’s extra parameters are stored in order contiguously from this offset. (Offset 0x3800 is used in this example.) The following parameters relate to interrupt queue set-up and handling: ■ TINTBASE.
Multi-Channel Controllers (MCCs) ■ MCCM. The Interrupt Mask Register filters interrupt event requests to the core. In this example, setting MCCM = 0x4004 enables the RINT0 and TINT interrupts. ■ MCCE. The Interrupt Event Register reports receive and transmit events. This register is cleared by writing all ones (MCCE = 0xFFFF) at initialization.
Select the TSA Channel Route to a TDM Timeslot 10.3.4 Set Up the Channel Extra Parameters Each MCC channel has an 8-byte allocation for parameters defining the actual address of the Tx and Rx BDs for a specific channel. These extra parameters are located at an offset from the base address of the DPRAM, defined by XTRABASE, in the global parameters. The driver sets up all channel-extra parameters for MCC2 from the [XTRABASE+(channel number × 8)] address.
Multi-Channel Controllers (MCCs) 10.4.1 Define the Serial Interface Entries in SIRAM Internal MSC8101 External MSC8101 TDMA Channels MCC1 SIRAM1 TDMA pins Time-Slot Assigner SIRAM2 MCC2 TDMB pins TDMC pins TDMD pins TDMB channels TDMC channels TDMD channels Figure 10-8. Serial Interface The SIRAM is a block of memory internal to the CPM that routes data from the TDM pins to the MCC. The SIRAM consists of a series of entries, one set for the Tx and one for the Rx flow.
Select the TSA Channel Route to a TDM Timeslot Loop/ Super echo MCSEL CNT BYT LST Channel 160 Rx entry 1 0 10100000 000 1 0 Channel 160 Tx entry 0 0 10100000 000 1 0 Channel 191 Rx entry 1 0 10111111 000 1 1 Channel 191 Tx entry 0 0 10111111 000 1 1 Figure 10-9. Serial Interface Entry Definitions for Driver Example 10.4.2 Set up Clocks, Baud Rate Generators (BRG), and Timers The TDMB clocks (L1RCLKB, L1TCLKB) are always driven from an external source.
Multi-Channel Controllers (MCCs) 3. Timer Reference Register (TRR). Finally, the TRR1 register is set to contain the timeout reference value, resulting in a configuration of 0x00FF. The timer output TOUT1 must be externally connected to L1RSYNC. 10.5 Set Up the External Interface The CPM interface is essentially a set of I/O pins that can be configured for either a peripheral or a general-purpose function.
Chapter 11 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) is a synchronous serial data protocol that is standard across many Motorola processors and other SPI-compatible devices, including EEPROMs and analog-to-digital A/D converters. It is essentially a shift register that transmits and receives data serially to and from other devices with an SPI.
Serial Peripheral Interface (SPI) Table 11-1. SPI Signals (Continued) Signal SPIMISO Description SPI Master In Slave Out When the SPI is configured as a master, SPIMISO is the input signal that receives data from the slave device. When the SPI is configured as a slave, SPIMISO is the output signal that transmits data to the master device. SPICLK SPI Clock When the SPI is configured as a master, SPICLK is the output signal that shifts received data in from SPIMISO and transmitted data out to SPIMOSI.
Setting the Clock 11.2 Setting the Clock In the master mode, the baud rate is determined by the divide by 16 option and the prescale modulus. The SPI baud rate generator (SPI BRG) takes its input from BRGCLK and generates the SPICLK. The SPI BRG provides a divide-by 16 option and a prescale divider option. Figure 11-1 shows the SPI BRG block diagram. BRGCLK Prescale Modulus Divide by 1 or 16 SPICLK SPI BRG Figure 11-1.
Serial Peripheral Interface (SPI) changed only when the SPI is disabled. The remaining parameters are for communications processor (CP) use only, so you do not need to initialize them. Table 11-2. SPI Parameter Table IMM + 0x Value in 0x89FC Name Width 0x00 RBASE 16-bits 0x02 TBASE 16-bits 0x04 RFCR 8-bits 0x05 TFCR 8-bits 0x06 MRBLR 16-bits Maximum receive buffer length Defines the maximum number of bytes the MSC8101 writes to a receive buffer before moving to the next buffer.
Operating the SPI as a Master then the SPI parameter table would begin at IMM + 0x3800. The RxBDs reside in the dual-port RAM, starting at the address in RBASE. The TxBDs also reside in the dual-port RAM, starting at the address in TBASE. For example, if one RxBD is followed by one TxBD, RBASE contains 0x0000, and TBASE contains 0x0008, then the RxBD is located at IMM + 0x0000 and the TxBD is located at IMM + 0x0008. The data buffers can reside in the internal dual-port RAM.
Serial Peripheral Interface (SPI) shifts transmit data out on SPIMOSI and receive data in on SPIMISO. Received data is written into a receive buffer using the next available RxBD. 3. The SPI transmits and receives data until the entire buffer is sent or an error occurs. The CP clears TxBD[R] after the buffer is sent and clears RxBD[E] to indicate that the buffer is full. 4.
Operating the SPI as a Master The following example shows the steps required to initialize the SPI as a master. The master SPI drives the SCLK signal. The assumptions underlying this example are: ■ IMM is a pointer to the MSC8101 registers in the PowerPC system bus address spaces and is initialized to 0xF0000000. ■ SPIPRAM is a pointer to the SPI parameter RAM. ■ RxTxBD is a pointer to the buffer descriptors RxBD and TxBD. ■ One RxBD and one TxBD are used.
Serial Peripheral Interface (SPI) a. Configure the RxBD and TxBD. Since there is only one RxBD, it is the last BD in the table. Assume the buffer is empty and an interrupt is generated after the buffer is filled. RxTxBD->RxBD[0].bd_cstatus = 0xB000; Since there is only one TxBD, it is the last BD in the table. Assuming the buffer is ready, an interrupt is generated after the buffer is filled and the buffer contains the last character of the message. RxTxBD->TxBD[0].
Operating the SPI as a Slave 11.5 Operating the SPI as a Slave The state diagram in Figure 11-4 shows how the SPI transmits and receives characters as a master. The SPI is enabled by setting SPMODE[7]:EN=1. 1. Once the SPI is enabled, the start of data transfer is enabled: SPCOM[0]:STR=1. 2. TxBD[R] is set to indicate that the buffer is ready for transmission. Once SPISEL is asserted, the slave shifts data out on SPIMISO and shifts data in on SPIMOSI. 3.
Serial Peripheral Interface (SPI) The following example shows the steps required to initialize the SPI as a slave. The assumptions underlying this example are: ■ IMM is a pointer to the MSC8101 registers in the PowerPC system bus and PowerPC local bus address spaces. ■ SPIPRAM is a pointer to the SPI parameter RAM. ■ RxTxBD is a pointer to the buffer descriptors RxBD and TxBD. ■ One RxBD and one TxBD are used. The steps in initializing the SPI as a slave are as follows: 1.
Operating the SPI as a Slave 5. Configure MRBLR. Assume the maximum bytes per receive buffer is 16 bytes. SPIRAM->mrblr = 0x0010; 6. Configure the RxBD and TxBD. Since there is only one RxBD, it is the last BD in the table. Assume the buffer is empty and an interrupt is generated after the buffer is filled. RxTxBD->RxBD[0].bd_cstatus = 0xB000; Since there is only one TxBD, it is the last BD in the table.
Serial Peripheral Interface (SPI) 11.6 Responding to a Multi-master Error A multi-master error occurs when the SPISEL pin is asserted while the SPI is configured as a master because more than one SPI device is a bus master. To avoid this error, the SPISEL must be disabled as shown in Section 11.4, Operating the SPI as a Master, on page 11-5. Figure 11-5 shows how the SPI responds to a multi-master error.
Related Reading 11.7 Related Reading MSC8101 User’s Guide (This manual) Chapter 1, MSC8101 Overview Section 1.3.
Serial Peripheral Interface (SPI) 11-14 MSC8101 User’s Guide
Chapter 12 EOnCE/JTAG This chapter presents examples of how the EOnCE port can be used for system-level debugging of real-time systems. The following examples are presented: ■ Reading/writing EOnCE registers through JTAG ■ Executing a single instruction through JTAG ■ Writing to the EOnCE Receive Register (ERCV) ■ Reading from the EOnCE Transmit Register (ETRSMT) ■ Downloading software ■ Reading/writing the trace buffer ■ Using the EOnCE to perform profiling functions 12.
EOnCE/JTAG be issued to transition through the appropriate states. The first action that occurs when either block is entered is a Capture operation. The Capture-DR state captures the data into the selected serial data path, and the Capture-IR state captures status information into the instruction register. The Exit state follows the Shift state when shifting of instructions or data is complete.
EOnCE/JTAG Basics Table 12-1. JTAG Scan Paths Select-DR Scan Path Select-IR Scan Path Select-DR_SCAN Select-IR_SCAN Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Update-DR Update-IR 12.1.1 Instructions The host sends JTAG instructions to the MSC8101 least significant bit first. As Figure 12-2 shows, the TDI pin inputs the instruction into the MSC8101 and is sampled on the rising edge of TCK.
EOnCE/JTAG Table 12-2. JTAG Instructions B4 B3 B2 B1 B0 Instruction Description 0 0 0 0 0 EXTEST Selects the Boundary Scan Register. Forces a predictable internal state while performing external boundary scan operations. 0 0 0 0 1 SAMPLE/PRELOAD Selects the Boundary Scan Register. Provides a snapshot of system data and control signals on the rising edge of TCK in the Capture-DR controller state. Initializes the BSR output cells prior to selection of EXTEST or CLAMP.
EOnCE/JTAG Basics instructions are sent least significant bit first on TDI. If the TAP controller is in the Run-Test/Idle state, DEBUG_REQUEST is issued via JTAG, as shown in Figure 12-3. 1 2 3 4 5 6 7 8 9 10 11 TCK TMS TDI 1 1 1 0 0 Figure 12-3. Executing DEBUG_REQUEST The following sequence occurs at the rising edge of each TCK cycle: 1. TMS = 1 to enter the Select-DR state. 2. TMS = 1 to enter the Select-IR state. 3. TMS = 0 to enter the Capture-IR state. 4.
EOnCE/JTAG Table 12-3. EOnce Control Register (ECR) Bits Name 15–10 Settings Description Reserved. Write to zero for future compatibility. 9 R/W 8 GO Specifies the direction of a data transfer. 0 Write the data into the register specified by REGSEL 1 Read the data in the register specified by REGSEL 0 Inactive 1 Execute one instruction When EX is set, the SC140 core leaves Debug mode and resumes normal operation after executing the read or write command.
EOnCE/JTAG Basics Table 12-4. EOnce Register Summary (Continued) Address Offset Mnemonic 0A PC_DETECT ... Reserved 10 Register Width PC Breakpoint Detection Register 32 EDCA0_CTRL EDCA 0 Control Register 16 11 EDCA1_CTRL EDCA 1 Control Register 16 12 EDCA2_CTRL EDCA 2 Control Register 16 13 EDCA3_CTRL EDCA 3 Control Register 16 14 EDCA4_CTRL EDCA 4 Control Register 16 15 EDCA5_CTRL EDCA 5 Control Register 16 ...
EOnCE/JTAG Table 12-4. EOnce Register Summary (Continued) Address Offset Mnemonic Register Width 41 ECNT_VAL Counter Value Register 32 42 ECNT_EXT Extension Counter Value 32 ... Reserved 48 ESEL_CTRL Selector Control Register 8 49 ESEL_DM Selector DM Mask 16 4A ESEL_DI Selector DI Mask 16 4B Reserved 4C ESEL_ETB Selector Enable TB Mask 16 4D ESEL_DTB Selector Disable TB Mask 16 ...
EOnCE/JTAG Basics ■ Opcode (bits 19–4). Derive from the instruction opcode. These bits are reversed in order from the instruction opcode value. That is, bits 15–0 of the instruction opcode are reversed as bits 0–15 of the CORE_CMD register. ■ Immediate A (bits 33–20). Derive from the instruction immediate A value. These bits are reversed in order from the instruction immediate A value. The two most significant bits of the instruction immediate A value are not used.
EOnCE/JTAG 12.1.3.1 CORE_CMD Example 1 Instruction: move.l #0xdead,d0 Opcode: 0x30C0 3EAD 8000 CORE_CMD: 0x0002 D5F0 30C3 ImmA ImmB Opcode Prefix1[5, 7] Length 3 words 0x8000 0x3EAD 0x30C0 ImmA[15:0] 1000 0000 0000 0000 ImmB[15–0] 0011 1110 1010 1101 Opcode[15–0] 0011 0000 1100 0000 ImmA[0:13] 0000 0000 0000 00 ImmB[0–13] 1011 0101 0111 11 Opcode[0–15] 0000 0011 0000 1100 00 11 Prefix1[5, 7] Length Note: The 48-bit CORE_CMD register is the concatenation of the bits in boldface. 12.
Writing EOnCE Registers Through JTAG 12.1.3.4 CORE_CMD Example 4 Instruction: move.
EOnCE/JTAG Host MSC8101 CHOOSE_EONCE Shift in ‘1’ on TDI MSC8101 EOnCE device is selected. ENABLE_EONCE EOnCE is enabled and system debug functions can now be performed. Write into ECR: Write, no Go, ECNT_VAL ECNT_VAL register is selected. Write 32-bit data into ECNT_VAL Figure 12-5. Writing EOnCE Registers 12.3 Reading EOnCE Registers Through JTAG This section presents an example of the host reads from the SC140 core 32-bit Event Counter Value Register (ECNT_VAL) via JTAG.
Executing a Single Instruction Through JTAG Host MSC8101 CHOOSE_EONCE MSC8101’s EOnCE device is selected. Shift in ‘1’ on TDI EOnCE is enabled and system debug functions can now be performed. ENABLE_EONCE ECNT_VAL register is selected. Write into ECR: Read, no Go, ECNT_VAL Read 32-bit data from ECNT_VAL Figure 12-6. Reading EOnCE Registers 12.
EOnCE/JTAG Host MSC8101 CHOOSE_EONCE Shift in ‘1’ on TDI MSC8101’s EOnCE device is selected. DEBUG_REQUEST Debug request is granted and system debug functions can now be performed. Write into ECR: Write, Go, CORE_CMD CORE_CMD register is selected. Write 48-bit data into CORE_CMD The core executes the instruction written into the CORE_CMD register. Figure 12-7. Executing a Single Instruction Through JTAG 12.
Reading From the EOnCE Transmit Register (ETRSMT) Host MSC8101 CHOOSE_EONCE Shift in ‘1’ on TDI MSC8101 EOnCE device is selected. ENABLE_EONCE EOnCE is enabled and system debug functions can now be performed. Write into ECR: Write, no Go, ERCV ERCV register is selected. Write 64-bit data into ERCV RCV bit in ESR is set to indicate host has finished writing to the ERCV register. SC140 core can now read the ERCV. LSB is read first. RCV bit is cleared after MSB is read. Figure 12-8.
EOnCE/JTAG Host MSC8101 CHOOSE_EONCE Shift in ‘1’ on TDI MSC8101 EOnCE device is selected. ENABLE_EONCE EOnCE is enabled and system debug functions can now be performed. Write into ECR: Read, no Go, ETRSMT ETRSMT register is selected. Read 64-bit ETRSMT data ESR[]:TRSMT bit is set to indicate that the SC140 core has finished writing the MSB of the ETRSMT register. The TRSMT bit is cleared after ETRSMT is read. The host can now read the ETRSMT. The TRSMT bit is cleared after ETRSMT is read.
Downloading Software ECR[R/W] = 0 to perform a write access. ECR[GO] = 1 to execute the instruction. ECR[REGSEL] = 1111110 to select the CORE_CMD register. 7. Select-DR: Write 48-bit CORE_CMD data to move data from the lower 32-bits of the ERCV to an internal register. Assuming that address register r1 points to 0xEFFE08, the ERCV address, the following command moves the ERCV data into data register d1: move.l (r1)+,d1 The CORE_CMD value is 0x0000 0009 98A1. See Section 12.1.3.
EOnCE/JTAG Host MSC8101 CHOOSE_EONCE Shift in ‘1’ on TDI MSC8101 EOnCE device is selected. DEBUG_REQUEST Debug request is granted and system debug functions can now be performed. Write into ECR: Write, no Go, ERCV ERCV register is selected. RCV bit in ESR is set to indicate host has finished writing to the ERCV register. Write 64-bit data into ERCV Write into ECR: Write, Go, CORE_CMD CORE_CMD register is selected. Write 48-bit data into CORE_CMD move.
Writing and Reading the Trace Buffer 12.8 Writing and Reading the Trace Buffer This section presents an example that shows how the trace buffer is written and read. Table 12-5 shows the trace buffer register set: Table 12-5. Trace Buffer Register Set Register Description TB_CTRL Trace Buffer Control Register TB_RD Trace Buffer Read Pointer TB_WR Trace Buffer Write Pointer TB_BUFF Trace Buffer Virtual Register 1. Enable the trace buffer by setting TB_CTRL[TEN] = 1.
EOnCE/JTAG Because of the pre-fetch mechanism, a three-cycle delay must occur from the time the trace buffer is disabled until the first read access to the trace buffer is issued. 12.9 Using EE0 to Enter Debug Mode In the previous examples, the JTAG instruction DEBUG_REQUEST is used to enter Debug mode. Another method of entering Debug mode is to program the EE0 pin to cause the SC140 core to enter Debug mode after core reset.
Counting Core Cycles 3. Enable the event counter. The event counter is disabled but hardware enables it when EDCA #0 detects an event because ECNT_CTRL[ECNTEN] = 0001. In this example, the event counter is enabled when EDCA #0 detects the starting address. 4. Enable the event detection channels. Set EDCA0_CTRL[EDCAEN] = 1111 and EDCA1_CTRL[EDCAEN] = 1111 to enable the EDCA. 5. Set the reference values to be compared by the event detection channel comparators.
EOnCE/JTAG When the event counter counts the core clock, the memory contention and external wait state clocks are not counted. 12.11 Related Reading StarCore SC140 Core Reference Manual Chapter 4, Emulation and Debug (EOnCE) MSC8101 Reference Manual Chapter 17, JTAG and IEEE 1149.
Appendix A Programming Reference This reference for programmers includes a table summarizing the routing of programmable interrupt controller (PIC) interrupts, a table showing interrupt source priority levels for the internal and external SIU-CPM interrupt controllers (SIC and SIC_EXT), a table showing the SIC and SIC_EXT interrupt vectors, and programming sheets for key programmable MSC8101 registers, excluding the CPM registers.
Programming Reference Table A-1.
Interrupt Sources and Priorities Table A-2.
Programming Reference Table A-3.
Interrupt Sources and Priorities Table A-3.
Programming Reference Table A-3. SIC and SIC_EXT Interrupt Source Priority (Continued) Priority Level (Highest to Lowest) Description Multiple Events 72 YCC8 (Spread) Yes 73 Reserved — Pending unmasked interrupts are presented to the core in order of priority. The core reads SIVEC to get the interrupt vector. The interrupt vector gives the location of the interrupt service routine.
Programming Sheets Table A-4.
ETM – Compatibility Mode Enable, Bit 12 0 Strict PowerPC system bus mode.
PISCR SYSTEM INTERFACE UNIT (SIU) PISCR PTF – Periodic Interrupt Frequency, Bit 14 Periodic Interrupt Status and Control Register Address: 0x10240 Reset: 0 Read/Write 0 The input clock to the periodic interrupt timer is 4 MHz 1 The input clock to the periodic interrupt timer is 32 KHz MSC8101 User’s Guide PIE – Periodic Interrupt Enable, Bit 13 0 The periodic interrupt timer does not generate an interrupt 1 The periodic interrupt timer generates an interrupt when PS = 1 PTE – Periodic Timer Ena
SIUMCR Programming Reference A-10 SYSTEM INTERFACE UNIT (SIU) SIUMCR PBSE – Parity Byte Select Enable, Bit 2 0 Parity byte select is disabled 1 Parity byte select is enabled IRQ7INT – IRQ7 or INT_OUT Selection, Bit 3 SIU Module Configuration Register (page 1 of 2) Address: 0x10000 Reset: 0 Read/Write: Depends on reset configuration sequence 0 IRQ7/INT_OUT pin is IRQ7 1 IRQ7/INT_OUT pin is INT_OUT DPPC[0–1] – Data Parity Pin Configuration, Bits 4–5 MSC8101 User’s Guide ESE – External Snoop En
TCPC[0–1] – Transfer Code Pin Configuration, Bits 10–11 SIUMCR SYSTEM INTERFACE UNIT (SIU) SIUMCR Pin 00 01 10 11 MODCK1/BNKSEL0/TC0 TC0 RES BNKSEL0 RES MODCK2/BNKSEL1/TC1 TC1 RES BNKSEL1 RES MODCK3/BNKSEL2/TC2 TC2 RES BNKSEL2 RES SIU Module Configuration Register (page 2 of 2) Address: 0x10000 Reset: 0 Read/Write: Depends on reset configuration sequence BC1PC[0–1] – Buffer Control 1-Pin Configuration, Bits 12–13 Pin 00 MSC8101 User’s Guide BCTL1 01 BCTL1 BCTL1 10 11 RES RES
LBME – Local Bus Monitor Enable, Bit 25 0 PowerPC local bus monitor is disabled 1 PowerPC local bus monitor is enabled sypcr System Protection Control Register SWE – Software Watchdog Enable, Bit 29 Address: 0x10004 Reset: 0–15 1111_1111_1111_1111, 16–31 1111_1111_0000_0111 Read/Write MSC8101 User’s Guide PowerPC system bus monitor is disabled 1 PowerPC system bus monitor is enabled 0 Software watchdog timer is disabled 1 Software watchdog timer is enabled SWRI – Software Watchdog Reset/Inte
TMCNTSC SYSTEM INTERFACE UNIT (SIU) TMCNTSC ALE – Alarm Interrupt Enable, Bit 13 0 No alarm interrupt 1 The time counter generates an interrupt when ALR is set Timer Counter Status and Control Register Address: 0x10220 Reset: 0 Read/Write TCF – Time Counter Frequency, Bit 14 MSC8101 User’s Guide SIE – Once per Second Interrupt Enable, Bit 12 0 The time counter does not generate an interrupt when SEC is set 1 The time counter generates an interrupt when SEC is set 0 The input clock to the time
Programming Reference A-14 WP – Write Protect, Bit 23 BR MEMORY CONTROLLER BR[0–7, 10, 11] 0 Read and write accesses are allowed 1 Only read access is allowed MSEL[0–2] – Machine Select, Bits 24–26 Base Register 000 Address: BR0 (0x10100), BR1 (0x10108), BR2 (0x10110), BR3 (0x10118), BR4 (0x10120), BR5 (0x10128), BR6 (0x10130), BR7 (0x10138), BR10 (0x10150), BR11 (0x10158) Reset: 0–31 depends on reset configuration sequence, After a system reset, the V bit is set in BR0 and reset in BR[1–7, 10, 1
ACS[0–1] – Address to Chip-Select Setup, Bits 21–22 OR/GPCM MEMORY CONTROLLER OR[0–7, 10, 11] 00 CS is output at the same time as the address lines 01 Reserved 10 CS is output a quarter of a clock after the address lines 11 CS is output half a clock after the address lines GPCM Mode SCY[0–3] – Cycle Length in Clocks, Bits 24–27 Option Register Address: OR0 (0x10104), OR1 (0x1010C), OR2 (0x10114), OR3 (0x1011C), OR4 (0x10124), OR5 (0x1012C), OR6 (0x10134), OR7 (0x1013C), OR10 (0x10154), OR11 (0x
OR/SDRAM Programming Reference A-16 ROWST[0–3] – Row Start Address Bit, Bits 19–22 MEMORY CONTROLLER OR[0–7, 10, 11] PSDMR[PBI] = 0 0010 A7 1010 A11 0100 A8 1100 A12 SDRAM Mode 0110 A9 1110 A13 Option Register 1000 A10 Address: OR0 (0x10104), OR1 (0x1010C), OR2 (0x10114), OR3 (0x1011C), OR4 (0x10124), OR5 (0x1012C), OR6 (0x10134), OR7 (0x1013C), OR10 (0x10154), OR11 (0x1015C) Reset: 0 Read/Write 0000 A0 1100 A12 Other values are reserved PSDMR[PBI] = 1 0001 A1 1101–1111 Reserved
OR/UPM MEMORY CONTROLLER OR[0–7, 10, 11] UPM Mode BI – Burst Inhibit, Bit 23 Option Register 0 Bank supports burst accesses Address: OR0 (0x10104), OR1 (0x1010C), OR2 (0x10114), OR3 (0x1011C), OR4 (0x10124), OR5 (0x1012C), OR6 (0x10134), OR7 (0x1013C), OR10 (0x10154), OR11 (0x1015C) Reset: 0 Read/Write 1 Bank does not support burst accesses.
DSx[0–1] – Disable Timer Period, Bits 8–9 00 1 cycle disable period 10 3 cycle disable period 01 2 cycle disable period 11 4 cycle disable period G0CLx[0–2] – General Line 0 Control, Bits 10–12 Machine A/B/C Mode Registers Address: MAMR (0x10170), MBMR (0x10174), MCMR (0x10178) Reset: 0–15 0000_0000_0000_0100, 16–31 0000_0000_0000_0000 Read/Write 000 A12 010 A10 100 A8 110 A6 001 A11 011 A9 101 A7 111 A5 GPL_x4DIS – GPL_A4 Output Line Disable, Bit 13 AMx[0–2] – Address Multiplex S
PSDMR MEMORY CONTROLLER PSDMR (page 1 of 2) SDAM[0–2] – Address Multiplex Size, Bits 5–7 External Signal External Signal SDAM PowerPC Bus Driven on SDAM PowerPC Bus Driven on Address Pin External Pin Address Pin External Pin 60x Bus SDRAM Mode Register Address: 0x10190 Reset: 0 Read/Write 000 A[13–31] A[5–23] 011 A[16–31] A[5–20] 001 A[14–31] A[5–22] 100 A[17–31] A[5–19] 010 A[15–31] A[5–21] 101 A[18–31] A[5–18] BSMA[0–2] – Bank Select Multiplexed Address Line, Bits 8–10 OP[0–2] – SDRA
PSCMR/2 MEMORY CONTROLLER PSDMR (page 2 of 2) 001 1 clock cycle 111 7 clock cycles 010 2 clock cycles 000 8 clock cycles •••• 60x Bus SDRAM Mode Register BL – Burst Length, Bit 23 Address: 0x10190 Reset: 0 Read/Write 0 SDRAM burst length is 4 1 SDRAM burst length is 8 LDOTOPRE[0–1] – Last Data Out to Precharge, Bits 24–25 00 0 cycles 01 -1 cycle 10 -2 cycles 11 Reserved PRETOACT[0–2] – Precharge to Activate Interval, Bits 17–19 001 1 clock-cycle wait states 010 WRC[0–1] – Write
ELIRA INTERRUPT SCHEME ELIRA PIL[30–32, 20–22, 10–12, 0–2] – Priority Level for IRQ Input xx, Bits 1–3, 5–7, 9–11, 13–15 PIC Edge/Level-Triggered Interrupt Priority Register A Address: 0x1C00 Reset: 0 Read/Write PED[3, 2, 1, 0] – Trigger Mode for IRQ Input xx, Bits 0, 4, 8, 12 0 Level-triggered mode 1 Edge-triggered mode MSC8101 User’s Guide 0 1 2 3 4 5 6 7 8 9 10 Address: 0x1C08 Reset: 0 Read/Write PED[7, 6, 5, 4] – Trigger Mode for IRQ Input xx, Bits 0, 4, 8, 12 Level-triggered mode 1
ELIRC PIL[110–112, 100–102, 90–92, 80–82] – Priority Level for IRQ Input xx, Bits 1–3, 5–7, 9–11, 13–15 PIC Edge/Level-Triggered Interrupt Priority Register C 000 Address: 0x1C10 Reset: 0 Read/Write PED[11, 10, 9, 8] – Trigger Mode for IRQ Input xx, Bits 0, 4, 8, 12 0 Level-triggered mode 1 Edge-triggered mode MSC8101 User’s Guide 0 1 2 3 4 5 6 7 8 9 10 Interrupts disabled 100 IPL4 001 IPL0 (lowest priority) 101 IPL5 010 IPL1 110 IPL6 011 IPL2/IPL3 111 IPL7 (highest priorit
ELIRE INTERRUPT SCHEME ELIRE PIL[190–192, 180–182, 170–172, 160–162] – Priority Level for IRQ Input xx, Bits 1–3, 5–7, 9–11, 13–15 PIC Edge/Level-Triggered Interrupt Priority Register E Address: 0x1C20 Reset: 1000_0000_0000_0000 Read/Write PED[19, 18, 17, 16] – Trigger Mode for IRQ Input xx, Bits 0, 4, 8, 12 0 Level-triggered mode 1 Edge-triggered mode MSC8101 User’s Guide 0 1 2 3 4 5 6 7 8 9 10 000 Interrupts disabled 100 IPL4 001 IPL0 (lowest priority) 101 IPL5 010 IPL1 110 I
SICR/SICR_E XT Programming Reference A-24 INTERRUPT SCHEME SICR/SICR_EXT GSIU – Group SIU, Bit 14 SIU Interrupt Configuration Register 0 Grouped. The XSIUs are grouped by priority at the top of the table 1 Spread. The XSIUs are spread by priority in the table Address: SICR (0x10C00), SICR_EXT (0x10C40) Reset: 0 Read/Write SPS – Spread Priority Scheme, Bit 15 HP[0–5] – Highest Priority, Bits 2–7 To retain the original priority, program HP to the interrupt number assigned to XSIU1 0 Grouped.
CONT – Continuous Buffer Mode, Bit 2 BD_ATTR DIRECT MEMORY ACCESS (DMA) BD_ATTR 0 Buffer is closed when BD_SIZE reaches zero 1 Buffer continues operating when BD_SIZE reaches zero Buffer Attributes Parameter (page 1 of 2) 0 Increment address after request is serviced Reset: Undefined Read/Write 1 Do not increment address after request is serviced NO_INC – Increments Address, Bit 4 BP[0–1] – Bus Priority, Bits 5–6 MSC8101 User’s Guide 0 1 CYC – Cyclic Address, Bit 1 00 Sequential address.
BD_ATTR 2 Programming Reference A-26 FLS – Flush FIFO, Bit 26 DIRECT MEMORY ACCESS (DMA) BD_ATTR 0 Do not flush FIFO 1 Flush FIFO 0 Write transaction 1 Read transaction RD – Read Channel, Bit 27 Buffer Attributes Parameter (page 2 of 2) Reset: Undefined Read/Write TSZ[0–2] – Transfer Size, Bits 22-24 MSC8101 User’s Guide 100 TC – Transfer Code, Bit 29 Max transfer size is one burst 001 Max transfer size is 8 bits 010 Max transfer size is 16 bits 011 Max transfer size is 32 bits 101
DCHCR DIRECT MEMORY ACCESS (DMA) DCHCR[0–15] EXP[0–2] – Expiration Timer, Bits 5–7 The channel will ignore level request to ‘EXP+1’ bus cycles after the assertion of DRACK or DACK signal, as defined by DRACK bit DMA Channel Configuration Register (page 1 of 2) DRS – DREQ Sensitivity Mode, Bit 8 MSC8101 User’s Guide Address: DCHCR0 (0x10700), DCHCR1 (0x10704), DCHCR2 (0x10708), DCHCR3 (0x1070C), DCHCR4 (0x10710), DCHCR5 (0x10714), DCHCR6 (0x10718), DCHCR7 (0x1071C), DCHCR8 (0x10720), DCHCR9 (0x10724),
RQNUM[0–4] – Requestor Number, Bits 19–23 DCHCR DMA Channel Configuration Register (page 2 of 2) Address: DCHCR0 (0x10700), DCHCR1 (0x10704), DCHCR2 (0x10708), DCHCR3 (0x1070C), DCHCR4 (0x10710), DCHCR5 (0x10714), DCHCR6 (0x10718), DCHCR7 (0x1071C), DCHCR8 (0x10720), DCHCR9 (0x10724), DCHCR10 (0x10728), DCHCR11 (0x1072C), DCHCR12 (0x10730), DCHCR13 (0x10734), DCHCR14 (0x10738), DCHCR15 (0x1073C) Reset: 0 Read/Write 00000 HDI16 read request 01000 External request 1, DREQ1 00001 HDI16 write request 0100
FISL – Filter Input Scale, Bit 9 FACR ENHANCED FILTER COPROCESSOR (EFCOP) FACR MSC8101 User’s Guide Shared Convergent rounding 01 Two’s complement rounding 10 Truncation (no rounding) 11 Reserved FSCL[0–1] – Filter Scaling, Bits 14–15 00 FSCO – Filter Shared Coefficients Mode, Bit 8 1 Scales IIR feedback terms only FRM[0–1] – Filter Rounding Mode, Bits 12–13 Address: 0x0CA0 Reset: 0 Read/Write Not shared Scales both IIR feedback terms and IIR input 1 00 EFCOP ALU Control Register 0 0
FCTL FOFIE – Data Output Full Interrupt Enable, Bit 3 Address: 0x0C80 Reset: 0 Read/Write Data output buffer full interrupt enabled 0 Data input buffer not full interrupt disabled 1 Data input buffer not full interrupt enabled FIEIE – Data Input Empty Interrupt Enable, Bit 5 FONEIE – Data Output Not Empty Interrupt Enable, Bit 2 MSC8101 User’s Guide 0 Data output buffer not empty interrupt disabled 1 Data output buffer not empty interrupt enabled 0 Data input buffer empty interrupt disabled
FOM[0–1] – Filter Operation Mode, Bits 10–11 FCTL ENHANCED FILTER COPROCESSOR (EFCOP) FCTL 00 Mode 0: Real FIR filter 01 Mode 1: Full complex FIR filter 10 Mode 2: Complex FIR filter with alternate real and imaginary outputs 11 Mode 3: Magnitude FUPD – Filter Update, Bit 12 MSC8101 User’s Guide EFCOP Control Register (page 2 of 2) 0 Update mode disabled Address: 0x0C80 Reset: 0 Read/Write 1 Update mode enabled FADP – Filter Adaptive Mode, Bit 13 FMLC – Filter Multichannel Mode, Bit 9 0 Mu
HCR DBTE – DMA Transmit Burst Enable, Bit 9 0 DMA transmit burst mode disabled 1 DMA transmit burst mode enabled DBRE – DMA Receive Burst Enable, Bit 10 Host Control Register Address: 0x0000 Hardware Reset: 0, Individual Reset: All bit values are indeterminate after reset Read/Write 0 DMA receive burst mode disabled 1 DMA receive burst mode enabled HCIE – Host Command Interrupt Enable, Bit 11 HDM[0–2] – Host DMA/Last Address Mode, Bits 5–7 0 Host command interrupt disabled 1 Host command inter
DBTE – DMA Transmit Burst Enable, Bit 9 HCR/2 HOST INTERFACE (HDI16) HCR (HICR=1) 0 DMA transmit burst mode disabled 1 DMA transmit burst mode enabled DBRE – DMA Receive Burst Enable, Bit 10 Host Control Register Address: 0x0000 Hardware Reset: 0, Individual Reset: All bit values are indeterminate after reset Read/Write: 0–4, 8–15 Read Only: 5–7 0 DMA receive burst mode disabled 1 DMA receive burst mode enabled HCIE – Host Command Interrupt Enable, Bit 11 0 Host command interrupt disabled 1 H
HPC1 HDDS – Host Dual Data Strobe, Bit 3 0 HDI16 operates in single-strobe bus mode 1 HDI16 operates in dual-strobe bus mode HDSP – Host Data Strobe Polarity, Bit 6 Host Port Control Register Address: 0x0020 Hardware Reset: 0, Individual Reset: All bit values are indeterminate after reset Read/Write 0 Data strobe signals are configured as active low inputs 1 Data strobe signals are configured as active high inputs HEN – Host Enable, Bit 8 0 HDI16 host interface disabled MSC8101 User’s Guide 1 H
HOST INTERFACE (HDI16) ICR (DMA=0, DMA=1, HICR=0) HDRQ – HREQ/HTRQ and HACK/HRRQ Pin Control, Bit 13 ICR (DMA=0, HICR=0) Interface Control Register 0 HREQ/HTRQ and HACK/HRRQ pins function as HREQ and HACK, respectively 1 HREQ/HTRQ and HACK/HRRQ pins function as HTRQ and HRRQ, respectively Note 1: If ICR (DMA=0, HICR=0) then this pin functions as HDRQ; otherwise, this bit is reserved and should be written to zero Address: 0x0 Hardware Reset: 0, Individual Reset: All bit values are indeterminate after
ICR2 ICR (DMA=0, HICR=1) Interface Control Register 0 HREQ/HTRQ and HACK/HRRQ pins function as HREQ and HACK, respectively 1 HREQ/HTRQ and HACK/HRRQ pins function as HTRQ and HRRQ, respectively Note 1: If ICR (DMA=0, HICR=1) then this pin functions as HDRQ; otherwise, this bit is reserved and should be written to zero Address: 0x0 Hardware Reset: 0, Individual Reset: All bit values are indeterminate after reset Read/Write TREQ – HREQ and HTREQ Pin Control, Bit 14 HPCR[DMA] 0 HF[2–3] – Host Flags 2
Appendix B Glossary This glossary presents an alphabetical list of terms, phrases, and abbreviations that are used in this manual. Many of the terms are defined in the context of how they are used in this manual—that is, in the context of the MSC8101. Some of the definitions are derived from Newton’s Telecom Dictionary: The Official Dictionary of Telecommunications, © 1998 by Harry Newton. AAL ATM adaptation layer.
Glossary AGU Address generation unit. One of the execution units in the MSC8101. The AGU performs effective address calculations using the integer arithmetic necessary to address data operands in memory, and it contains the registers to generate the addresses. It performs four types of arithmetic: linear, modulo, multiple wrap-around modulo, and reverse-carry. The AGU operates in parallel with other chip resources to minimize address generation overhead.
baseband The original band of frequencies of a signal before it is modulated for transmission at a higher frequency. The signal is typically multiplexed and sent on a carrier with other signals at the same time. See also broadband. beat A single state on the MSC8101 interface that may extend across multiple bus cycles. An MSC8101 transaction can be composed of multiple address or data beats.
Glossary broadband Also called wideband. A type of data transmission in which a single medium (wire) can carry several channels at once. Cable TV, for example, uses broadband transmission. In contrast, baseband transmission allows only one signal at a time. Most communications between computers, including the majority of local-area networks, use baseband communications. An exception is B-ISDN networks, which employ broadband transmission. See also baseband.
CPM Communications processor module. One of three internal modules in the MSC8101: CPM, SIU, and SC140 extended core. The CPM consists of much more than PIO ports. The brains of the CPM is the communications processor (CP), a 32-bit RISC microcontroller that resides on a separate bus from the SC140 core and performs tasks independently of the SC140 core. The CP handles lower-layer communications tasks and DMA control, freeing the SC140 core to handle higher-layer activities.
Glossary DMA Direct memory access. A fast method of moving data from a storage device to RAM, which speeds up processing. The MSC8101 multi-channel DMA controller supports up to 16 time-multiplexed channels and buffer alignment by hardware. The DMA controller connects to both the PowerPC system bus and the local PowerPC bus and can function as a bridge between both buses. The MSC8101 DMA controller supports flyby transactions to either bus.
E1 The European equivalent of the North American T1, except that E1 carries information at the rate of 2.048 Mbps. This is a telephony standard. Its size is based on the number of channels, each of which carries 64 Kbps. See also T1. EFCOP Enhanced filter coprocessor. A peripheral MSC8101 module that functions as a general-purpose, fully programmable complex filter.
Glossary FCC Fast communications controllers. A type of serial communications controller (SCC) optimized for synchronous high-rate protocols. MSC8101 FCCs can be configured independently to implement different protocols. Together, they can implement bridging functions, routers, and gateways; they can interface with a wide variety of standard WANs, LANs, and proprietary networks.
FIR Finite impulse response. A type of filter. FIR filters are characterized by transfer functions that are polynomials, where the coefficients are directly the impulse response of the filter. The most common implementation of an FIR filter is the direct form with the recursive section removed. The form of an FIR filter gives rise to the terminology of tapped delay line and the coefficients as tap weights.
Glossary GPCM General-purpose chip-select machine. Part of the MSC8101 memory controller. The GPCM provides interfacing for simpler, lower-performance memory resources and memory-mapped devices. The GPCM has inherently lower performance because it does not support bursting. For this reason, GPCM-controlled banks are used primarily for boot-loading and access to low-performance memory-mapped peripherals. The MSC8101 GPCM controls Bank 11, which is assigned for DSP peripherals.
MAC Multiply and accumulate. On the SC140 core, the MAC unit is the main arithmetic processing unit. It performs all the calculations on data operands. The MAC unit outputs one 40-bit result in the form of [Extension:Most Significant Portion:Least Significant Portion] (EXT:MSP:LSP). The multiplier executes 16-bit x 16-bit fractional or integer multiplication between two’s complement signed, unsigned, or mixed operands.
Glossary MII Media independent interface. Part of the Fast Ethernet specification, the MII replaces 10BaseT AUI (Attachment Unit Interface) and connects the MAC layer to the physical layer. The MII is the standard for all three 100Base-T specifications: 100Base-TX, 100Base-T4, and 100Base0Fx. The MII interface can be used for both 100Base-T and 10Base-T. MSC8101 MII support includes four bits of data for transmit and four bits of data for receive.
PIC Program interrupt controller. A peripheral module to serve all the interrupt requests (IRs) and non-maskable interrupts (NMIs) received from MSC8101 peripherals and I/O pins. The PIC is memory mapped to the SC140 core and is accessed via the SC140 core QBus. The PIC not only handles incoming interrupts from internal and external devices, but also generates interrupts to other devices.
Glossary SCC Serial communications controller. The MSC8101 has four SCCs, which can be configured independently to implement different protocols for bridging functions, routers, and gateways and to interface with a wide variety of standard WANs, LANs, and proprietary networks. An SCC offers many physical interface options, such as interfacing to TDM buses, ISDN buses, and standard modem interfaces.
SIU System interface unit. Controls system start-up and initialization, as well as operation, protection, and the external system bus. The system configuration and protection functions provide various monitors and timers, including the bus monitor, software watchdog timer, periodic interrupt timer, and time counter. The clock synthesizer generates the clock signals for the SIU and other MSC8101 modules. slave The device addressed by the master.
Glossary SRAM Static random access memory. Contrast with dynamic random access memory (DRAM). The dynamic nature of the circuits for DRAM require data to be written back after being read, hence the difference between the access time and the cycle time and also the need to refresh. SRAMs use more circuits per bit to prevent the information from being disturbed when read. Thus, unlike DRAMs, there is no difference between access time and cycle time, and there is no need to refresh SRAM.
transaction A complete exchange between two bus devices. A typical transaction is composed of an address tenure and a data tenure, which may overlap or occur separately from the address tenure. A transaction can minimally consist of an address tenure alone. TSA Time-slot assigner. A functional block within the MSC8101 CPM that connects the time-division multiplexing (TDM) interfaces to selected communications controllers inside the MSC8101.
Glossary Appendix B-18 MSC8101 User’s Guide
Appendix C Bootloader Program This appendix lists the boot program for the MSC8101. ;;/****************************************************************/ ;;/* */ ;;/* File : boot_code_rev0.asm */ ;;/* */ ;;/* (C) Copyright Motorola Inc, 2000.
Bootloader Program ;; HOST registers addresses definitions ;; dsp side HCR equ BASE0_D+$0000 HPCR equ BASE0_D+$0020 HSR equ BASE0_D+$0040 HCVR equ BASE0_D+$0060 HOTX equ BASE0_D+$0080 HORX equ BASE0_D+$00a0 ELIRE equ BASE0_D+$1c20 ELIRF equ BASE0_D+$1c28 Fmain ;---------- illegal exception offset 0x80 ---------section illegal_exception org p:$0080+BASE_exception_TABLE illegal_exception rte endsec ;---------- trap exception offset 0xc0 ---------section debug_exception org p:$00c0+BASE_exception_TABLE debug_
endsec ;---------- auto ir exception offset 0x1c0 ---------section auto_ir_exception org p:$01c0+BASE_exception_TABLE auto_ir_exception rte endsec ;---------- in address 0 goto 0x200 ------------section start org p:$0000+BASE_ROM_ADDRESS start ;; exception stack pointer initialization move.l #BASE_exception_TABLE,vba move.l #STACK_ADDR,r0 nop tfra r0,sp ; init ESP ; init vba ;; stack initialization move.l #0,d3 move.
Bootloader Program ;; calculating the checksum ; during the loading process the check sum is calculated for the whole ; long and at the end of the block the two words in the calculated ; checksum are xored with each other to get the real checksum Fmain move.l emr,d1 extractu #3,#19,d1,d3 ; d3 xor 3’b100 to recover original isb eor #$4,d3.l nop jmp find_siubase return_find_siu ; SRAM INIT jmp sram_init return_sram_init ; initialize ELIRE move.w #$8000,d0 nop move.w d0,ELIRE ; initialize ELIRF move.
; d3 xor 3’b100 to recover original isb eor #$4,d3.l ;r3 <- d3 move.l d3,r3 nop ; FIND IMMR FROM ISB ;r3 *= 4 so the offset will be in long instead of bytes ;r3 = r3<<2 asl2a r3 ;put the address of the external memory boot table in r4 move.l #EXTERNAL_MEM_BOOT_TABLE,r4 nop adda r4,r3 nop ;move the address from the table into r3 move.l (r3),r3 nop ;jump to that address jmp r3 from_host ;disables software watchdog move.l (r6+$4),d1 ;;sypcr,d1 and #$fffffffb,d1,d1 move.
Bootloader Program ;write checksum , ~checksum at the and of the block move.l d5,(r3) ;calculate the checksum of these words eor d4,d7 ;calculate ~checksum -> d2 ;get the real checksum from d7 and ;get it into d7.
;move the size into d6 move.l d4,d6 ;move the address into r3 move.l d5,r3 ;; check if the finished bit is set ,if it is set clear it ;; and the sticky bit . ( it means there was an error and ;; the blocks are being loaded for the second time) move.w HCR,d4 bmtsts.w #$8000,d4.l jf continue_loading_16 move.w HCR,d4 and #$6fff,d4.l move.
Bootloader Program load_8bit ;d7 = 0 , checksm =0 clr d7 ;load the size into d6 jsr load_from_fifo ;; check if the finished bit is set ,if it is set clear it ;; and the sticky bit .( it means there was an error and ;; the blocks are being loaded for the second time move.w HCR,d6 bmtsts.w #$8000,d6.l jf continue_loading_8 move.w HCR,d6 and #$6fff,d6.l move.w d6,HCR continue_loading_8 move.
and #$0000ffff,d7,d7 ;d7 = d7 ^ d2 eor d2,d7 ;d2 = (~d7 & 0x0000ffff) = ~checksum not d7,d2 and #$0000ffff,d2,d2 ;load the checksum ,~checksum jsr load_from_fifo ;get ~checksum into d4 extractu #16,#16,d5,d4 ;delete the ~checksum from d4 and #$0000ffff,d5,d5 ;if ( checksum_loaded |= Checksum_calculated ) goto set sticky bit cmpeq d5,d7 iff jsr set_sticky_bit ;if ( ~checksum_loaded |= ~Checksum_calculated ) goto set sticky bit ;clean d5.
Bootloader Program and #$0000ffff,d4,d4 ;if ( checksum_loaded |= Checksum_calculated ) goto set sticky bit cmpeq d4,d7 iff jsr set_sticky_bit ;clean d5.h and #$0000ffff,d5,d5 ;if ( ~checksum_loaded |= ~Checksum_calculated ) goto set sticky bit cmpeq d5,d2 iff jsr set_sticky_bit ;set hf7 bit in HCR to show that loading is finished move.w HCR,d6 or #$00008000,d6.l move.w d6,HCR ;check if the check sticky bit is set ( hf0 in HSR (HSR[12] ) move.
;d7 eor ;d2 not and = d7 ^ d2 d2,d7 = (~d7 & 0x0000ffff) = ~checksum d7,d2 #$0000ffff,d2,d2 ;get ~checksum into d4 extractu #16,#16,d5,d4 ;delete the ~checksum from d5 and #$0000ffff,d5,d5 ;if ( checksum_loaded |= Checksum_calculated ) goto set sticky bit cmpeq d5,d7 iff jsr set_sticky_bit ;clean d4.h and #$0000ffff,d4,d4 ;if ( ~checksum_loaded |= ~Checksum_calculated ) goto set sticky bit cmpeq d4,d2 iff jsr set_sticky_bit ;set hf7 bit in HCR to show that loading is finished move.w HCR,d6 or #$8000,d6.
Bootloader Program move.2l (r0),d4:d5 rts set_sticky_bit ;set the hf6 bit in HCR move.w HCR,d6 or #$00001000,d6.l move.w d6,HCR rts find_siubase cmpeq.w #$0,d3 nop ift move.l #$f0000000,d1 isb1 cmpeq.w #$1,d3 nop ift move.l #$f0f00000,d1 isb2 cmpeq.w #$2,d3 nop ift move.l #$ff000000,d1 isb3 cmpeq.w #$3,d3 nop ift move.l #$fff00000,d1 isb5 cmpeq.w #$5,d3 nop ift move.l #$00f00000,d1 isb6 cmpeq.w #$6,d3 nop ift move.l #$0f000000,d1 isb7 cmpeq.w #$7,d3 nop ift move.l #$0ff00000,d1 isb4 cmpeq.
move.l d1,r6 move.l #$02000000,d1 move.l d1,r5 ; bmset #$00c1,d1.l move.l #$fff80000,d7 move.l d7,(r6+$154) move.l d1,(r6+$150) ; gpcm_init move.l #$ffff0000,d1 move.l #$01f00021,d0 move.l d1,(r6+$15c) move.l d0,(r6+$158) jmp return_sram_init ; base address for sram is 0x0200_0000 ; SET OR10 ; SET BR10 ; ; ; ; SET SET SET SET OR11 BR11 OR11 BR11 MASK 64 KB TO $01f0_0000 MASK 64 KB TO $01f0_0000 upmc_init ;; -------------- READ SINGLE ------------------------------------move.l #$90051240,d7 move.
Bootloader Program move.w #$0,(r5) move.l #$00030044,d7 move.l d7,(r6+$188) ; move.w #$0,(r5) move.l #$00030045,d7 move.l d7,(r6+$188) ; ; ; move.w #$0,(r5) ; ;; -------------- WRITE SINGLE ------------------------------------move.l #$90051258,d7 move.l d7,(r6+$178) ; move.l #$00000040,d7 move.l d7,(r6+$188) ; cmpeq.w #$2,d3 jf continue_upmc2 move.w #$0,(r5) move.l #$00000040,d7 move.l d7,(r6+$188) continue_upmc2 move.w #$0,(r5) move.l #$00000045,d7 move.l d7,(r6+$188) ; ; ; ; move.
move.w #$0,(r5) move.l #$00000045,d7 move.l d7,(r6+$188) ; ; move.w #$0,(r5) ; ;; -------------- EXCEPTION ------------------------------------move.l #$9005127c,d7 move.l d7,(r6+$178) ; move.l #$ff000001,d7 move.l d7,(r6+$188) ; move.w #$0,(r5) ; ;; -------------- RESUME NORMAL OPERATION ------------------------move.l #$80011240,d7 move.
Bootloader Program C-16 MSC8101 User’s Guide
Appendix D Acronyms and Abbreviations A A AACK AAL AAU ABB ABI ABR ACR ADM ADSL ADTF AGU ALE ALU AM APC ARTRY ASIC ATM ATOM1 address bus signal (A[0–31]) address acknowledge signal ATM adaptation layer address arithmetic unit address bus busy signal application binary interface available bit rate allowed cell rate application development module asymmetric digital subscriber line ACR decrease time factor address generation unit address latch enable signal arithmetic logic unit address mode ATM pace control
CHAMR Channel Mode Register C/I command/indication (channel) CI congestion indication CLP cell loss priority CLSN collision signal CM continuous mode CMX CPM multiplexing logic CMXFCR CMX FCC Clock Route Register CMXSCR CMX SCC Clock Route Register CMXSIxCR CMX SI[1–2] Clock Route Registers CMXSMR CMX SMC Clock Route Register CMXUAR CMX UTOPIA Address Register COL collision detect CP communications processor, also called the RISC microcontroller CPCR CP Command Register CP-CS common parts of the convergence
ENQ EOB EOnCE EPD EPROM enquiry character end-of-burst (data) Enhanced On-Chip Emulation early packet discard erasable programmable read-only memory ER explicit rate ESP exception stack pointer ETB end-of-block ETX end-of-text character EVM evaluation module EXT_BG external bus grant signal EXT_BR external bus request signal EXT_DBG external data bus grant signal FMAC FMC FPR FPSCR FPSMR FPU F-RM FSB FSTR FTIRR FTODR F FACR FCBA EFCOP ALU Control Register EFCOP Coefficient Base Address Register FC-PB
HD HDDS HDI16 HDLC HDS HDSP H8BIT HORX HOTX HPCR HRD HREQ HRESET HRRQ HRW HSR HTRQ HW HWR Hz (core-side) host data bus signal host dual data strobe signal host interface (enhanced 16-bit parallel host interface) high-level data link control protocol host data strobe host data strobe polarity signal 8-bit mode control signal Host Receive Data Register (core-side) Host Transmit Data Register (core-side) Host Port Control Register (core-side) host read strobe signal host request signal hard resest signal host
LDMTEA Local PowerPC Bus DMA Transfer Error Address Register LDMTER Local PowerPC Bus DMA Transfer Error Requestor Number Register LDTEA Local PowerPC Bus SDMA Transfer Error Address Register LDTEM Local PowerPC Bus SDMA Transfer Error MSNUM LIFO last-in/first-out LR Link Register LRC longitudinal redundancy checking LRU least recently used lsb least-significant bit LSB least-significant byte LSU load/store unit L_TESCR Local Bus Transfer Error Status and Control Register M MAC MAC MAMR MAR Mb MB MBMR MBS
PCM PCMCIA pulse-code modulation Personal Computer Memory Card International Association PCR peak cell rate PCU program control unit PD general-purpose I/O port D signal PDAT Port A–D Data Register PDIR Port A–D Data Direction Register PDMTER PPC 60x Bus DMA Transfer Error Requestor Number Register PDTEA PPC 60x Bus SDMA Transfer Error Address Register PDTEM PPC 60x Bus SDMA Transfer Error MSNUM Register PDU program dispatch unit PGPL PPC 60x Bus UPM general-purpose signal PGTA 60x GPCM TA signal PHY physi
RQNUM RSCFG requestor number Reset Configuration Registers (host-side) RSR Reset Status Register RSTATE receiver state RSTCONF reset configuration signal RSTRT receive start signal RTER RISC (CP) Timer Event Register RTMR RISC (CP) Timer Mask Register RTOS real-time operating system RTSCR RISC Time-Stamp Control Register RTSR RISC (CP) Time-Stamp Register RWITM read with intent to modify Rx receive RX Receive Word Registers (host-side) RxBD receive buffer descriptor RxCLAV receive cell available signal RX_
SPIM SPLL SPLL MF SPLL PDF SPMODE SPR SR SRAM SRESET SRR SRTS SS7 SWR SWSR SYNC SYPCR SPI Mask Register system PLL SPLL multiplication factor SPLL pre-division factor SPI Mode register Special-Purpose Register Status Register static random access memory soft reset signal machine status save/restore registers[0–1] synchronous residual time stamp Signaling System 7 Software Watchdog Register Software Service Register synchronization character System Protection Control Register T T1 TA TAP TB TBST TC TCC TCK
UNI UPM UPM USART USB UTOPIA user-network interface user-programmable machine user-programmable machine universal synchronous/asynchronous receiver/transmitter universal serial bus universal test and operations physical layer interface V VA VAB VBA VBR VC VCIF VCLT VEA VLES VPLT VRC virtual address vector address bus Vector Base Address Register variable bit rate virtual channel VCI Filtering VC-level table virtual environment architecture variable-length execution set VP-level address compression table
D-10 MSC8101 User’s Guide
Index Numerics 300 MHz clock at 1.
receive buffer descriptor (RxBD) table 1-13 RxBD buffer pointer 1-14 RxBD data length 1-14 RxBD processing example 1-18 status and control 1-14 structure common to all serial controllers 1-13 transmit buffer descriptor (TxBD) table 1-13 TxBD buffer pointer 1-14 TxBD data length 1-14 TxBD data length.
DMA FIFO peripheral data transfers 6-5 DMA FIFO to memory data transfers 6-4 DMA Internal Mask Register (DIMR) 6-7 DMA Pin Configuration Register (DPCR) 6-7 DMA Status Register (DSTR) 6-7 dual access to transfer 16 bytes of data from external flash memory to external SDRAM 6-21 dual-access transaction 6-2 enable generation of interrupt requests to their associated interrupt controllers 6-9 enable interrupts 6-13 enable the interrupts 6-13 equate labels 6-15 example of flyby data transfer with an internal pe
eliminate clock skews 2-2 enhanced filter coprocessor (EFCOP) 1-4 Adaptive and Multichannel modes 9-4 Adaptive mode 9-4 Adaptive or Multichannel modes and decimation 9-7 Alternating Complex mode 9-6, 9-8 basics of adaptive filtering.
downloading software 12-1 entering Debug mode 12-20 EOnCE Control Register (ECR) 12-5 EOnCE registers 12-5 event counter, event detection, and event selector register sets 12-20 executing a JTAG instruction 12-4 executing a single instruction through JTAG 12-1, 12-13 Exit state 12-2 host sends data to the MSC8101 or receives status information from the MSC8101 12-1 host sends JTAG instructions to MSC8101 12-1 how software is downloaded from the host to the DSP via JTAG 12-16 how the host writes an instructi
activate the DMA 8-21 as asynchronous interface 4-14 broadcast bootstrap code to all devices 4-15 clearing an interrupt 8-16 define the size of the data transferred 8-5 determine the data transfer size 8-5 determine when the PIC accepts command 8-24 determine whether current data is last data to be transferred 8-16 DMA mode 8-3 DMA permits data transfers between memory (external on PowerPC system bus or internal) 8-20 double host requests enabled 8-19 downloads initialization bootstrap code 4-14 DSP-side co
Host Transmit Not Full bit in the Host Status Register 8-14 host-side Receive Data Registers (RX) 8-6 host-side Transmit Data Registers (TX) 8-6 how interrupt source status bits and masking bits operate to generate an interrupt 8-16 indicate a request for a data transfer (receive or transmit) 8-10 indicate which register (HCR or ICR) defines the data size 8-8 initialize and enable the HDI16 port 8-11 initialize the HDI16 port in DMA mode 8-12 interrupts 8-15 minimum hardware set-up necessary for use in Norm
assign priority 5 to the SIC interrupt 7-9 clear an edge-triggered interrupt request 7-13 clear pending requests 7-9 disable interrupts instruction 7-6 edge-triggered IRs and NMIs 7-3 edge-triggered/level-triggered interrupt priority registers 7-4 edge-triggered/level-triggered modes 7-3 enable interrupts instruction 7-6 encoding the interrupt vector A-6 external SIU-CPM interrupt controller (SIC_EXT) 7-1 interrupt pending registers 7-6 interrupt vector A-6, B-10 non-maskable interrupts (NMIs) 7-5 pending i
define a base for the Transmit (Tx) and Receive (Rx) buffer descriptor (BD) rings 10-10 define interrupt queue addresses 10-10 define mapping of MCC channel blocks to a TDM pin interface 10-11 define number of receive frame interrupts that cause an interrupt to the core 10-10 define the activation of the TDM channels for each SI 10-16 define the initial MCC state 10-10 define the maximum buffer size 10-10 determine which non-masked events are passed to the interrupt queue assigned to the channel.
P packaging 1-6 page-based interleaved configuration (PSDMR PBI bit = 1) 4-8 page-based interleaving 4-8, 4-13 parallel arithmetic operations B-5 parameter RAM for all SCC protocols 1-16 periodic interrupt timer 1-3 Peripheral Interrupt Controller (PIC) 6-9 phase lock between the PowerPC system bus clock and CLKIN 2-3 phase-locked loops (PLLs) 2-2 phase-locking mechanism for skew elimination 2-2 PIC 5-3, 7-2 Edge/Level triggered Interrupt Priority Registers (ELIRx) 8-16, 8-23 Interrupt Pending Registers (IP
RSTCONF 2-5, 2-9, 2-10, 2-14 RxBD buffer pointer 1-14 S SC100 DSP cores 1-1 SC140 application development methodology 3-1 SC140 core 1-6, 5-1 SCC UART mode 1-18 SDMA channels bus arbitration 5-11 bus transfers 5-11 SDMA Status Register (SDSR) 5-10 SDRAM address mask 5-7 address mask, lower 5-7 advantages 4-7 control commands 4-8 controller control settings 4-10 controller operation illustrated 4-1 controller, programmable timing parameters 4-10 in Single-Master MSC8101 Bus mode 4-7 JEDEC-compliant 4-7 SDRA
system-level debugging of real-time systems 12-1 T T1, CEPT, T1/E1,T3/E3, pulse code modulation highway, ISDN basic rate 1-5 target applications 1-5, 1-6 target markets media (voice/FAX/date) over packet gateways 1-1 wireless infrastructure systems 1-1 TDM backplanes/interconnects and WAN networks 10-1 TDM interfaces 1-5 TDM loopback 10-8 Test Mode Select (TMS) pin 12-1 time-division multiplexing (TDM) interfaces 10-1 time-slot assigner (TSA) 1-11, 10-1, 10-8 trace buffer 12-19 transcoder basestation 9-1 T
