Freescale Semiconductor, Inc. CONTENTS CHAPTER 3 FUNCTIONAL DESCRIPTION Freescale Semiconductor, Inc... 3.1 3.2 3.3 INTRODUCTION............................................................................................................. 3-1 EVB DESCRIPTION........................................................................................................ 3-1 MCU SUMMARY ............................................................................................................ 3-3 3.3.
Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... CONT CHAPTER GEN Motorola reserves the right to make changes without further notice to any products herein to 1 improve reliability, function, or design. Motorola does not assume any liability arising out of the 1.1 INTRODUCTION...................................... application or use of any product or circuit described herein; neither does it convey any license 1.2 FEATURES................................................
Freescale Semiconductor, Inc. GENERAL INFORMATION TAB Freescale Semiconductor, Inc... 1.3 GENERAL DESCRIPTION 1-1. EVB Specifications .................................... 1-2. External Equipment Requirements ............ The EVB is a low-cost tool for evaluating and debugging MPC505 MCU-based systems. The MPC505 MCU device is an advanced single-chip MCU with2-1. on-chip memory andTypes................................. peripheral Jumper Header functions.
Freescale Semiconductor, Inc. CONTENTS CHAP GENERAL IN 1.1 INTRODUCTION Freescale Semiconductor, Inc... This manual provides general information, hard support information for the MPC505EVB Evalu PowerPC MPC505 RISC Microcontrollers. 1.
Freescale Semiconductor, Inc. HARDWARE PREPARATION AND INSTALLATION to 2 megabytes by replacing the devices at lo devices. The flash memory devices require +5 vo There are a total of eight 52-pin PLCC sockets U31, and U32) for synchronous static RAM (SSR and lower words and organized for long-word (3 to as BANKx. Freescale Semiconductor, Inc... The SSRAM factory default for the EVB is 128 These devices have 9 nanosecond access times an be expanded to 256 kilobytes by replacing the devices.
Freescale Semiconductor, Inc. GENERAL INFORMATION 1.5 EQUIPMENT REQUIRED CHAP Table 1-2 lists the external equipment requirements for EVB operation. HARDWARE PREPARATI Table 1-2. External Equipment Requirements External Equipment +5 Vdc power supply Freescale Semiconductor, Inc... SUN host computer 2.1 INTRODUCTION This chapter provides unpacking instructions, ha for the EVB. Chapter 6 is a description of the EV RS-232C cable assembly 2.
Freescale Semiconductor, Inc. HARDWARE PREPARATION AND INSTALLATION 2.2.2 Clock Source Select Header (J2) Freescale Semiconductor, Inc... Table 2-1. Jump Use jumper header J2 to select either a crystal or clock oscillator as the MCU clock source. The drawing below shows the factory configuration: bus wire soldered on Header pins 2 and 3. This Jumper configuration selects the crystal clock source; crystal in socket at locatedType Y1.
Freescale Semiconductor, Inc. HARDWARE PREPARATION AND INSTALLATION 2.2.1(continued) Crystal Clock Select Header (J1) Table 2-2. MPFB Jumper Header Descriptions Jumper Header Type J4 321 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. HARDWARE PREPARATION AND INSTALLATION 2.2.4 2.2.9 EVB Reset Switches Freescale Semiconductor, Inc... There are two reset switches on the EVB: • Switch SW1 lets you reset the MPC505 MCU • Switch SW2 lets you reset the EVB. Keep Alive Power 2 Select Header (J4) Jumper header J3 provides power to the MCU modules via the MCU VKAPWR1 pin. You may pins 1 and 2) or connect an external +3.3 Vdc po Vdc power supply on J4 pins 2 and 3 will mainta turned OFF.
Freescale Semiconductor, Inc. HARDWARE PREPARATION AND INSTALLATION 2.2.6 System Clock Selection Headers (J6 and J7) 2.2.7 EVB LED Descriptions Jumper headers J6 and J7 let you define the system clock source. There are Thethree factory LEDsconfiguration on the EVB. Their function (shown below) is for normal operation; a fabricated jumper on J6 and J7 pins 1 and 2. Refer to • LD1 – 3.3 Vdc power: ON = 3.3 Vdc Table 2-4 for configuring the system clock source.
Freescale Semiconductor, Inc. HARDWARE PREPARATION AND INSTALLATION Table 2-7. Data Bus Reset Configuration Word 2.2.10.1 (continued) Chip Select Dip Switch (DS1) Data Bus Bit Configuration Function Effected 24 LEN Freescale Semiconductor, Inc... 25 26 PRUMODE ADDR[12:15] Effect of Mode Select = 1 During Reset L-bus Memory modules are enabled. No effect ADDR[12:15] PB[4:7] Reserved 28 Reserved 29 Reserved 31 2-14 disabled and emulated externally.
Freescale Semiconductor, Inc. HARDWARE PREPARATION AND INSTALLATION 2.3.10.2 Reset Data Dip Switches (DS2 – DS5) Table 2-7. Data Bus Reset Co Data Configuration Dip switches DS2 – DS5 are connected through 4 buffers on the MPC505 MCU data bus (D31 – Bus Function to these D0). At RESET the MCU reads the data bus and changes its configuration according Bit Effected switches ("ON" = 0 LOGIC). Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. HARDWARE PREPARATION AND INSTALLATION 2.3.3 Power Supply – EVB Interconnection 2.2.10.3 DTE/DCE Settings The EVB requires +5 Vdc @ 2 amp power supply for operation. DS6 Connector switch 1P7lets pinyou 1 is define +5 Vdc; which connector pins 2 and 3 are ground (shown in Figure 2-2). Use 16-22 AWG switches wire in2the - 4connector lets you define (supplied I/O connectors P2 with the board). EVB power supply interconnection for connector DS6 P7switch is shown settings.
Freescale Semiconductor, Inc. HARDWARE PREPARATION AND INSTALLATION 2.3 INSTALLATION INSTRUCTIONS 2.3.2 Background Mode Connector (P5) Freescale Semiconductor, Inc... connector P5 host (pinouts shown below) to co The EVB is designed for table top operation. A user supplied Use power supply and computer debug mode (BDM). You may use the serial deve (with an RS-232C port) are required for EVB operation. Connect one end of the SDI to your host comp information about the SDI refer to the M68SDIU 2.3.
Freescale Semiconductor, Inc. HARDWARE PREPARATION AND INSTALLATION 2.3.6 Logic Analyzer Connectors 2.3.4 RS-232C – EVB Interconnection Freescale Semiconductor, Inc... Use connectors POD1 through POD7 to connect a logic analyzer Interconnection to the circuit of being an evaluated. RS-232C compatible de Below are the pin assignments for the logic analyzer connectors.supplied 9-pin cable assembly. One end of the ca or P3 (shown below). The other end of the cable POD1 232CPOD2 compatible device.
Freescale Semiconductor, Inc. HARDWARE PREPARATION AND INSTALLATION 2.3.5 C EVB Expansion Connectors +3.3 Vdc 1 • There are two expansion connectors (P6 and P8) on the EVB. The pin assignments for the +3.3 expansion connectors are in Figures 2-3 and 2-4. Signal descriptions are in Appendix B. Vdc 2 • Freescale Semiconductor, Inc... C B +3.
Freescale Semiconductor, Inc. FUNCTIONAL DESCRIPTION Freescale Semiconductor, Inc... POD5 NC 1 • • 2 NC NC 3 • • 4 DSCK DSDI 5 • • 6 DSDO VF0 7 • • 8 VF1 VF2 9 • • 10 VFLS0 VFLS1 11 • • 12 WP0~ WP1~ 13 • • 14 WP2~ WP3~ 15 • • 16 WP4~ WP5~ 17 • • 18 NC NC 19 • • 20 GND POD7 2.3.
Freescale Semiconductor, Inc. HARDWARE PREPARATION AND INSTALLATION CHAP FUNCTIONAL 3.1 INTRODUCTION Freescale Semiconductor, Inc... This chapter is a functional description of the EV 3.2 EVB DESCRIPTION The EVB may be configured in either of two w mounted on the target system. Figure 3-1 is the E When the BCC is mounted on the PFB, you ma code. To do this connect a terminal or host comp debug monitor program. Logic analyzer connecti the PFB.
Freescale Semiconductor, Inc. FUNCTIONAL DESCRIPTION XXX7FF INTERNAL RAM (2) FFFFFF MCU INTERNAL MODULES FFF000 Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc. FUNCTIONAL DESCRIPTION Freescale Semiconductor, Inc... 3.3.5 3.3.2 Time Processor Unit 3.3.3 Queued Serial Module External Bus Interface The external bus consists of 24 address lines and sizing between 8- The and TPU 16-bithas data The Time Processor Unit (TPU) optimizes performance of time-related activities. a accesses. A r bus cycle interruption.
Freescale Semiconductor, Inc. SUPPORT INFORMATION 3.5 Pin Freescale Semiconductor, Inc... 1 I/O CONNECTORS Table 4-1. SCSI Connector (not populated) There are two 64-pin expansion connectors on th the BCC communicates with the PFB or target sy Mnemonic Signal through P3 and serial communication through P4 GND GROUND interface connectors pin assignments. 2 SDB0 SCSI DATA BUS (bit 0) – Bit 0 of the SCSI bi-directional data bus lines.
Freescale Semiconductor, Inc. FUNCTIONAL DESCRIPTION The coprocessor interface is a transparent, logical extension of the MC68332 MCU device registers and instructions. To the external environment the CPU and coprocessor execution model appear to be on the same chip. CHAP Freescale Semiconductor, Inc... SUPPORT INF A coprocessor interface is an execution model based on sequential instruction execution by the CPU and coprocessor.
Freescale Semiconductor, Inc. SUPPORT INFORMATION Freescale Semiconductor, Inc... Table 4-4. Host Computer Connector P4 Pin Assignments 4-6 Signal Table 4-1. SCSI Connector Pin Mnemonic 1 NC 2 CTXD TRANSMIT – RS-232C serial output signal.32 3 CRXD 4 CRTS RECEIVE DATA – RS-232C serial input signal. 33 – 35 GND GROUND REQUEST TO SEND – An input signal used to request permission to 36 BSY BUSY – Active low I/ transfer data.
Freescale Semiconductor, Inc. SUPPORT INFORMATION Table 4-2. RS-232C I/O Connector P2 Pin Assignments Freescale Semiconductor, Inc... Pin Mnemonic Signal Pin Table 4-3. RS-232C I/O Con Mnemonic 1 ADCD* DATA CARRIER DETECT – An output signal 1 used to indicate BDCD* an acceptable received line (carrier) signal has been detected. DATA CARRIER DE acceptable received 2 ARXD RECEIVE DATA – RS-232C serial input signal. 2 BRXD RECEIVE DATA – R 3 ATXD TRANSMIT – RS-232C serial output signal.
Freescale Semiconductor, Inc. SUPPORT INFORMATION Freescale Semiconductor, Inc... Table 4-8. P8 Expansion Connector Pin Assignments (continued)Table 4-5. Debug Mode Co Pin Mnemonic A-21 NC A-22 ARETRY* A-23 BG* A-24 BR* BUS REQUEST – Active-low input signal that an externalDEVELOPMENT SE 4 indicates that DSCK device requests bus mastership. debug mode.
Freescale Semiconductor, Inc. SUPPORT INFORMATION Freescale Semiconductor, Inc... Table 4-6. P6 Expansion Connector Pin Assignments Pin Mnemonic A-1 FOE* FLASH OUTPUT ENABLE - Active low output 1 signal that VCC lets you read +5 VDC POWER – In the EVB on-board flash memory. logic circuits. The "VC A-2 CS5* A-3 A-13 A10 A20 CHIP SELECT 5 Output signal that selects2peripheral/memory GND devices GROUND The "GND at programmed addresses.
Freescale Semiconductor, Inc. SUPPORT INFORMATION Freescale Semiconductor, Inc... Table 4-14. Logic Analyzer Connector POD6 Pin Assignments Table 4-8. P8 Expansion Connec Pin Mnemonic 1–3 NC 4 CLKOUT 5 RESET* 6 SRESET* 7 – 10 CT0 – CT3 11 CR* 12 BR* 13 14 15, 16 17 18 19 20 4-14 Signal Not Connected Pin Mnemonic C-4 BI* SYSTEM CLOCK OUT – Output signal that is the MPC505 MCU C-5, C-6 IRQ3* IRQ2* internal system clock.
Freescale Semiconductor, Inc. SUPPORT INFORMATION Freescale Semiconductor, Inc... Table 4-9. Logic Analyzer Connector POD1 Pin Assignments Table 4-12. Logic Analyzer Con Pin Mnemonic Signal Pin Mnemonic 1, 2 NC Not Connected 1–3 NC 3 TS* 4 FOE* TRANSFER START – An active-low output 4 –signal 19 that indicates D0 – D15the DATA BUS (bits 0 1 start of a bus cycle. 20 GND GROUND FLASH OUTPUT ENABLE - Active low output signal that lets you read the EVB on-board flash memory.
Freescale Semiconductor, Inc. SUPPORT INFORMATION Freescale Semiconductor, Inc... Table 4-15. Logic Analyzer Con 4-16 Pin Mnemonic 1, 2 NC 3 CLKOUT 4 BURST BURST – Active low 5 TEA* TRANSFER ERROR indicates bus error co 6 AACK* ADDRESS ACKNOW the slave has receive 7 TA* TRANSFER ACKNO indicates the slave h data during a read cy 8 – 11 BE0* – BE3* BYTE ENABLE (0 3 controls one byte lan 12 BDIP* BURST DATA IN PR indicates the data be master.