M68332BCC/D REV 1 October 1993 M68332BCC BUSINESS CARD COMPUTER USER’S MANUAL © MOTOROLA, INC.
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
TABLE OF CONTENTS TABLE OF CONTENTS CHAPTER 1 GENERAL INFORMATION 1.1 1.2 1.3 1.4 1.5 Introduction......................................................................................................................... 1-1 Features............................................................................................................................... 1-1 Specifications......................................................................................................................
TABLE OF CONTENTS CHAPTER 3 OPERATING INSTRUCTIONS (continued) 3.5 3.6 Assembling/Disassembling Procedure ............................................................................. 3-12 Downloading Procedures.................................................................................................. 3-16 3.6.1 Apple Macintosh (with MacTerminal) to BCC...................................................... 3-17 3.6.2 Apple Macintosh (with White Knight) to BCC........................................
TABLE OF CONTENTS LIST OF ILLUSTRATIONS Figure 2-1 2-2 2-3 2-4 2-5 4-1 4-2 Page BCC Jumper Header and Connector Location Diagram .................................................... 2-2 BCC to DB-9 Cable Schematic Diagram ......................................................................... 2-13 BCC to DB-25 Cable Schematic Diagram ....................................................................... 2-14 Expansion Connectors Pin Assignments .........................................................
TABLE OF CONTENTS M68332BCC/D REV 1 iv MOTOROLA
GENERAL INFORMATION CHAPTER 1 GENERAL INFORMATION 1.1 INTRODUCTION This manual provides general information, hardware preparation, installation instructions, functional description, and support information for the M68332BCC Business Card Computer (hereafter referred as BCC). Appendix A contains BCC downloading S-record information. 1.
GENERAL INFORMATION 1.3 SPECIFICATIONS Table 1-1 lists the BCC specifications. Table 1-1. BCC Specifications CHARACTERISTICS Internal Clock External Clock Memory 32k x 16 RAM 64k x 16 EPROM Terminal/Host I/O Port SPECIFICATIONS 32.768 kHz 25 kHz to 50 kHz(1) 85ns (3 clock bus cycle access @ 16.7 MHz) 200ns (5 clock bus cycle access @ 16.
GENERAL INFORMATION 1.4 GENERAL DESCRIPTION Using the BCC, the user can design, debug, and evaluate MC68332 Microcontroller Unit (MCU) based target systems. The BCC simplifies user evaluation of prototype hardware/software products. The BCC requires a user-supplied power supply and an RS-232C compatible terminal for functional operation. The BCC can operate as a standalone single board computer, or as a well-defined core in larger applications.
GENERAL INFORMATION 1.5 EQUIPMENT REQUIRED Table 1-2 lists the external equipment requirements for BCC operation. Table 1-2. External Equipment Requirements EXTERNAL EQUIPMENT A terminal or host computer (RS-232C compatible) with a terminal emulation package (PCKERMIT, PROCOMM, MacTerminal, White Knight, etc.)(1) RS-232C serial communication cable for the terminal or host computer(2). +5 Vdc at 200 mA power supply(2) 1.
HARDWARE PREPARATION AND INSTALLATION CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION 2.1 INTRODUCTION This chapter provides unpacking instructions, hardware preparation, and installation instructions for the BCC prior to target system installation. This description ensures the BCC is properly configured for target system operation. 2.2 UNPACKING INSTRUCTIONS Unpack the BCC from shipping carton. Refer to the packing list and verify that all items are present.
HARDWARE PREPARATION AND INSTALLATION 64-Pin Expansion Connector P1 Background Mode Connector J5 J4 J7 TxD Select J1 J6 Clock Input Select RxD Select RS-232C Serial Communication J2 J3 VSTBY Select RAM Chip Select EPROM Chip Select J8 P2 64-Pin Expansion Connector Figure 2-1.
HARDWARE PREPARATION AND INSTALLATION Table 2-1. Jumper Header Types Jumper Header Type (1) Symbol Description three-pin with jumper Three-pin jumper header with jumper and designated as JX (X = the jumper header number). To change the factory jumper header configuration, move the jumper to the two desired pins. two-pin with jumper Two-pin jumper header with jumper, designated as JX (X = the jumper header number). 1. J7 and J8 are designated as jumper headers but they are in fact connectors.
HARDWARE PREPARATION AND INSTALLATION Table 2-1. Jumper Header Summary (continued) Jumper Header Type J5(1) Description Jumper between pins 1 and 2 (factory default); connects the on-board receive data serial communication drivers to the MC68332 MCU device. 2 1 No jumper; disconnects the on-board receive data serial communication drivers from the MC68332 MCU device. This allows connection of the MCU serial port to off board logic.
HARDWARE PREPARATION AND INSTALLATION 2.3.1 VSTBY Select Header (J1) Use the two-pin jumper header J1 (shown below) to select a voltage standby (VSTBY) power supply source. VSTBY provides battery backup to the RAM contained in the MC68332 MCU device. The BCC is shipped from the factory with VSTBY connected to ground (GND) via J1 cut-trace short. To power VSTBY with an external supply, cut the trace on the bottom of the PCB and connect an external power supply between P1, pin 28 and any BCC ground pin.
HARDWARE PREPARATION AND INSTALLATION 2.3.2 RAM Chip Enable Select Header (J2) Use the three-pin jumper header J2 (shown below) to enable/disable selection of the on-board RAM. The BCC is shipped from the factory with the RAM chip select connected to GND via a cut-trace short on the bottom of the BCC PCB between pins 1 and 2. A fabricated jumper is also installed between pins 1 and 2. The cut-trace short or a fabricated jumper between pins 1 and 2 enables the BCC on-board RAM.
HARDWARE PREPARATION AND INSTALLATION 2.3.3 EPROM Chip Select Header (J3) When BCC power is applied or reset occurs, the MC68332 MCU device resets itself and downloads the program in EPROM (U1 & U2). The EPROM contains the boot program. Use the three-pin jumper header J3 (shown below) to disable the BCC on-board EPROM. The BCC is shipped from the factory with the EPROM connected to the MCU bootstrap chip select pin (CSBOOT ) via a cut-trace short on the bottom of the BCC PCB between pins 1 and 2.
HARDWARE PREPARATION AND INSTALLATION 2.3.4 TxD Select Header (J4) Jumper header J4 allows the user to disconnect the transmit TxD serial data pin of the MC68332 MCU device (U5) from the RS-232C receiver/driver (U6) and use a target system receiver/driver. The BCC is shipped from the factory with the receiver/driver connected to MCU TxD (pin 52) via a cut-trace short on the bottom of the BCC PCB between J4, pins 1 and 2 (shown below). A fabricated jumper is also installed on pins 1 and 2.
HARDWARE PREPARATION AND INSTALLATION 2.3.5 RxD Select Header (J5) Jumper header allows the user to disconnect the receive RxD serial data pin of the MC68332 MCU device (U5) from the RS-232C receiver/driver (U6) and use a target system receiver/driver. The BCC is shipped from the factory with receiver/driver connected to MCU RxD via a cut-trace short on the bottom of the BCC PCB between J5, pins 1 and 2 (shown below). A fabricated jumper is also installed on pins 1 and 2.
HARDWARE PREPARATION AND INSTALLATION 2.3.6 Clock Input Select Header (J6) Use the three-pin jumper header J6 (shown below) to select the BCC on-board clock source or an external clock source. The BCC on-board clock source is a 32 kHz crystal, which is frequency multiplied by the MC68332 to a programmable operating frequency. The BCC is shipped with the on-board crystal selected as the clock source. J6 has a cut-trace short on the bottom of the BCC PCB between pins 2 and 3.
HARDWARE PREPARATION AND INSTALLATION An optional high frequency oscillator (0 to 16.77 MHz) may be used if MODCK (connector P2, pin 28) is pulled to a logic low level. To use the target-system, external-source CMOS clock; follow these steps: a. Turn off power to the BCC. b. Cut the printed circuit trace on the bottom of the BCC between pins 2 and 3. c. Move the fabricated jumper between pins 2 and 3 to pins 1 and 2. d. Supply an external oscillator to connector P2, pin 59 (EXTAL). e.
HARDWARE PREPARATION AND INSTALLATION 2.4 INSTALLATION INSTRUCTIONS A user supplied power supply and RS-232C compatible terminal are required for BCC operation. An RS-232C compatible host computer, with terminal emulation package, may be connected to the BCC for S-record downloading. 2.4.1 Power Supply - BCC Interconnection The BCC requires +5 Vdc @ 200 mA (max.) for operation. Use 18 to 20 AWG wire to connect a user supplied power supply to the BCC.
HARDWARE PREPARATION AND INSTALLATION 2.4.2 Terminal - BCC Interconnection Interconnection of an RS-232C compatible terminal to the BCC is accomplished via a user supplied 9- or 25-conductor cable assembly as shown in Figures 2-2 and 2-3. If the user’s terminal/host computer has a DB-9 connector refer to Figure 2-2. If the user’s terminal/host computer has a DB-25 connector refer to Figure 2-3. One end of the cable assembly connects to the BCC connector J9 (shown below).
HARDWARE PREPARATION AND INSTALLATION 1 BCC J8 2 3 4 XMT 232 NC GND RCV 232 NC +10V NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TERMINAL OR HOST COMPUTER Figure 2-3.
HARDWARE PREPARATION AND INSTALLATION 2.4.3 Target System - BCC Interconnection For target system to BCC interconnection the BCC mounts on the target system as shown below. This configuration is used to evaluate the user’s hardware design. The 64-pin expansion connectors provide access to most of the MC68332 MCU device pins. Figure 2-4 illustrates the expansion header pin assignments for the BCC. Physical dimension requirements for installing the BCC on a target system are illustrated in Figure 2-5.
HARDWARE PREPARATION AND INSTALLATION P1 GND 1 P2 2 GN D G ND 1 2 GND +5V 3 4 +5V +5V 3 4 +5V DT RO UT 5 6 A0 D1 5 6 D0 A2 D3 7 8 D2 9 10 D4 A1 7 8 A3 9 10 A4 D5 A5 11 12 A6 D7 11 12 D6 A7 13 14 A8 D 9 13 14 D8 A9 15 16 A10 D 11 15 16 D10 A11 17 18 A12 D13 17 18 D12 A13 19 20 A14 D15 19 20 D14 A15 21 22 A16 RXD DI 21 22 TXD DI A17 23 24 A18 M OD B DI 23 24 XMT 232 NC 25 26 NC CSBOOT 25 26 RC V 232 13-24V DI 2
HARDWARE PREPARATION AND INSTALLATION .100 in. 2.54 mm P1 P2 3.1 in. 7.87 cm 2 in. 5.08 cm VIEW: TOP Figure 2-5.
HARDWARE PREPARATION AND INSTALLATION M68332BCC/D REV 1 2-18 MOTOROLA
OPERATING INSTRUCTIONS CHAPTER 3 OPERATING INSTRUCTIONS 3.1 INTRODUCTION The EPROMs on the BCC contain the M68CPU32BUG debug monitor program (hereafter referred to as CPU32Bug). CPU32Bug is a software tool for evaluating and debugging systems built around the MC68332 MCU. CPU32Bug allows loading, debugging, and executing of user programs. Various CPU32Bug routines that handle I/O, data conversion, timer, and string functions are available to user programs through system calls.
OPERATING INSTRUCTIONS 3.2.1 Chip Select Usage The MC68332 MCU has chip select signals that enable peripheral devices. The BCC requires some of these chip selects for BCC operation making them unavailable to the user. Do not remove the chip selects used by the BCC, or CPU32Bug will not operate. In addition to the chip selects employed on the BCC, other chip selects are used elsewhere in the M68332EVK (refer to Tables 3-1 through 3-3).
OPERATING INSTRUCTIONS Table 3-2. BCC Rev. B Chip Selection Summary Signal Board/Chip CSBOOT CS0 CS1 CS2 CS3 CS4 CS5 BCC U2 BCC U1 BCC U3 BCC U3/U1 PFB PFB U5 CS6 CS7 CS8 CS9 CS10 PFB U2 PFB U4 PFB U1/U3 PFB U1 PFB U3 Description CPU32Bug EPROM write enable for MSB=UPPER=EVEN write enable for LSB=LOWER=ODD read enable for MSB/LSB=BOTH ABORT push-button autovector chip enable for MC68881/882. cut/-jump U5-J3 from CS2 to CS5 required.
OPERATING INSTRUCTIONS 3.2.2 Other MCU Resources Used by CPU32Bug Avoid writing the value zero to bit 7 of the port F pin assignment register (PFPAR); such a value disables the ABORT switch. The software watchdog timer is disabled via a write-once register (SYPCR) during power-up or reset, so the software watchdog timer cannot be used or re-enabled by the user unless the user modifies the SYPCR_OR and SYPCR_AND parameters.
OPERATING INSTRUCTIONS 3.3 OPERATING PROCEDURE A Power On Reset (POR) occurs when power is applied to the BCC. This POR condition resets the MCU and user I/O port circuitry. After a POR occurs, processing control passes to the monitor program. All MC68332 registers are set to their reset state during monitor power-up. The input serial format for the BCC terminal I/O port must be configured for 8 data bits, 1 stop bit, no parity, and 9600 baud.
OPERATING INSTRUCTIONS 3.4 MONITOR DESCRIPTION CPU32Bug performs various operations in response to user commands entered at the keyboard. When the debugger prompt CPU32Bug> appears on the terminal screen, the debugger is ready to accept commands. As the command line is entered it is stored in an internal buffer. Execution begins only after the carriage return is entered.
OPERATING INSTRUCTIONS 3.4.1 Memory and Register Display and Modification Commands Various commands are available to the user for displaying and modifying memory. For more information, refer to Chapter 3 of the M68CPU32BUG Debug Monitor User’s Manual, M68CPU32BUG/AD1. The memory display and modification commands are: 3.4.2 • BF (block of memory fill) fills the specified range of memory with a data pattern.
OPERATING INSTRUCTIONS 3.4.3 System Calls The CPU32Bug TRAP #15 handler allows system calls from user programs. A system call accesses selected functional routines contained in CPU32Bug, including input and output routines. TRAP #15 also transfers control to CPU32Bug at the end of a user program. For more information on system calls, refer to Chapter 5 of the M68CPU32BUG Debug Monitor User’s Manual, M68CPU32BUG/AD1. System calls include: • .
OPERATING INSTRUCTIONS • .WRITDLN (output line with data in pointer/count format) uses the monitor I/O routine which outputs a user string containing embedded variable fields. The user passes the starting address of the string and the data stack address containing the data which is inserted into the string. The output goes to the default output port. • .SNDBRK (send break) sends a break to the default output port. • .
OPERATING INSTRUCTIONS 3.4.4 Diagnostic Monitor The diagnostic monitor is a series of self-tests for the MC68332 MCU device. The diagnostic monitor is programmed into the BCC EPROM. For more information on the diagnostic monitor, refer to Chapter 6 of the M68CPU32BUG Debug Monitor User’s Manual, M68CPU32BUG/AD1. The diagnostic monitor commands are: • HE (help) command displays a menu of the top level directory. • ST (self test) command executes self-test diagnostics.
OPERATING INSTRUCTIONS Memory tests are a series of diagnostics that verify random access memory (read/write) that may reside on the BCC.
OPERATING INSTRUCTIONS 3.5 ASSEMBLING/DISASSEMBLING PROCEDURE The assembler/disassembler is an interactive, one-line assembler/editor in which the source program is not saved. Each source line is converted into machine language code and is stored in memory on a line-by-line basis at the time of entry. In order to display an instruction, the machine code is disassembled and the instruction mnemonic and operands are displayed. All valid opcodes are converted to assembly language mnemonic.
OPERATING INSTRUCTIONS Enter the periodic interrupt timer (PIT) time-out program starting at address $5000: EXAMPLE PROGRAM PROGRAM DESCRIPTION Memory modify at location $5000 with disassembly option. Set-up level six vector table. Initialize PIT. Execute LPSTOP Instruction. Loop Beginning of message. End of message. Check for SCI not busy. Branch until free. Send message byte. Check for end of message. Branch until done. Return from print routine.
OPERATING INSTRUCTIONS After entering the PIT time-out program display the instructions at location $5000 EXAMPLE PROGRAM PROGRAM DESCRIPTION Display memory at location $5000 with disassembly option. CPU32Bug>MD 5000;DI 5000 5008 21FC0000 23FC061E FA22 5012 F80001C0 5018 6000FFF8 501C 307C5100 5020 327C510E 5024 08390000 502C 67F6 CPU32Bug> 502E 13D800FF 5034 B2C8 5036 6600FFEC 503A 4E73 503C 0000FFFF 5040 0000FFFF 5044 0000FFFF 5048 0000FFFF 501C0078 012000FF 2500 00FFFC0C MOVE.
OPERATING INSTRUCTIONS The following routines are performed on the preceding program loop: ROUTINE DESCRIPTION TERMINAL CPU32Bug>MD 5000;DI 00005000 21FC0000 501C0078 00005008 23FC061E 012000FF FA22 00005012 F80001C0 2500 00005018 6000FFF8 0000501C 307C5100 00005020 327C510E 00005024 08390000 00FFFC0C 0000502C 67F6 CPU32Bug>MM 500C 0000500C 0120? 00FF. CPU32Bug>g 5000 Effective address: 00005000 PIT TIME-OUT PIT TIME-OUT PIT TIME-OUT : : Display memory at address 5000 MOVE.L #$501C,($78).
OPERATING INSTRUCTIONS 3.6 DOWNLOADING PROCEDURES Downloading transfers information from a host computer to the BCC, via the load (LO) command. The procedure described below lets the user download with an IBM personal computer (PC) or Apple Macintosh host computer. The LO command moves data in S-record format (see Appendix A) from an external host computer to the EVK user pseudo ROM. Subsections 3.6.1 through 3.6.
OPERATING INSTRUCTIONS 3.6.1 Apple Macintosh (with MacTerminal) to BCC The MacTerminal downloading program serves as a terminal emulator for the Apple Macintosh computer. To download a Motorola S-record file from the Apple Macintosh computer to the BCC: a. Select the following menu Terminal Settings: Terminal: VT100 Mode: ANSI Cursor Shape: Underline Line Width: 80 Columns Select: On Line Auto Repeat Click on: OK b.
OPERATING INSTRUCTIONS d. Apply power to the BCC. e. Press Apple Macintosh computer keyboard carriage return () key to display applicable BCC monitor prompt. f Apple Macintosh computer displays the CPU32Bug> prompt. g. Enter BCC monitor download command as follows: CPU32Bug>LO h. Operate pull-down File menu, and select (choose): Send File ... i. Use dialog box and select applicable S-record object file. Click on: Send Motorola S-record file is now transferred to the BCC.
OPERATING INSTRUCTIONS 3.6.2 Apple Macintosh (with White Knight) to BCC The White Knight downloading program serves as a terminal emulator for the Apple Macintosh computer. To download a Motorola S-record file from the Apple Macintosh computer to the BCC: a. Execute White Knight program. b. Set up computer program to match BCC baud rate (typically) as follows: 9600 baud, no parity, 8-bits, 1-stop bit, full duplex c. Apply power to BCC. d.
OPERATING INSTRUCTIONS 3.6.3 IBM-PC (with KERMIT) to BCC Before performing any IBM-PC operation, ensure that both IBM-PC and BCC baud rates are 9600, and that the IBM-PC asynchronous port is configured for terminal mode of operation. If the asynchronous port is hard wired for host mode of operation and cannot be re-configured for a terminal mode of operation, the use a null modem (cross-coupled transmit (TxD), and receive (RxD), and associated handshake lines) is required.
OPERATING INSTRUCTIONS The underline cursor flashes and the beeper sounds when the S-record has finished downloading. Press the carriage return twice to return to the CPU32Bug prompt: CPU32Bug> CPU32Bug>(CTRL) ]C KERMIT-MS>EXIT M68332BCC/D REV 1 Exit Kermit program.
OPERATING INSTRUCTIONS 3.6.4 IBM-PC (with PROCOMM) to BCC To perform the IBM-PC to BCC downloading procedure with PROCOMM: a. Execute the PROCOMM.EXE program. b. Setup PROCOMM to match BCC baud rate and protocol (type (Alt)P, then the number 11) as follows: 9600 baud, no parity, 8 bits, 1 stop bit, full duplex c.
FUNCTIONAL DESCRIPTION CHAPTER 4 FUNCTIONAL DESCRIPTION 4.1 INTRODUCTION This chapter provides a functional description of the BCC. This description is supported by a block diagram (Figure 4-1) and a memory map diagram (Figure 4-2). Refer to Chapter 5 for the BCC schematic diagram. 4.
FUNCTIONAL DESCRIPTION TIMER CHANNELS TERMINAL/ HOST COMPUTER P4 RS-232C INTERFACE U5 P1 ADDRESS AND CONTROL LINES MCU U1 BACKGROUND MODE P3 64K x 8 EPROM U1 64K x 8 EPROM U2 32K x 8 RAM U3 32K x 8 RAM U4 INTERRUPT SIGNALS P2 DATA AND CONTROL LINES Figure 4-1. BCC Block Diagram 4.2.
FUNCTIONAL DESCRIPTION 4.2.1.1 32-Bit Central Processor Unit The CPU32 is the central processor for the MC68332 MCU device. The CPU32 is source and object code compatible with the MC68000 and MC68010. All user programs can be executed unchanged.
FUNCTIONAL DESCRIPTION The serial communications interface (SCI) port provides a standard non-return to zero (NRZ) mark/space format. Advanced error detection circuitry catches noise glitches to 1/16 of a bit time in duration. Word length is software selectable between 8- or 9-bits, and the SCI modulus-type, baud rate generator provides baud rates from 64 to 524k baud, based on a 16.77 MHz system clock.
FUNCTIONAL DESCRIPTION 4.2.1.8 Test Module The test module consolidates the microcontroller test logic into a single block to facilitate production testing, user self-test, and system diagnostics. Scan paths throughout the MC68332 provide signature analysis checks on internal logic. User self-test is initiated by asserting the test pin to enter test mode. This test provides a pass/fail response to various externally supplied test vectors. 4.2.
FUNCTIONAL DESCRIPTION XXX7FF INTERNAL RAM (2) (1 ) XXX000 FFFFFF MCU INTERNAL MODULES FFF000 OPTIONAL FPCP (3) PFB: U5 FFE800 800000 ALTERNATE MCU INTERNAL MODULES LOCATION (4) 7FF000 OPTIONAL RAM/EPROM PFB: U2 & U4 CPU32BUG EPROM BCC: U1 & U2 110000 /120000 (5) 100000 0E0000 OPTIONAL RAM PFB: U1 & U3 TARGET RAM BCC: U3 & U4 SYSTEM RAM BCC: U3 & U4 CPU32BUG INTERNAL STACK CPU32BUG INTERNAL VARIABLES CPU32BUG VECTOR TABLE TARGET VECTOR TABLE 020000 010000 003000 000000 1.
SUPPORT INFORMATION CHAPTER 5 SUPPORT INFORMATION 5.1 INTRODUCTION This chapter provides the connector signal descriptions. 5.2 CONNECTOR SIGNAL DESCRIPTIONS Connectors P1 and P2 connect the BCC to a target system. Connector P3 is for background mode. Connector P4 is for serial communication between the BCC and a host computer. Pin assignments for P1, P2, P3 and P4 are defined in Tables 5-1 through 5-4. Connector signals are identified by pin number, signal mnemonic, and signal name and description.
SUPPORT INFORMATION Table 5-1. P1 Expansion Connector Pin Assignments (continued) Signal Mnemonic Pin Number Signal Name And Description 28 VSTBY VOLTAGE STANDBY – Input standby voltage source for MCU on-chip RAM. 29 +13—24V DI 30 T2CLK 31 — 46 TP15 — TP0 47 MOSI MASTER-OUT SLAVE-IN – Serial output from the OSPI in master mode, and serial input to the QSPI in slave mode. 48 MISO MASTER-IN SLAVE-OUT – Serial input to the QSPI in master mode, and serial output from the QSPI in slave mode.
SUPPORT INFORMATION Table 5-1. P1 Expansion Connector Pin Assignments (continued) Signal Mnemonic Pin Number 55 Signal Name And Description BKPT / BREAKPOINT – An active-low input signal that places the CPU32 in background debug mode. DSCLK DEVELOPMENT SYSTEM CLOCK – Serial input clock for background debug mode. 56 RXD 57 RESET 58 FREEZE / FREEZE – Output signal that indicates that the CPU32 has entered background debug mode.
SUPPORT INFORMATION Table 5-2. P2 Expansion Connector Pin Assignments Signal Mnemonic Pin Number Signal Name And Description 1, 2 GND GROUND 3, 4 +5V +5 VOLT INPUT POWER 5 — 20 D0 — D15 21 RXD DI RECEIVE DATA DEVELOPMENT INTER-FACE – BCCDI receive data. 22 TXD DI TRANSMIT DATA DEVELOPMENT INTER-FACE – BCCDI transmit data. 23 MODB DI MODE B DEVELOPMENT INTERFACE – BCCDI mode B. 24 XMT 232 TRANSMIT DATA – Serial data output signal.
SUPPORT INFORMATION Table 5-2. P2 Expansion Connector Pin Assignments (continued) Signal Mnemonic Pin Number 35 — 37 Signal Name And Description FC2/CS5 , FC1/CS4 , FC0/CS3 FUNCTION CODES – Three-state output signals that identify the processor state and address space of the current bus cycle. CHIP SELECTS 3—5 – Output signals that select peripheral/memory devices at programmed addresses.
SUPPORT INFORMATION Table 5-2. P2 Expansion Connector Pin Assignments (continued) Signal Mnemonic Pin Number Signal Name And Description 49, 50 DSACK0 , DSACK1 DATA AND SIZE ACKNOWLEDGE – Active-low input signals that allow asynchronous data transfers and dynamic bus sizing between the MC68332 and external devices. 51 AVEC AUTOVECTOR – Active-low input signal that requests an automatic vector during an interrupt acknowledge cycle.
SUPPORT INFORMATION Table 5-3. J8 Background Mode Connector Pin Assignments Signal Mnemonic Pin Number Signal Name And Description 1 DS 2 BERR 3 GND 4 BKPT / BREAKPOINT – An active-low input signal that places the CPU32 in background debug mode. DSCLK DEVELOPMENT SYSTEM CLOCK – Serial input clock for background debug mode. DATA STROBE – Active-low output signal, that during a read cycle, indicates that an external device should place valid data on the data bus.
SUPPORT INFORMATION Table 5-4. J9 RS-232C Serial Communication Connector Pin Assignments Signal Mnemonic Pin Number Signal Name And Description 1 XMIT TRANSMIT DATA – RS-232C serial output data. 2 GND GROUND 3 RCV RECEIVE DATA – RS-232C serial input data. 4 +10V +10 VOLTS DC – Output voltage that may be used to drive RS-232C handshake lines.
APPENDIX A APPENDIX A S-RECORD INFORMATION The S-record format for output modules was devised for the purpose of encoding programs or data files in a printable format for transportation between computer systems. The transportation process can thus be visually monitored and the S-records can be more easily edited. S-RECORD CONTENT When viewed by the user, S-records are essentially character strings made of several fields which identify the record type, record length, memory address, code/data and checksum.
APPENDIX A Each record may be terminated with a CR/LF/NULL. Additionally, an S-record may have an initial field to accommodate other data such as line numbers generated by some time-sharing systems. An S-record file is a normal ASCII text file in the operating system of origin. Accuracy of transmission is ensured by the record length (byte count) and checksum fields.
APPENDIX A S-RECORDS CREATION S-record format files may be produced by dump utilities, debuggers, linkage editors, cross assemblers or cross linkers. Several pro- grams are available for downloading a file in S-record format from a host system to a microprocessor-based system.
APPENDIX A The next 16 character pairs of the first S1 record are the ASCII bytes of the actual program code/data. In this assembly language example, the hexadecimal opcodes of the program are written in sequence in the code/data fields of the S1 records: OPCODE INSTRUCTION 285F 245F 2212 226A0004 24290008 237C MOVE.L MOVE.L MOVE.L MOVE.L MOVE.L MOVE.
