user manual

Chapter 4 Functional Description
MVME3100 Installation and Use (V3100A/IH1)
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Processor
The MVME3100 supports the MPC8540 processor. The processor core frequency runs at 833
or 667 MHz. The MPC8540 has integrated 256KB L2 cache.
System Memory
The MPC8540 provides one standard DDR SDRAM SODIMM socket. This socket supports
standard single or dual bank, unbuffered, SSTL-2 DDR-I, JESD8-9B compliant, SODIMM
module with ECC. The MPC8540 DDR memory interface supports up to 166 MHz (333 MHz
data rate) operation.
Local Bus Interface
The MVME3100 uses the MPC8540 local bus controller (LBC) for access to on-board Flash and
I/O registers. The LBC has programmable timing modes to support devices of different access
times, as well as device widths of 8, 16, and 32 bits.
The MVME3100 uses the LBC in GPCM (general purpose chip select machine) mode to
interface to two physical banks of on-board Flash, an on-board quad UART (QUART), on-board
32-bit timers, and the System Control/Status registers. Refer to the MVME3100 Single-Board
Computer Programmer’s Reference Guide listed in Appendix B, Related Documentation, for the
LBC bank and chip select assignments.
Figure 4-2. MVME721 RTM Block Diagram
4390 0106
PIM 10
PIM
U
S
B
s ATA
P2 P0
GigE
RJ45
GigE 2
10/100
Serial Port 4
Serial Port 3
Serial Port 2
Serial Port 1
VPD
8K8
I
2
C Bus
Rear Panel
Future Option
10/100
RJ45
Serial
RJ45
Serial
RJ45
Serial
RJ45
Serial
RJ45
PMC 1 Jn4 10
s ATA 3
USB 2
Future Option