MCF5282UM/D Rev.
HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 Information in this document is provided solely to enable system and software implementers to use Motorola products.
Overview 1 ColdFire Core 2 Enhanced Multiply-Accumulate Unit (EMAC) 3 Cache 4 Static RAM (SRAM) 5 ColdFire Flash Module (CFM) 6 Power Management 7 System Control Module (SCM) 8 Clock Module 9 Interrupt Controller Modules 10 Edge Port Module (EPORT) 11 Chip Select Module 12 External Interface Module (EIM) 13 Signal Descriptions 14 Synchronous DRAM Controller Module 15 DMA Controller Module 16 Fast Ethernet Controller (FEC) 17 Watchdog Timer Module 18 Programmable Interrupt
1 Overview 2 ColdFire Core 3 Enhanced Multiply-Accumulate Unit (EMAC) 4 Cache 5 Static RAM (SRAM) 6 ColdFire Flash Module (CFM) 7 Power Management 8 System Control Module (SCM) 9 Clock Module 10 Interrupt Controller Modules 11 Edge Port Module (EPORT) 12 Chip Select Module 13 External Interface Module (EIM) 14 Signal Descriptions 15 Synchronous DRAM Controller Module 16 DMA Controller Module 17 Fast Ethernet Controller (FEC) 18 Watchdog Timer Module 19 Programmable Inter
CONTENTS Paragraph Number Title Page Number Chapter 1 Overview 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.1.7 1.1.8 1.1.9 1.1.10 1.1.11 1.1.12 1.1.13 1.1.14 1.1.15 1.1.16 1.1.17 1.2 1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 MCF5282 Key Features...................................................................................... 1-1 Version 2 ColdFire Core................................................................................. 1-8 System Control Module .......................................................
CONTENTS Paragraph Number 2.3 2.4 2.5 2.6 2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.7.6 2.7.7 2.7.8 2.7.9 2.7.10 2.7.11 2.7.12 2.7.13 2.7.14 2.8 2.8.1 2.8.2 2.9 2.10 2.11 2.12 2.13 2.14 Page Number Programming Model ........................................................................................... 2-8 Additions to the Instruction Set Architecture ..................................................... 2-9 Exception Processing Overview .......................................................................
CONTENTS Paragraph Number Title Page Number Chapter 4 Cache 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.4 4.4.1 4.4.2 Cache Features .................................................................................................... Cache Physical Organization .............................................................................. Cache Operation ................................................................................................. Interaction with Other Modules.......................
CONTENTS Paragraph Number 6.5 6.5.1 6.5.2 6.6 6.7 Page Number Flash Security Operation .................................................................................. 6-23 Back Door Access......................................................................................... 6-24 Erase Verify Check....................................................................................... 6-24 Reset.............................................................................................................
CONTENTS Paragraph Number Title Page Number Chapter 9 Clock Module 9.1 9.2 9.2.1 9.2.2 9.2.3 9.3 9.4 9.5 9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 9.6 9.6.1 9.6.2 9.7 9.7.1 9.7.2 9.7.3 9.7.4 Features ............................................................................................................... 9-1 Modes of Operation ............................................................................................ 9-1 Normal PLL Mode.........................................................................
CONTENTS Paragraph Number Title Page Number Chapter 11 Edge Port Module (EPORT) 11.1 11.2 11.3 11.4 11.4.1 11.4.2 Introduction....................................................................................................... Low-Power Mode Operation ............................................................................ Interrupt/General-Purpose I/O Pin Descriptions............................................... Memory Map and Registers..........................................................
CONTENTS Paragraph Number 14.2 14.2.1 14.2.2 14.2.3 14.2.4 14.2.5 14.2.6 14.2.7 14.2.8 14.2.9 14.2.10 14.2.11 14.2.12 14.2.13 14.2.14 14.2.15 14.2.16 Title Page Number MCF5282 External Signals............................................................................. External Interface Module (EIM) Signals .................................................. SDRAM Controller Signals ........................................................................ Clock and Reset Signals ..........................
CONTENTS Paragraph Number 16.2 16.3 16.4 16.4.1 16.4.2 16.4.3 16.4.4 16.4.5 16.5 16.5.1 16.5.2 16.5.3 16.5.4 16.5.5 Page Number DMA Request Control (DMAREQC) .............................................................. 16-3 DMA Transfer Overview.................................................................................. 16-4 DMA Controller Module Programming Model................................................ 16-5 Source Address Registers (SAR0–SAR3) ..............................................
CONTENTS Paragraph Number 17.5.1 17.5.2 17.5.3 17.5.4 17.6 17.6.1 17.6.2 17.6.3 Title Page Number Top Level Module Memory Map ............................................................... Detailed Memory Map (Control/Status Registers) ..................................... MIB Block Counters Memory Map............................................................ Registers...................................................................................................... Buffer Descriptors..............
CONTENTS Paragraph Number 20.3 20.4 20.4.1 20.4.2 20.4.3 20.5 20.5.1 20.5.2 20.5.3 20.5.4 20.5.5 20.5.6 20.5.7 20.5.8 20.5.9 20.5.10 20.5.11 20.5.12 20.5.13 20.5.14 20.5.15 20.5.16 20.5.17 20.5.18 20.5.19 20.6 20.6.1 20.6.2 20.6.3 20.6.4 20.6.5 20.6.6 20.6.7 20.7 20.8 20.8.1 20.8.2 20.8.3 20.8.4 xiv Page Number Low-Power Mode Operation ............................................................................ 20-3 Signal Description........................................................................
CONTENTS Paragraph Number Title Page Number Chapter 21 DMA Timers (DTIM0–DTIM3) 21.1 21.1.1 21.2 21.2.1 21.2.2 21.2.3 21.2.4 21.2.5 21.2.6 21.2.7 21.2.8 21.2.9 21.2.10 21.2.11 21.3 21.3.1 21.3.2 Overview........................................................................................................... 21-1 Key Features ................................................................................................. 21-2 DMA Timer Programming Model ................................................
CONTENTS Paragraph Number 22.5.6 22.5.7 22.5.8 Page Number QSPI Data Register (QDR)......................................................................... 22-14 Command RAM Registers (QCR0–QCR15).............................................. 22-15 Programming Example ............................................................................... 22-16 Title Chapter 23 UART Modules 23.1 23.2 23.3 23.3.1 23.3.2 23.3.3 23.3.4 23.3.5 23.3.6 23.3.7 23.3.8 23.3.9 23.3.10 23.3.11 23.3.12 23.3.13 23.4 23.5 23.
CONTENTS Paragraph Number 24.4.4 24.5 24.5.1 24.5.2 24.5.3 24.5.4 24.5.5 24.6 24.6.1 24.6.2 24.6.3 24.6.4 24.6.5 24.6.6 24.6.7 Title Page Number Clock Stretching ........................................................................................... 24-5 Programming Model ......................................................................................... 24-6 I2C Address Register (I2ADR) .....................................................................
CONTENTS Paragraph Number 25.5.3 25.5.4 25.5.5 25.5.6 25.5.7 25.5.8 25.5.9 25.5.10 25.5.11 25.5.12 Page Number FlexCAN Control Register 1 (CANCTRL1) .............................................. 25-23 Prescaler Divide Register (PRESDIV) ....................................................... 25-24 FlexCAN Control Register 2 (CANCTRL2) .............................................. 25-25 Free Running Timer (TIMER).................................................................... 25-26 Rx Mask Registers .
CONTENTS Paragraph Number 27.4.7 27.4.8 27.5 27.6 27.6.1 27.6.2 27.6.3 27.6.4 27.6.5 27.6.6 27.6.7 27.6.8 27.7 27.7.1 27.7.2 27.7.3 27.8 27.8.1 27.8.2 27.8.3 27.8.4 27.8.5 27.8.6 27.8.7 27.8.8 27.8.9 27.8.10 27.8.11 27.9 27.9.1 27.9.2 27.9.3 27.9.4 27.9.5 27.9.6 27.9.7 27.10 27.10.1 27.10.2 MOTOROLA Title Page Number Dedicated Analog Supply Signals ................................................................ 27-7 Dedicated Digital I/O Port Supply Signal...............................................
CONTENTS Paragraph Number Title Page Number Chapter 28 Reset Controller Module 28.1 28.2 28.3 28.3.1 28.3.2 28.4 28.4.1 28.4.2 28.5 28.5.1 28.5.2 28.5.3 Features ............................................................................................................. 28-1 Block Diagram .................................................................................................. 28-2 Signals..........................................................................................................
CONTENTS Paragraph Number Title Page Number Chapter 30 Chip Configuration Module (CCM) 30.1 30.2 30.2.1 30.2.2 30.3 30.4 30.4.1 30.4.2 30.4.3 30.5 30.5.1 30.5.2 30.5.3 30.6 30.6.1 30.6.2 30.6.3 30.6.4 30.6.5 30.6.6 30.7 30.8 Features ............................................................................................................. 30-1 Modes of Operation .......................................................................................... 30-1 Master Mode ................................
CONTENTS Paragraph Number 31.6.2 Page Number Nonscan Chain Operation........................................................................... 31-12 Title Chapter 32 Mechanical Data 32.1 32.2 Pinout ................................................................................................................ 32-2 Ordering Information ........................................................................................ 32-7 Chapter 33 Electrical Characteristics 33.1 33.2 33.3 33.4 33.5 33.6 33.
ILLUSTRATIONS Figure Number 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 4-1 4-2 4-3 5-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 Title Page Number MCF5282 Block Diagram ............................................................................................ 1-7 ColdFire Processor Core Pipelines ............................................................................... 2-1 User Programming Model ......................................................
ILLUSTRATIONS Figure Number 7-1 7-2 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 9-1 9-2 9-3 9-4 9-5 9-6 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 11-1 11-2 11-3 11-4 11-5 11-6 11-7 12-1 12-2 12-3 12-4 13-1 13-2 13-3 xxiv Title Page Number Low-Power Interrupt Control Register (LPICR) ......................................................... 7-3 Low-Power Control Register (LPCR) ......................................................................... 7-4 IPS Base Address Register (IPSBAR)..........
ILLUSTRATIONS Figure Number 13-4 13-5 13-6 13-7 13-8 13-9 13-10 13-11 13-12 13-13 13-14 13-15 13-16 13-17 13-18 13-19 13-20 14-1 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 15-13 15-14 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 17-1 17-2 Title Page Number Data Transfer State Transition Diagram ..................................................................... 13-5 Read Cycle Flowchart.................................................................................................
ILLUSTRATIONS Figure Number 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 17-11 17-12 17-13 17-14 17-15 17-16 17-17 17-18 17-19 17-20 17-21 17-22 17-23 17-24 17-25 17-26 17-27 17-28 18-1 18-2 18-3 18-4 18-5 19-1 19-2 19-3 19-4 19-5 19-6 20-1 20-2 20-3 20-4 20-5 xxvi Title Page Number Ethernet Address Recognitionq—Microcode Decisions .......................................... 17-13 Ethernet Interrupt Event Register (EIR) ...................................................................
ILLUSTRATIONS Figure Number 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 20-16 20-17 20-18 20-19 20-20 20-21 20-22 21-1 21-2 21-3 21-4 21-5 21-6 21-7 22-1 22-2 22-3 22-4 22-5 22-6 22-7 22-8 22-9 22-10 22-11 23-1 23-2 23-3 23-4 23-5 23-6 23-7 23-8 Title Page Number GPT Counter Register (GPTCNT) ............................................................................. 20-7 GPT System Control Register 1 (GPTSCR1).............................................................
ILLUSTRATIONS Figure Number 23-9 23-10 23-11 23-12 23-13 23-14 23-15 23-16 23-17 23-18 23-19 23-20 23-21 23-22 23-23 23-24 23-25 23-26 24-1 24-2 24-3 24-4 24-5 24-6 24-7 24-8 24-9 24-10 25-1 25-2 25-3 25-4 25-5 25-6 25-7 25-8 25-9 25-10 25-11 25-12 25-13 25-14 xxviii Title Page Number UART Input Port Change Register (UIPCRn) ......................................................... 23-12 UART Auxiliary Control Register (UACRn) ...........................................................
ILLUSTRATIONS Figure Number 25-15 25-16 25-17 26-1 26-2 26-3 26-4 26-5 26-6 26-7 26-8 26-9 26-10 26-11 26-12 26-13 26-14 26-15 26-16 26-17 26-18 26-19 26-20 26-21 26-22 26-23 26-24 26-25 26-26 26-27 26-28 26-29 26-30 27-1 27-2 27-3 27-4 27-5 27-6 27-7 27-8 27-9 27-10 Title Page Number Interrupt Flag Register (IFLAG)............................................................................... 25-31 FlexCAN Receive Error Counter (RXECTR) ..........................................................
ILLUSTRATIONS Figure Number 27-11 27-12 27-13 27-14 27-15 27-16 27-17 27-18 27-19 27-20 27-21 27-22 27-23 27-24 27-25 27-26 27-27 27-28 27-29 27-30 27-31 27-32 27-33 27-34 27-35 27-36 27-37 27-38 27-39 27-40 27-41 27-42 27-43 27-44 27-45 27-46 27-47 27-48 27-49 27-50 27-51 27-52 xxx Title Page Number QADC Status Register 0 (QASR0)........................................................................... 27-22 Queue Status Transition.......................................................................
ILLUSTRATIONS Figure Number 27-53 28-1 28-2 28-3 28-4 29-1 29-2 29-3 29-4 29-5 29-6 29-7 29-8 29-9 29-10 29-11 29-12 29-13 29-14 29-15 29-16 29-17 29-18 29-19 29-20 29-21 29-22 29-23 29-24 29-25 29-26 29-27 29-28 29-29 29-30 29-31 29-32 29-33 29-34 29-35 29-36 29-37 29-38 Title Page Number Electrical Model of an A/D Input Signal .................................................................. 27-73 Reset Controller Block Diagram...........................................................................
ILLUSTRATIONS Figure Number 29-39 29-40 29-41 30-1 30-2 30-3 30-4 31-1 31-2 31-3 32-1 32-2 33-1 33-2 33-3 33-4 33-5 33-6 33-7 33-8 33-9 33-10 33-11 33-12 33-13 33-14 33-15 33-16 33-17 33-18 33-19 33-20 33-21 xxxii Title Page Number BDM Command Format............................................................................ 29-36 Command Sequence .................................................................................. 29-36 Recommended BDM Connector............................................
TABLES Table Number 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 3-1 3-2 3-3 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 5-1 5-2 6-1 6-2 6-3 6-4 Title Page Number Cache Configuration ..................................................................................................... 1-8 CCR Field Descriptions ................................................................................................ 2-4 SR Field Descriptions .............................................
TABLES Table Page Title Number Number 6-5 CFMCLKD Field Descriptions................................................................................... 6-10 6-6 CFMSEC Field Descriptions ...................................................................................... 6-11 6-7 CFMPROT Field Descriptions ................................................................................... 6-12 6-8 CFMSACC Field Descriptions ..................................................................................
TABLES Table Page Title Number Number 10-2 Interrupt Controller Base Addresses........................................................................... 10-5 10-3 Interrupt Controller Memory Map .............................................................................. 10-5 10-4 IPRHn Field Descriptions ........................................................................................... 10-7 10-5 IPRLn Field Descriptions ...........................................................................
TABLES Table Page Title Number Number 15-3 DRAM Controller Registers ....................................................................................... 15-4 15-4 DCR Field Descriptions.............................................................................................. 15-5 15-5 DACRn Field Descriptions ......................................................................................... 15-6 15-6 DMRn Field Descriptions .....................................................................
TABLES Table Page Title Number Number 17-11 MIB Counters Memory Map .................................................................................... 17-22 17-12 EIR Field Descriptions.............................................................................................. 17-24 17-13 EIMR Field Descriptions .......................................................................................... 17-26 17-14 RDAR Field Descriptions ...................................................................
TABLES Table Page Title Number Number 20-8 GPTCNT Field Descriptions ...................................................................................... 20-8 20-9 GPTSCR1 Field Descriptions ..................................................................................... 20-8 20-10 GPTTOV Field Description........................................................................................ 20-9 20-11 GPTCL1 Field Descriptions ........................................................................
TABLES Table Page Title Number Number 23-15 UART Module Initialization Sequence .................................................................... 23-30 24-1 I2C Interface Memory Map ....................................................................................... 24-6 24-2 I2ADR Field Descriptions .......................................................................................... 24-6 24-3 I2FDR Field Descriptions ..............................................................................
TABLES Table Page Title Number Number 26-17 PTCPAR Field Descriptions ..................................................................................... 26-22 26-18 PTDPAR Field Descriptions..................................................................................... 26-23 26-19 PUAPAR Field Descriptions .................................................................................... 26-24 27-1 Multiplexed Analog Input Channels..................................................................
TABLES Table Page Title Number Number 29-10 DBMR Field Descriptions ........................................................................................ 29-13 29-11 Access Size and Operand Data Location .................................................................. 29-13 29-12 PBR Field Descriptions ............................................................................................ 29-14 29-13 PBMR Field Descriptions ..........................................................................
TABLES Table Page Title Number Number 33-9 SGFM Flash Module Life Characteristics ................................................................ 33-10 33-10 Processor Bus Input Timing Specifications.............................................................. 33-10 33-11 External Bus Output Timing Specifications ............................................................. 33-11 33-12 SDRAM Timing .......................................................................................................
About This Book The primary objective of this user’s manual is to define the functionality of the MCF5282 processors for use by software and hardware developers. The information in this book, except for changes to the Flash functionality, also applies to the MCF5281. The information in this book is subject to change without notice, as described in the disclaimers on the title page.
Organization xliv • Chapter 4, “Cache,” describes the MCF5282 cache implementation, including organization, configuration, and coherency. It describes cache operations and how the cache interacts with other memory structures. • Chapter 5, “Static RAM (SRAM),” describes the MCF5282 on-chip static RAM (SRAM) implementation. It covers general operations, configuration, and initialization. It also provides information and examples of how to minimize power consumption when using the SRAM.
Organization • Chapter 17, “Fast Ethernet Controller (FEC),” provides a feature-set overview, a functional block diagram, and transceiver connection information for both MII (Media Independent Interface) and 7-wire serial interfaces. It also provides describes operation and the programming model. • Chapter 18, “Watchdog Timer Module,” describes Watchdog timer functionality, including operation in low power mode.
Suggested Reading • Chapter 29, “Debug Support” describes the Revision A enhanced hardware debug support in the MCF5282. • Chapter 31, “IEEE 1149.1 Test Access Port (JTAG),” describes configuration and operation of the MCF5282 Joint Test Action Group (JTAG) implementation. It describes those items required by the IEEE 1149.1 standard and provides additional information specific to the MCF5282. For internal details and sample applications, see the IEEE 1149.1 document.
Conventions — ColdFire MCF5102 User’s Manual (MCF5102UM/AD) — ColdFire MCF5202 User’s Manual (MCF5202UM/AD) — ColdFire MCF5204 User’s Manual (MCF5204UM/AD) — ColdFire MCF5206 User’s Manual (MCF5206EUM/AD) — ColdFire MCF5206E User’s Manual (MCF5206EUM/AD) — ColdFire MCF5307 User’s Manual (MCF5307UM/AD) — ColdFire MCF5407 User’s Manual (MCF5407UM/AD) Additional literature on ColdFire implementations is being released as new processors become available.
Acronyms and Abbreviations Acronyms and Abbreviations Table i lists acronyms and abbreviations used in this document. Table i.
Terminology Conventions Table i.
Terminology Conventions Table ii.
Terminology Conventions Table ii.
Revision History Revision History Table iii provides a revision history for this document. Table iii. Revision History Revision Number Date of Release 0 11/2002 Preliminary release. 0.1 1/2003 Changed title from “MCF5282 ColdFire® Integrated Microprocessor User’s Manual” to “MCF5282 ColdFire® Microcontroller User’s Manual.” Substantive Changes 1.1/1-1 Changed equation in footnote to fsys = fref × 2(MFD + 2)/2 exp RFD; fref × 2(MFD + 2) ≤ 80 MHz, fsys ≤ 66 MHz.
Revision History Table iii. Revision History Revision Number Date of Release Substantive Changes Changed text in Step 1 to read “If fSYS ÷ 2 is greater than 12.8 MHz, PRDIV8 = 1; otherwise PRDIV8 = 0.” 6.4.3.1/6-18 Changed equation in Step 2 to the following: 6.4.3.1/6-18 fSYS DIV[5:0] = 2 x 200kHz x (1 + (PRDIV8 x 7)) Changed equation in Step 3 to the following: fCLK = 6.4.3.1/6-18 fSYS 2 x (DIV[5:0] + 1) x (1 + (PRDIV8 x 7)) Changed equations in example to reflect revisions above. 6.4.3.
Revision History Table iii. Revision History Revision Number Date of Release Substantive Changes Section/Page Changed value in “Divide by” block to 8192. Figure 18-1/18-2 Multiplied all system clock divisor values in PRE field description by 2. Table 19-3/19-4 Changed equation in text to the following: 19.6.3/19-7 Timeout period = PRE[3:0] × (PM[15:0] + 1) × system clock ÷ 2 In “UISR Field” row, changed bit 6 to a reserved bit. Figure 23-12/23-14 Changed bit 6 to a reserved bit.
Revision History Table iii. Revision History Revision Number Date of Release Substantive Changes Changed the min value in spec 2 to “4.” Table 33-23/33-25 Changed the min value in spec 3 to “25.” Table 33-23/33-25 Changed the min value in spec 6 to “25.” Table 33-23/33-25 Changed the max value in spec 7 to “30.” Table 33-23/33-25 Changed the max value in spec 8 to “30.” Table 33-23/33-25 Changed the max value in spec 11 to “25.” Table 33-23/33-25 Changed the min value in spec D1 to “5.
Revision History Table iii. Revision History Revision Number Date of Release Substantive Changes Section/Page Changed pull-up indications in the ‘Internal Pull-Up’ column. Table 14-3/14-11 Change encodings for bits 31–9 to: Table 17-13/17-26 0 The corresponding interrupt source is masked. 1 The corresponding interrupt source is not masked. Change PIT1–PIT4 to PIT0–PIT3 throughout chapter.
Chapter 1 Overview This chapter provides an overview of the MCF5282 microprocessor features, including the major functional components. 1.1 MCF5282 Key Features A block diagram of the MCF5282 is shown in Figure 1-1.
MCF5282 Key Features • • • 1-2 Power management — Fully-static operation with processor sleep and whole chip stop modes — Very rapid response to interrupts from the low-power sleep mode (wake-up feature) — Clock enable/disable for each peripheral when not used Fast Ethernet Controller (FEC) — 10BaseT capability, half- or full-duplex — 100BaseT capability, half- or limited-throughput full-duplex — On-chip transmit and receive FIFOs — Built-in dedicated DMA controller — Memory-based flexible descriptor r
MCF5282 Key Features • • • • Three universal asynchronous/synchronous receiver transmitters (UARTs) — 16-bit divider for clock generation — Interrupt control logic — Maskable interrupts — DMA support — Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity — Up to 2 stop bits in 1/16 increments — Error-detection capabilities — Modem support includes request-to-send (URTS) and clear-to-send (UCTS) lines for two UARTs — Transmit and receive FIFO buffers I2C module — Interchip bus interface f
MCF5282 Key Features • • • • 1-4 — Automated queue modes initiated by: – External edge trigger and gated trigger – Periodic/interval timer, within QADC module [Queue 1 and 2] – Software command — Single-scan or continuous-scan of queues — Output data readable in three formats: – Right-justified unsigned – Left-justified signed – Left-justified unsigned — Unused analog channels can be used as digital I/O — Low pin-count configuration implemented Four 32-bit DMA timers — 15-ns resolution at 66 MHz — Pro
MCF5282 Key Features • • • • Phase locked loop (PLL) — Crystal or external oscillator reference — 2- to 10-MHz reference frequency for normal PLL mode — 33- to 66-MHz oscillator reference frequency for 1:1 mode — Low-power modes supported — Separate clock output pin Two interrupt controllers — Support for up to 63 interrupt sources per interrupt controller (a total of 126), organized as follows: – 56 fully-programmable interrupt sources – 7 fixed-level interrupt sources — Seven external interrupt signa
MCF5282 Key Features • • • • 1-6 — Up to seven chip selects available — Byte/write enables (byte strobes) — Ability to boot from internal Flash memory or external memories that are 8, 16, or 32 bits wide Reset — Separate reset in and reset out signals — Seven sources of reset: – Power-on reset (POR) – External – Software – Watchdog – Loss of clock – Loss of lock – Low-voltage detection (LVD) — Status flag indication of source of last reset Chip integration module (CIM) — System configuration during re
Chip Configuration Reset Controller Power Management MCF5282 Key Features JTAG Port External Interface Module Test Controller Debug Module Ports Module ColdFire V2 Core Flash Module 64K SRAM DIV EMAC 2-Kbyte D-Cache/I-Cache Interrupt Controller 1 DMA Controller Interrupt Controller 0 Internal Bus Arbiter Edgeport System Control Module (SCM) Chip Selects DRAM Controller UART0 Serial I/O Clock Module (PLL) UART1 Serial I/O UART2 Serial I/O DMA Timer Modules (DTIM0– DTIM3) I2C Module
MCF5282 Key Features 1.1.1 Version 2 ColdFire Core The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes two pipeline stages.
MCF5282 Key Features as temporary storage during miss processing. For all data cache configurations, the memory operates in write-through mode and all operand writes generate an external bus cycle. 1.1.1.2 SRAM The SRAM module provides a general-purpose 64-Kbyte memory block that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 64-Kbyte boundary within the 4-Gbyte address space.
MCF5282 Key Features debug interface, users can access real-time trace and debug information. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The debug interface is a superset of the BDM interface provided on Motorola’s 683xx family of parts.
MCF5282 Key Features 1.1.4 Chip Select Programmable chip select outputs provide a glueless connection to external memory and peripheral circuits, providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing. 1.1.5 Power Management The MCF5282 incorporates several low-power modes of operation which are entered under program control and exited by several external trigger events.
MCF5282 Key Features 1.1.9 Test Access Port The MCF5282 supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register.
MCF5282 Key Features • • • • • Parity, framing, and overrun error detection False-start bit detection Line-break detection and generation Detection of breaks originating in the middle of a character Start/end break interrupt/status 1.1.11 DMA Timers (DTIM0-DTIM3) There are four independent, DMA-transfer-generating 32-bit timers (DTIM0, DTIM1, DTIM2, DTIM3) on the MCF5282. Each timer module incorporates a 32-bit timer with a separate register set for configuration and control.
MCF5282 Key Features 1.1.14 Software Watchdog Timer The watchdog timer is a 16-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown. 1.1.15 Phase Locked Loop (PLL) The clock module contains a crystal oscillator (OSC), phase-locked loop (PLL), reduced frequency divider (RFD), status/control registers, and control logic.
MCF5282-Specific Features 1.2 1.2.1 MCF5282-Specific Features Fast Ethernet Controller (FEC) The MCF5282’s integrated Fast Ethernet Controller (FEC) performs the full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface functions. The FEC supports connection and functionality for the 10/100 Mbps 802.3 media independent interface (MII). It requires an external transceiver (PHY) to complete the interface to the media. 1.2.
MCF5282-Specific Features status registers, the 64-entry conversion command word (CCW) table, and the 64-entry result table.
Chapter 2 ColdFire Core This section describes the organization of the Version 2 (V2) ColdFire® processor core and an overview of the program-visible registers. For detailed information on instructions, see the ColdFire Family Programmer’s Reference Manual. 2.1 Processor Pipelines Figure 2-1 is a block diagram showing the processor pipelines of a V2 ColdFire core.
Processor Register Description The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The Instruction Fetch Pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage Operand Execution Pipeline (OEP), which decodes the instruction, fetches the required operands and then executes the required function.
Processor Register Description 2.2.1.1 Data Registers (D0–D7) Registers D0–D7 are used as data registers for bit (1-bit), byte (8-bit), word (16-bit) and longword (32-bit) operations; they can also be used as index registers. 2.2.1.2 Address Registers (A0–A6) These registers can be used as software stack pointers, index registers, or base address registers; they can also be used for word and longword operations. 2.2.1.
Processor Register Description 31 15 7 0 D0 D1 D2 D3 D4 D5 D6 D7 15 7 DATA REGISTERS A0 A1 A2 A3 A4 A5 A6 ADDRESS REGISTERS A7 USERSTACK POINTER PC PROGRAM COUNTER CCR CONDITION CODE REGISTER 0 Figure 2-2. User Programming Model 2.2.1.5 Condition Code Register (CCR) The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results generated by processor operations.
Processor Register Description 2.2.2 EMAC Programming Model The registers in the EMAC portion of the user programming model, are described in Section Chapter 5, “Enhanced Multiply-Accumulate Unit (EMAC),” and include the following registers: • • • • Four 48-bit accumulator registers partitioned as follows: — Four 32-bit accumulators (ACC0–ACC3) — Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into two 32-bit values for load and store operations (ACCEXT01 and ACCEXT23).
Processor Register Description • • Two 32-bit access control registers (ACR0, ACR1) Two 32-bit memory base address registers (RAMBAR, FLASHBAR) 15 7 0 (CCR) SR STATUS OTHER_A7 SUPERVISOR A7 STACK POINTER VBR VECTOR BASE REGISTER CACR CACHE CONTROL ACR0 ACCESS CONTROL ACR1 ACCESS CONTROL FLASHBAR FLASH BASE ADDRESS REGISTER RAMBAR RAM BASE ADDRESS REGISTER 31 Figure 2-5. Supervisor Programming Model The following paragraphs describe the supervisor programming model registers. 2.2.3.
Processor Register Description Table 2-2. SR Field Descriptions (continued) Bits Name Description 12 M Master/interrupt state. This bit is cleared by an interrupt exception, and can be set by software during execution of the RTE or move to SR instructions. 11 — Reserved, should be cleared. 10–8 I 7–5 — 4–0 CCR 2.2.3.2 Interrupt level mask. Defines the current interrupt level.
Programming Model 2.2.3.3 Vector Base Register (VBR) The VBR contains the base address of the exception vector table in memory. To access the vector table, the displacement of an exception vector is added to the value in VBR. The lower 20 bits of the VBR are not implemented by ColdFire processors; they are assumed to be zero, forcing the table to be aligned on a 1 MByte boundary. 2.2.3.4 Cache Control Register (CACR) The CACR controls operation of the instruction/data cache memories.
Additions to the Instruction Set Architecture Table 2-3.
Exception Processing Overview Table 2-4. ISA Revision A+ New Instructions 2.5 Instruction Description BITREV The contents of the destination data register are bit-reversed; that is, new Dx[31] = old Dx[0], new Dx[30] = old Dx[1], ..., new Dx[0] = old Dx[31]. BYTEREV The contents of the destination data register are byte-reversed; that is, new Dx[31:24] = old Dx[7:0], ..., new Dx[7:0] = old Dx[31:24].
Exception Processing Overview Third, the processor saves the current context by creating an exception stack frame on the supervisor system stack. As a result, the exception stack frame is created at a 0-modulo-4 address on the top of the current system stack. Additionally, the processor uses a simplified fixed-length stack frame for all exceptions.
Exception Stack Frame Definition Table 2-5. Exception Vector Assignments (continued) Vector Number(S) Vector Offset (Hex) Stacked Program Counter Assignment 64–255 0x100–0x3FC Next User-defined interrupts “Fault” refers to the PC of the instruction that caused the exception; “Next” refers to the PC of the next instruction that follows the instruction that caused the fault. All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers.
Processor Exceptions • There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for access and address errors only and written as zeros for all other types of exceptions. See Table 2-7. Table 2-7. Fault Status Encodings FS[3:0] • 2.7 2.7.
Processor Exceptions The V2 ColdFire processor uses an imprecise reporting mechanism for access errors on operand writes. Because the actual write cycle may be decoupled from the processor’s issuing of the operation, the signaling of an access error appears to be decoupled from the instruction that generated the write. Accordingly, the PC contained in the exception stack frame merely represents the location in the program when the access error was signaled.
Processor Exceptions The STOP instruction has the following effects: 1. The instruction before the STOP executes and then generates a trace exception. In the exception stack frame, the PC points to the STOP opcode. 2. When the trace handler is exited, the STOP instruction is executed, loading the SR with the immediate operand from the instruction. 3. The processor then generates a trace exception.
Processor Exceptions 2.7.10 RTE and Format Error Exception When an RTE instruction is executed, the processor first examines the 4-bit format field to validate the frame type. For a ColdFire core, any attempted RTE execution where the format is not equal to {4,5,6,7} generates a format error. The exception stack frame for the format error is created without disturbing the original RTE frame and the stacked PC pointing to the RTE instruction.
Processor Exceptions The reset exception places the processor in the supervisor mode by setting the S-bit and disables tracing by clearing the T bit in the SR. This exception also clears the M-bit and sets the processor’s interrupt priority mask in the SR to the highest level (level 7). Next, the VBR is initialized to zero (0x00000000). The control registers specifying the operation of any memories (e.g., cache and/or RAM modules) connected directly to the processor are disabled.
Processor Exceptions Table 2-8. D0 Hardware Configuration Info Field Description Bits Name Description 31–24 PF 23–20 VER ColdFire core version number. This field is fixed to a hex value of 0x2 indicating a Version 2 ColdFire core. 19–16 REV Processor revision number. 15 MAC MAC execute engine status. Indicates if optional MAC unit is present. 0 MAC execute engine not present in core. (This is the value used for MCF5282.) 1 MAC execute engine is present in core.
Processor Exceptions 31 Field 30 29 CL 28 27 ICA 24 23 ICSIZ 20 RAM0SIZ Reset 0001_0011_1011_0000 R/W R 15 Field 14 BUSW 13 12 DCA 11 19 8 7 DCSIZ ROM0SIZ 4 3 RAM1SIZ Reset 0001_0000_1000_0000 R/W R 16 0 ROM1SIZ Figure 2-9. D1 Hardware Configuration Info Table 2-9. D1 Local Memory Hardware Configuration Information Field Description Bits Name 31–30 CL Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size.
Processor Exceptions Table 2-9. D1 Local Memory Hardware Configuration Information Field Description (continued) Bits 23–20 Name Description RAM0SIZ RAM bank 0 size. The first RAM bank can be used for either SRAM or Flash. The first encodings shown are used to indicate the size of a RAM bank, and the second set of encodings indicate the size for a Flash bank. On the MCF5282, RAM0 is associated with the on-chip Flash, so these bits use the Flash encodings. RAM size encodings: 0x0–0x3 No RAM.
Instruction Execution Timing Table 2-9. D1 Local Memory Hardware Configuration Information Field Description (continued) Bits Name Description 7–4 RAM1SIZ RAM bank 1size. 0x0–0x3 No RAM. 0100 4KB RAM. 0101 8KB RAM. 0110 16KB RAM. 0111 32KB RAM. 1000 64KB RAM. (This is the value used for MCF5282) 1001 128KB RAM. 0xA–0xF Reserved. 3–0 ROM1SIZ ROM bank 1size. 0x0–0x3 No ROM. (This is the value used for MCF5282) 0100 4KB ROM. 0101 8KB ROM. 0110 16KB ROM. 0111 32KB ROM. 1000 64KB ROM. 1001 128KB ROM.
Instruction Execution Timing 2. The OEP does not experience any sequence-related pipeline stalls. For V2 ColdFire processors, the most common example of this type of stall involves consecutive store operations, excluding the MOVEM instruction. For all STORE operations (except MOVEM), certain hardware resources within the processor are marked as “busy” for two processor clock cycles after the final DSOC cycle of the store instruction.
Instruction Execution Timing Table 2-11. Move Byte and Word Execution Times Destination Source Rx (Ax) (Ax)+ -(Ax) (d16,Ax) (d8,Ax,Xi) (xxx).
Standard One Operand Instruction Execution Times 2.9 Standard One Operand Instruction Execution Times Table 2-13. One Operand Instruction Execution Times Effective Address Opcode Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl #xxx bitrev Dx 1(0/0) — — — — — — — byterev Dx 1(0/0) — — — — — — — clr.b 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) — clr.w 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1) — clr.
Standard Two Operand Instruction Execution Times Table 2-14. Two Operand Instruction Execution Times (continued) Effective Address Opcode and.l (d16,An) (d8,An,Xn*SF) (d16,PC) (d8,PC,Xn*SF) Rn (An) (An)+ -(An) ,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) and.l Dy, — 3(1/1) 3(1/1) 3(1/1) andi.l #imm,Dx 1(0/0) — — asl.l ,Dx 1(0/0) — asr.l ,Dx 1(0/0) bchg Dy, bchg xxx.
Miscellaneous Instruction Execution Times Table 2-14. Two Operand Instruction Execution Times (continued) Effective Address 1 Opcode subi.l (d16,An) (d8,An,Xn*SF) (d16,PC) (d8,PC,Xn*SF) Rn (An) (An)+ -(An) #imm,Dx 1(0/0) — — — — subq.l #imm, 1(0/0) 3(1/1) 3(1/1) 3(1/1) subx.l Dy,Dx 1(0/0) — — — xxx.wl #xxx — — — 3(1/1) 4(1/1) 3(1/1) — — — — — For divide and remainder instructions the times listed represent the worst-case timing.
EMAC Instruction Execution Times 2.12 EMAC Instruction Execution Times Table 2-16. EMAC Instruction Execution Times Effective Address Opcode 1 2 Rn (An) (An)+ -(An) (d16,An) (d8,An,X n*SF) xxx.wl #xxx muls.w y, Dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) 7(1/0) 6(1/0) 4(1/0) mulu.w y, Dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) 7(1/0) 6(1/0) 4(1/0) muls.l y, Dx 4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) — — — mulu.
Branch Instruction Execution Times NOTE The execution times for moving the contents of the Racc, Raccext[01,23], MACSR, or Rmask into a destination location x shown in this table represent the best-case scenario when the store instruction is executed and there are no load or M{S}AC instructions in the EMAC execution pipeline.
ColdFire Instruction Set Architecture Enhancements BITREV BITREV Bit Reverse Register (Supported Starting with ISA A+) Operation: Bit Reversed Dx → Dx Assembler Syntax: BITREV.L Dx Attributes: Size = longword Instruction Format: 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 0 0 1 1 0 0 0 2 1 0 Register, Dx The contents of the destination data register are bit-reversed; that is, new Dx[31] = old Dx[0], new Dx[30] = old Dx[1], ..., new Dx[0] = old Dx[31].
ColdFire Instruction Set Architecture Enhancements BYTEREV BYTEREV Byte Reverse Register (Supported Starting with ISA A+) Operation: Byte Reversed Dx → Dx Assembler Syntax: BYTEREV.
ColdFire Instruction Set Architecture Enhancements FF1 FF1 Find First One in Register (Supported Starting with ISA A+) Operation: Bit Offset of the First Logical One in Register → Destination Assembler Syntax: FF1.
ColdFire Instruction Set Architecture Enhancements STRLDSR STRLDSR Store/Load Status Register (Supported Starting with ISA A+) Operation: If Supervisor State Then SP - 4 → SP; zero-filled SR → (SP); immediate data → SR Else TRAP Assembler Syntax:STRLDSR # Attributes: Instruction Format: Size = word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 1 1 1 1 1 1 0 0 Immediate Data Description: Pushes the contents
Chapter 3 Enhanced Multiply-Accumulate Unit (EMAC) This chapter describes the functionality, microarchitecture, and performance of the enhanced multiply-accumulate (EMAC) unit in the ColdFire family of processors. 3.1 Multiply-Accumulate Unit The MAC design provides a set of DSP operations which can be used to improve the performance of embedded code while supporting the integer multiply instructions of the baseline ColdFire architecture.
Introduction to the MAC • A 48-bit accumulation data path to allow the use of a 40-bit product plus the addition of 8 extension bits to increase the dynamic number range when implementing signal processing algorithms. The three areas of functionality are addressed in detail in following sections. The logic required to support this functionality is contained in a MAC module, as shown in Figure 3-1. Operand Y Operand X X Shift 0,1,-1 +/- Accumulator(s) Figure 3-1.
General Operation N–1 y(i) = N–1 ∑ a ( k )y ( i – k ) + ∑ b ( k )x ( i – k ) k=1 k=0 Figure 3-2. Infinite Impulse Response (IIR) Filter Here, the output y(i) is determined by past output values and past input values. This is the general form of an infinite impulse response (IIR) filter. A finite impulse response (FIR) filter can be obtained by setting coefficients a(k) to zero. In either case, the operations involved in computing such a filter are multiplies and product summing.
General Operation For all operations, the resulting 40-bit product is extended to a 48-bit value (using sign-extension for signed integer and fractional operands, zero-fill for unsigned integer operands) before being combined with the 48-bit destination accumulator. Figure 3-4 and Figure 3-5 show relative alignment of input operands, the full 64-bit product, the resulting 40-bit product used for accumulation, and 48-bit accumulator formats.
General Operation Thus, the 48-bit accumulator definition is a function of the EMAC operating mode.
Memory Map/Register Set The additional MAC status register (MACSR) contains a 4-bit operational mode field and condition flags. Operational mode bits control whether operands are signed or unsigned and whether they are treated as integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding is performed. Negative, zero, and multiple overflow condition flags are also provided. 3.
Memory Map/Register Set Table 3-1. MACSR Field Descriptions Bits Name 31–12 — 11–8 PAVx 7–4 Description Reserved, should be cleared. Product/accumulation overflow flags. Contains four flags, one per accumulator, that indicate if past MAC or MSAC instructions generated an overflow during product calculation or the 48-bit accumulation. When a MAC or MSAC instruction is executed, the PAVx flag associated with the destination accumulator is used to form the general overflow flag, MACSR[V].
Memory Map/Register Set Table 3-1. MACSR Field Descriptions (continued) Bits Name Description 2 Z Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC, and load operations; it is not affected by MULS and MULU instructions. 1 V Overflow. Set if an arithmetic overflow occurs on a MAC or MSAC instruction indicating that the result cannot be represented in the limited width of the EMAC.
Memory Map/Register Set • Execution of a MAC (or MSAC) instruction with 32-bit operands. If MACSR[R/T] is zero, multiplying two 32-bit numbers creates a 64-bit product that is truncated to the upper 40 bits; otherwise, it is rounded using round-to-nearest (even) method. To understand the round-to-nearest-even method, consider the following example involving the rounding of a 32-bit number, R0, to a 16-bit number. Using this method, the 32-bit number is rounded to the closest 16-bit number possible.
Memory Map/Register Set The following assembly language routine shows the proper sequence for a correct EMAC state save. This code assumes all Dn and An registers are available for use and the memory location of the state save is defined by A7. EMAC_state_save: move.l macsr,d7 clr.l d0 move.l d0,macsr move.l acc0,d0 move.l acc1,d1 move.l acc2,d2 move.l acc3,d3 move.l accext01,d4 move.l accext23,d5 move.l mask,d6 movem.l #0x00ff,(a7) ; ; ; ; save the macsr zero the register to ...
Memory Map/Register Set This register performs a simple AND with the operand address for MAC instructions. That is, the processor calculates the normal operand address and, if enabled, that address is then ANDed with {0xFFFF, MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the operand address can be constrained to a certain memory region. This is used primarily to implement circular queues in conjunction with the (An)+ addressing mode.
EMAC Instruction Set Summary 3.5 EMAC Instruction Set Summary Table 3-3 summarizes EMAC unit instructions. Table 3-3.
EMAC Instruction Set Summary The mov.l instruction that stores the accumulator to an integer register (Rz) stalls until the program-visible copy of the accumulator is available. Figure 3-8 shows EMAC timing. Three-cycle regBusy stall DSOC AGEX mac EMAC EX1 EMAC EX2 EMAC EX3 EMAC EX4 mov mov mac mov mac mov Accumulator 0 mac mac mac old new Figure 3-8.
EMAC Instruction Set Summary N–2 value = – ( 1 ⋅ a N – 1 ) + ∑ 2 (i + 1 – N) ⋅ ai i=0 Figure 3-9. Two’s Complement, Signed Fractional Equation This format can represent numbers in the range -1 < operand < 1 - 2(N-1). For words and longwords, the largest negative number that can be represented is -1, whose internal representation is 0x8000 and 0x8000_0000, respectively. The largest positive word is 0x7FFF or (1 - 2-15); the most positive longword is 0x7FFF_FFFF or (1 - 2-31). 3.5.
EMAC Instruction Set Summary — For unsigned word and longword operations, a zero is shifted into the product on right shifts. — For signed, word operations, the sign bit is shifted into the product on right shifts unless the product is zero. For signed, longword operations, the sign bit is shifted into the product unless an overflow occurs or the product is zero, in which case a zero is shifted in. — For all left shifts, a zero is inserted into the lsb position.
EMAC Instruction Set Summary f } /* sign-extend to 48 bits before performing any scaling */ product[47:40] = {8{product[39]}} /* sign-extend */ /* scale product before combining with accumulator */ switch (SF) /* 2-bit scale factor */ { case 0: /* no scaling specified */ break; case 1: /* SF = “<< 1” */ product[40:0] = {product[39:0], 0} break; case 2: /* reserved encoding */ break; case 3: /* SF = “>> 1” */ product[39:0] = {product[39], product[39:1]} break; } if (MACSR.
EMAC Instruction Set Summary if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {Ry[31:16], 0x0000} else operandY[31:0] = {Ry[15:0], 0x0000} if (U/Lx == 1) then operandX[31:0] = {Rx[31:16], 0x0000} else operandX[31:0] = {Rx[15:0], 0x0000} } else {operandY[31:0] = Ry[31:0] operandX[31:0] = Rx[31:0] } /* perform the multiply */ product[63:0] = (operandY[31:0] * operandX[31:0]) << 1 /* check for product rounding */ if (MACSR.
EMAC Instruction Set Summary then { MACSR.
EMAC Instruction Set Summary } /* check for accumulation overflow */ if (accumulationOverflow == 1) then {MACSR.PAVx = 1 MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1) then result[47:0] = 0x0000_0000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ result[47:0] = 0xffff_ffff_ffff } /* transfer the result to the accumulator */ ACCx[47:0] = result[47:0] } MACSR.V = MACSR.PAVx MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.
EMAC Instruction Set Summary 3-20 MCF5282 User’s Manual MOTOROLA
Chapter 4 Cache This chapter describes the MCF5282 cache operation. 4.1 • • • • • • • 4.
Cache Physical Organization array address. The tag array outputs the address mapped to the given cache location along with the valid bit for the line. This address field is compared to bits [31:11] for instructionor data-only configurations and to bits [31:10] for a split configuration of the fetch address from the local bus to determine if a cache hit has occurred.
Cache Operation External Data[31:0] 31 Local Address Bus 10 4 3 21 0 31 4 I or D Line Buffer Storage Buffer Address I or D Line MUX = Fill Hit TAG 0 VALID 11 31 31 0 0 DATA ‘512 128 = Tag Hit MUX Local Data Bus Figure 4-1. Cache Block Diagram 4.3 Cache Operation The cache is physically connected to the ColdFire core's local bus, allowing it to service all fetches from the ColdFire core and certain memory fetches initiated by the debug module.
Cache Operation 4.3.2 Memory Reference Attributes For every memory reference the ColdFire core or the debug module generates, a set of “effective attributes” is determined based on the address and the access control registers (ACRs). This set of attributes includes the cacheable/noncacheable definition, the precise/imprecise handling of operand write, and the write-protect capability. In particular, each address is compared to the values programmed in the ACRs.
Cache Operation 4.3.4 Reset A hardware reset clears the CACR and disables the cache. The contents of the tag array are not affected by the reset. Accordingly, the system startup code must explicitly perform a cache invalidation by setting CACR[24] before the cache can be enabled. 4.3.5 Cache Miss Fetch Algorithm/Line Fills As discussed in Section 4.2, “Cache Physical Organization,” the cache hardware includes a 16-byte line-fill buffer for providing temporary storage for the last fetched line.
Cache Operation Once an external fetch has been initiated and the data is loaded into the line-fill buffer, the cache maintains a special “most-recently-used” indicator that tracks the contents of the associated line-fill buffer versus its corresponding cache location. At the time of the miss, the hardware indicator is set, marking the line-fill buffer as “most recently used.
Cache Programming Model 4.4 Cache Programming Model Three supervisor registers define the operation of the cache and local bus controller: the cache control register (CACR) and two access control registers (ACR0, ACR1). 4.4.1 Cache Registers Memory Map Table 4-3 below shows the memory map of the cache and access control registers.
Cache Programming Model 31 30 Field CENB 29 — 28 27 26 CPD CFRZ 25 — 24 23 22 CINV DIDI DISD Reset 0000_0000_0000_0000 R/W W 15 11 Field — 10 9 8 7 CEIB DCM DBWE Reset 0000_0000_0000_0000 R/W W 6 — 21 20 19 16 INVI INVD 5 4 DWP EUSP — 3 2 — 1 0 CLNF Figure 4-2. Cache Control Register (CACR) Table 4-4. CACR Field Descriptions Bits Name Description 31 CENB Cache enable. The memory array of the cache is enabled only if CENB is asserted.
Cache Programming Model Table 4-4. CACR Field Descriptions (continued) Bits Name Description 22 DISD Disable data caching. When set, this bit disables data caching. This bit, along with the CENB (cache enable) and DISI (disable instruction caching) bits, control the cache configuration. See the CENB definition for a detailed description. 0 Do not disable data caching 1 Disable data caching Table 4-5 describes cache configuration and Table 4-6 describes how to set the cache invalidate all bit.
Cache Programming Model Table 4-4. CACR Field Descriptions (continued) Bits Name 3–2 — 1–0 CLNF Description Reserved, should be cleared. Cache line fill. These bits control the size of the memory request the cache issues to the bus controller for different initial instruction line access offsets. See Table 4-7 for external fetch size based on miss address and CLNF. Table 4-5 shows the relationship between CACR bits 31, 23, and 22 and the cache configuration. Table 4-5.
Cache Programming Model Table 4-7. External Fetch Size Based on Miss Address and CLNF Longword Address Bits CLNF[1:0] 4.4.2.2 00 01 10 11 00 Line Line Line Longword 01 Line Line Longword Longword 10 Line Line Line Line 11 Line Line Line Line Access Control Registers (ACR0, ACR1) The ACRs provide a definition of memory reference attributes for two memory regions (one per ACR).
Cache Programming Model Table 4-8. ACR Field Descriptions (continued) Bits Name 14–13 SM Supervisor mode. This two-bit field allows the given ACR to be applied to references based on operating privilege mode of the ColdFire processor. The field uses the ACR for user references only, supervisor references only, or all accesses. 00 Match if user mode 01 Match if supervisor mode 1x Match always—ignore user/supervisor mode 12–7 — Reserved, should be cleared. 6 CM Cache mode.
Chapter 5 Static RAM (SRAM) 5.1 • • • • • 5.2 SRAM Features One 64-Kbyte SRAM Single-cycle access Physically located on processor's high-speed local bus Memory location programmable on any 0-modulo-64 Kbyte address Byte, word, longword address capabilities SRAM Operation The SRAM module provides a general-purpose memory block that the ColdFire processor can access in a single cycle. The location of the memory block can be specified to any 0-modulo-64K address within the 4-GByte address space.
SRAM Programming Model 5.3.1 SRAM Base Address Register (RAMBAR) The configuration information in the SRAM base address register (RAMBAR) controls the operation of the SRAM module. • The RAMBAR holds the base address of the SRAM. The MOVEC instruction provides write-only access to this register. The RAMBAR can be read or written from the debug module in a similar manner. All undefined bits in the register are reserved.
SRAM Programming Model Table 5-1. SRAM Base Address Register (continued) Bits Name Description 9 SPV Secondary port valid. Allows access by DMA 0 DMA access to memory is disabled. 1 DMA access to memory is enabled. NOTE: The BDE bit in the second RAMBAR register must also be set to allow dual port access to the SRAM. For more information, see Section 8.4.2, “Memory Base Address Register (RAMBAR).” 8 WP Write protect. Allows only read accesses to the SRAM.
SRAM Programming Model The ColdFire processor or an external emulator using the debug module can perform these initialization functions. 5.3.3 SRAM Initialization Code The following code segment describes how to initialize the SRAM. The code sets the base address of the SRAM at 0x20000000 and then initializes the SRAM to zeros. RAMBASE EQU $20000000 ;set this variable to $20000000 RAMVALID EQU $00000001 move.l #RAMBASE+RAMVALID,D0 ;load RAMBASE + valid bit into D0. movec.
SRAM Programming Model MOTOROLA Chapter 5.
SRAM Programming Model 5-6 MCF5282 User’s Manual MOTOROLA
Chapter 6 ColdFire Flash Module (CFM) The MCF5282 incorporates SuperFlash® technology licensed from SST. The ColdFire Flash Module (CFM) is constructed with eight banks of 32K x 16-bit Flash to generate a 512-Kbyte, 32-bit wide electrically erasable and programmable read-only memory array. The CFM is ideal for program and data storage for single-chip applications and allows for field reprogramming without external high-voltage sources.
Block Diagram • • • Security for single-chip applications Single power supply (system VDD) used for all module operations Auto-sense amplifier timeout for low-power, low-frequency read operations NOTE Enabling Flash security will disable BDM communications. NOTE When Flash security is enabled, the chip will boot in single-chip mode regardless of the external reset configuration. 6.
Block Diagram An erased Flash bit reads 1 and a programmed Flash bit reads 0. The CFM features a sense amplifier timeout (SATO) block that automatically reduces current consumption during reads at low system clock frequencies.
Memory Map 6.3 Memory Map Figure 6-2 shows the memory map for the CFM array. The CFM array can reside anywhere in the memory space of the MCU. The starting address of the array is determined by the CFM array base address which must reside on a natural size boundary; that is, the CFM array base address must be an integer multiple of the array size. The CFM register space must reside on a 64 byte boundary as determined by the CFM register base address.
Memory Map The CFM module has hardware interlocks to protect data from accidental corruption. The CFM memory array is logically divided into 16-Kbyte sectors for the purpose of data protection and access control. A flexible scheme allows the protection of any combination of logical sectors (see Section 6.3.4.4, “CFM Protection Register (CFMPROT)”). A similar mechanism is available to control supervisor/user and program/data space access to these sectors. 6.3.
Memory Map • The FLASHBAR valid bit is programmed according to the chip mode selected at reset (see Chapter 30, “Chip Configuration Module (CCM)” for more details). All other bits are unaffected. The FLASHBAR register contains several control fields. These fields are shown in Figure 6-3 NOTE The default value of the FLASHBAR is determined by the chip configuration selected at reset (see Chapter 30, “Chip Configuration Module (CCM)” for more information).
Memory Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 Field BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 Reset 0000_0000_0000_0000 R/W R/W 15 9 Field — 8 WP Reset 7 6 — — 5 4 3 2 1 0 C/I SC SD UC UD V 0000_0001_0010_000 R/W R/W R Address R/W 16 See Note R R/W CPU + 0xC04 Note: The reset value for the valid bit is determined by the chip mode selected at reset (see Chapter 30, “Chip Configuration Module (CCM)”). Figure 6-3.
Memory Map 6.3.3 CFM Registers The CFM module also contains a set of control and status registers. The memory map for these registers and their accessibility in supervisor and user modes is shown in Table 6-3. Table 6-3.
Memory Map Table 6-4. CFMCR Field Descriptions Bits Name 15–11 — 10 LOCK Write lock control. The LOCK bit is always readable and is set once. 1 CFMPROT, CMFSACC, and CFMDACC register are write-locked. 0 CFMPROT, CMFSACC, and CFMDACC register are writable. 9 PVIE Protection violation interrupt enable. The PVIE bit is readable and writable. The PVIE bit enables an interrupt in case the protection violation flag, PVIOL, is set. 1 An interrupt will be requested whenever the PVIOL flag is set.
Memory Map Table 6-5. CFMCLKD Field Descriptions Bits Name Description 7 DIVLD Clock divider loaded 1 CFMCLKD has been written since the last reset. 0 CFMCLKD has not been written. 6 PRDIV8 Enable prescaler divide by 8 1 Enables a prescaler that divides the CFM clock by 8 before it enters the CFMCLKD divider. 0 The CFM clock is fed directly into the CFMCLKD divider. 5–0 DIV Clock divider field.
Memory Map Table 6-6. CFMSEC Field Descriptions Bits Name Description 31 KEYEN 30 SECSTAT Flash security status 1 Flash security is enabled 0 Flash security is disabled 29–16 — Reserved. Should be cleared. 15–0 SEC[15:0] Enable back door key to security 1 Back door to Flash is enabled. 0 Back door to Flash is disabled. Security field. The SEC bits define the security state of the device; see below.
Memory Map 6.3.4.4 CFM Protection Register (CFMPROT) The CFMPROT specifies which Flash logical sectors are protected from program and erase operations. 31 16 Field PROT Reset See Note R/W R/W 15 0 Field PROT Reset See Note R/W R/W Address IPSBAR + 0x1D_0010 Note: The CFMPROT register is loaded at reset from the Flash Program/Erase Sector Protection longword stored at the array base address + 0x0000_0400. Figure 6-7.
Memory Map (ARRAY_BASE + 0x0007_FFFF) SECTOR 31 PROTECT[31] (ARRAY_BASE + 0x0007_C000) • • • PROTECT[2] } 16Kbyte Sector SECTOR 2 Protected Flash Logical Sectors as defined by CFMPROT register (ARRAY_BASE + 0x0000_8000) SECTOR 1 (ARRAY_BASE + 0x0000_4000) SECTOR 0 (ARRAY_BASE + 0x0000_0000) Figure 6-8. CFMPROT Protection Diagram 6.3.4.5 CFM Supervisor Access Register (CFMSACC) The CFMSACC specifies the supervisor/user access permissions of Flash logical sectors.
Memory Map Table 6-8. CFMSACC Field Descriptions Bits Name Description 31–0 SUPV[31:0] Supervisor address space assignment. The SUPV[31:0] bits are always readable and only writable when LOCK = 0. Each Flash logical sector can be mapped into supervisor or unrestricted address space. CFMSACC uses the same correspondence between logical sectors and register bits as does CFMPROT. See Figure 6-8 for details.
Memory Map 6.3.4.7 CFM User Status Register (CFMUSTAT) The CFMUSTAT reports Flash state machine command status, array access errors, protection violations, and blank check status. Field 7 6 CBEIF CCIF Reset R/W 5 1 PVIOL ACCERR — BLANK 0 — 1100_0000 R/W Address R R/W IPSBAR + 0x1D_0020 Figure 6-11. CFM User Status Register (CFMUSTAT) NOTE Only one CFMUSTAT bit should be cleared at a time. Table 6-10.
Memory Map Table 6-10. CFMUSTAT Field Descriptions Bits Name Description 2 BLANK Erase Verified Flag. The BLANK flag indicates that the erase verify command (RDARY1) has checked the two interleaved Flash physical blocks selected by BKSL[1:0] and found them to be blank. Clear BLANK by writing it to 1. Writing a 0 has no effect. 1 Flash physical blocks verify as erased. 0 If an erase verify command has been requested, and the CCIF flag is set, then the selected Flash physical blocks are not blank.
CFM Operation 6.4 CFM Operation The CFM registers, subject to the restrictions previously noted, can generally be read and written (see Section 6.3.4, “Register Descriptions” for details). Reads of the CFM array occur normally and writes behave according to the setting of the KEYACC bit in CFMCR. Program, erase, and verify operations are initiated by the CPU. Special cases of user mode apply when the CPU is in low-power or debug modes and when the MCU boots in master mode or emulation mode. 6.4.
CFM Operation 6.4.3.1 Setting the CFMCLKD Register Prior to issuing any program or erase commands, CFMCLKD must be written to set the Flash state machine clock (FCLK). The CFM module runs at the system clock frequency ÷ 2, but FCLK must be divided down from this frequency to a frequency between 150 kHz and 200 kHz. Use the following procedure to set the PRDIV8 and DIV[5:0] bits in CFMCLKD: 1. If fSYS ÷ 2 is greater than 12.8 MHz, PRDIV8 = 1; otherwise PRDIV8 = 0. 2.
CFM Operation WARNING For proper program and erase operations, it is critical to set fCLK between 150 kHz and 200 kHz. Array damage due to overstress can occur when fCLK is less than 150 kHz. Incomplete programming and erasure can occur when fCLK is greater than 200 kHz. NOTE Command execution time increases proportionally with the period of fCLK. When CFMCLKD is written, the DIVLD bit is set automatically. If DIVLD is 0, CFMCLKD has not been written since the last reset.
CFM Operation The Flash state machine flags errors in command write sequences by means of the ACCERR and PVIOL flags in the CFMUSTAT register. An erroneous command write sequence self-aborts and sets the appropriate flag. The ACCERR or PVIOL flags must be cleared before commencing another command write sequence. NOTE By writing a 0 to CBEIF, a command sequence can be aborted after the longword write to the CFM array or the command write to the CFMCMD and before the command is launched.
CFM Operation START READ CFMCLKD CLOCK REGISTER WRITTEN CHECK NO DIVLD SET? YES WRITE CFMCLKD READ CFMUSTAT CBEIF SET? NO YES WRITE PROGRAM DATA TO ARRAY ADDRESS 1. 2. NOTE: COMMAND SEQUENCE WRITE PROGRAM COMMAND 0x20 ABORTED BY WRITING 0x00 TO CFMCMD TO CFMUSTAT 3.
CFM Operation 6.4.3.4 Flash User Mode Illegal Operations The ACCERR flag will be set during a command write sequence if any of the illegal operations below are performed. Such operations will cause the command sequence to immediately abort. 1. Writing to the CFM array before initializing CFMCLKD. 2. Writing to the CFM array while in emulation mode. 3. Writing a byte or a word to the CFM array. Only 32-bit longword programming is allowed. 4. Writing to the CFM array while CBEIF is not set. 5.
Flash Security Operation 3. The CCIF and ACCERR flags are set if a command is active when the MCU enters stop mode. NOTE The state of any longword(s) being programmed or any erase pages/physical blocks being erased is not guaranteed if the MCU enters stop mode with a command in progress. WARNING Active commands are immediately aborted when the MCU enters stop mode. Do not execute the STOP instruction during program and erase operations. 6.4.
Reset 6.5.1 Back Door Access If the KEYEN bit is set, security can be bypassed by: 1. Setting the KEYACC bit in the CFM configuration register (CFMMCR). 2. Writing the correct 8-byte back door comparison key to the CFM array at addresses 0x0000_0400 to 0x0000_0407. This operation must consist of two 32-bit writes to address 0x0000_0400 and 0x0000_0404 in that order. The two back door write cycles can be separated by any number of bus cycles. 3. Clearing the KEYACC bit. 4.
Interrupts 6.7 Interrupts The CFM module can request an interrupt when all commands are completed or when the address, data, and command buffers are empty. Table 6-14 shows the CFM interrupt mechanism. Table 6-14. CFM Interrupt Sources MOTOROLA Interrupt Source Interrupt Flag Local Enable Command, data and address buffers empty CBEIF (CFMUSTAT) CBEIE (CFMCR) All commands are completed CCIF (CFMUSTAT) CCIE (CFMCR) Access error ACCERR (CFMUSTAT) AEIE (CFMCR) Chapter 6.
Interrupts 6-26 MCF5282 User’s Manual MOTOROLA
Chapter 7 Power Management The Power Management Module (PMM) controls the low-power operation on the MCF5282. 7.1 Features The following features support low-power operation. • • • 7.2 Four modes of operation: — Run — Wait — Doze — Stop Ability to shut down most peripherals independently Ability to shut down the external CLKOUT pin Memory Map and Registers This subsection provides a description of the memory map and registers. 7.2.
Memory Map and Registers 7.2.2 Memory Map Table 7-1. Chip Configuration Module Memory Map IPSBAR Offset Bits 31–24 Bits 23–16 Bits 15–8 Bits 7–0 Access 1 0x0000_0010 Core Reset Status Register (CRSR) 2 Core Watchdog Control Register (CWCR) Low-Power Interrupt Control Register (LPICR) Core Watchdog Service Register (CWSR) S Reserved Low-Power Control Register (LPCR) S 0x0011_0004 Chip Configuration Register (CCR) 3 1 S = CPU supervisor mode access only.
Memory Map and Registers 3. The entry into a low-power mode is processed by the low-power mode control logic, and the appropriate clocks (usually those related to the high-speed processor core) are disabled. 4. After entering the low-power mode, the interrupt controller enables a combinational logic path which evaluates any unmasked interrupt requests. The device waits for an event to generate an interrupt request with a priority level greater than the value programmed in LPICR[XLPM_IPL[2:0]].
Memory Map and Registers Table 7-3. XLPM_IPL Settings 7.2.3.
Functional Description Table 7-5. Low-Power Modes LPMD[1:0] Mode 11 STOP 10 WAIT 01 DOZE 00 RUN Table 7-6.
Functional Description The latter method of exiting from low-power mode, by a valid and enabled interrupt request, requires several things: • • • • An interrupt request whose priority is higher than the value programmed in the XLPM_IPL field of the LPICR An interrupt request whose priority higher than the value programmed in the interrupt priority mask (I) field of the core’s status register An interrupt request from a source which is not masked in the interrupt controller’s interrupt mask register An int
Functional Description NOTE Entering stop mode will disable the SDRAMC including the refresh counter. If SDRAM is used, then code is required to insure proper entry and exit from stop mode. See Section 7.3.2.5, “SDRAM Controller (SDRAMC)” for more information. 7.3.1.5 Peripheral Shut Down Most peripherals may be disabled by software in order to cease internal clock generation and remain in a static state.
Functional Description 7.3.2.5 SDRAM Controller (SDRAMC) SDRAMC operation is unaffected by either the wait or doze modes; however, the SDRAMC is disabled by stop mode. Since all clocks to the SDRAMC are disabled by stop mode, the SDRAMC will not generate refresh cycles. To prevent loss of data the SDRAM should be placed in self-refresh mode by setting DCR[IS] before entering stop mode.
Functional Description In stop mode, the UARTs stop immediately and freeze their operation, register values, state machines, and external pins. During this mode, the UART clocks are shut down. Coming out of stop mode returns the UARTs to operation from the state prior to the low-power mode entry. 7.3.2.
Functional Description DMA timer operation is disabled in stop mode, but the DMA timer is unaffected by either the wait or doze modes and may generate an interrupt to exit these modes. Upon exiting stop mode, the timer will resume operation unless stop mode was exited by reset. 7.3.2.12 Interrupt Controllers (INTC0, INTC1) The interrupt controller is not affected by any of the low-power modes.
Functional Description If the phase lock loop (PLL) in the clock module is active and if the appropriate (LOCRE, LOLRE) bits in the synthesizer control register are set, then any loss-of-clock or loss-of-lock will reset the chip and exit any low-power modes. If the watchdog timer is still enabled during wait or doze modes, then a watchdog timer timeout may generate a reset to exit these low-power modes. When the CPU is inactive, a software reset cannot be generated to exit any low-power mode. 7.3.2.
Functional Description The external CLKOUT output pin may be disabled in the low state to lower power consumption via the DISCLK bit in the SYNCR. The external CLKOUT pin function is enabled by default at reset. 7.3.2.18 Edge Port In wait and doze modes, the edge port continues to operate normally and may be configured to generate interrupts (either an edge transition or low level on an external pin) to exit the low-power modes.
Functional Description 7.3.2.22 General Purpose Timers (GPTA and GPTB) When not stopped, the General Purpose Timers may generate an interrupt to exit the low-power modes. Clearing the timer enable bit (TE) in the GPT system control register 1 (GPTSCR1) or the pulse accumulator enable bit (PAE) in the GPT pulse accumulator control register (GPTPACTL) disables timer functions.
Functional Description • Self-wake mechanism. If the SELF-WAKE bit in the MCR is set at the time the FlexCAN enters stop mode, then upon detection of recessive to dominant transition on the CAN bus, the FlexCAN resets the STOP bit in the MCR and resumes its clocks.
Functional Description lasts until the next recessive to dominant edge, which re-synchronizes the FlexCAN back to conform to the protocol. The same holds for auto-power save mode upon wake-up by recessive to dominant edge. The auto-power save mode in the FlexCAN is intended to enable NORMAL operation with optimized power saving. Upon setting the AUTO POWER SAVE bit in the MCR register, the FlexCAN looks for a set of conditions in which there is no need for clocks to run.
Functional Description 7.3.2.25 BDM Entering halt mode via the BDM port (by asserting the external BKPT pin) will cause the CPU to exit any low-power mode. 7.3.2.26 JTAG The JTAG (Joint Test Action Group) controller logic is clocked using the TCLK input and is not affected by the system clock. The JTAG cannot generate an event to cause the CPU to exit any low-power mode. Toggling TCLK during any low-power mode will increase the system current consumption. 7.3.
Functional Description Table 7-7.
Functional Description 7-18 MCF5282 User’s Manual MOTOROLA
Chapter 8 System Control Module (SCM) This section details the functionality of the System Control Module (SCM) which provides the programming model for the System Access Control Unit (SACU), the system bus arbiter, a 32-bit core watchdog timer (CWT), and the system control registers and logic.
Memory Map and Register Definition • • 8.
Register Descriptions 8.4 8.4.1 Register Descriptions Internal Peripheral System Base Address Register (IPSBAR) The IPSBAR specifies the base address for the 1 Gbyte memory space associated with the on-chip peripherals. At reset, the base address is loaded with a default location of 0x4000_0000 and marked as valid (IPSBAR[V]=1). If desired, the address space associated with the internal modules can be moved by loading a different value into the IPSBAR at a later time.
Register Descriptions 31 30 29 16 Field BA31 BA30 Reset 0 — 1 — R/W R/W 15 1 Field — Reset — R/W 0 V R/W Address IPSBAR + 0x000 Figure 8-1. IPS Base Address Register (IPSBAR) Table 8-2. IPSBAR Field Description Bits Name Description 31–30 BA Base address. Defines the base address of the 1-Gbyte internal peripheral space. This is the starting address for the IPS registers when the valid bit is set. 29–1 — Reserved, should be cleared. 0 V Valid.
Register Descriptions The physical base address programmed in both copies of the RAMBAR is typically the same value; however, they can be programmed to different values. By definition, the base address must be a 0-modulo-size value.
Register Descriptions For details on the processor's view of the local SRAM memories, see Section 5.3.1, “SRAM Base Address Register (RAMBAR).” 8.4.3 Core Reset Status Register (CRSR) The CRSR contains a bit for two of the reset sources to the CPU. A bit set to 1 indicates the last type of reset that occurred. The CRSR is updated by the control logic when the reset is complete. Only one bit is set at any one time in the CRSR. The register reflects the cause of the most recent reset.
Register Descriptions periodic execution of a core watchdog servicing sequence. If this periodic servicing action does not occur, the timer times out, resulting in a watchdog timer interrupt or a hardware reset, as programmed, by CWCR[CWRI]. If the timer times out and the core watchdog transfer acknowledge enable bit (CWCR[CWTA]) is set, a watchdog timer interrupt is asserted.
Register Descriptions Field 7 6 CWE CWRI 5 3 CWT[2:0] Reset 2 1 0 CWTA CWTAVAL CWTIC 0000_0000 R/W R/W Address IPSBAR + 0x011 Figure 8-4. Core Watchdog Control Register (CWCR) Table 8-5. CWCR Field Description Bits Name 7 CWE Core watchdog enable. 0 SWT disabled. 1 SWT enabled. 6 CWRI Core watchdog reset/interrupt select. 0 If a time-out occurs, the CWT generates an interrupt to the processor core.
Internal Bus Arbitration 8.4.5 Core Watchdog Service Register (CWSR) The software watchdog service sequence must be performed using the CWSR as a data register to prevent a CWT time-out. The service sequence requires two writes to this data register: first a write of 0x55 followed by a write of 0xAA. Both writes must be performed in this order prior to the CWT time-out, but any number of instructions or accesses to the CWSR can be executed between the two writes.
Internal Bus Arbitration “back door” to SRAM and Flash SRAM1 MPARK RAMBAR CPU M0 DMA M2 Internal Bus Master M1 FEC EIM MARB Internal Modules SDRAMC M3 Figure 8-6.
Internal Bus Arbitration 8.5.1 Overview The basic functionality is that of a 4-port, pipelined internal bus arbitration module with the following attributes: • • • • • • The master pointed to by the current arbitration pointer may get on the bus with zero latency if the address phase is available. All other requesters face at least a one cycle arbitration pipeline delay in order to meet bus timing constraints on address phase hold.
Internal Bus Arbitration If no masters are requesting, the arbitration unit must “park”, pointing at one of the masters. There are two possibilities, park the arbitration unit on the last active master, or park pointing to the highest priority master. Setting MPARK[PRK_LAST] causes the arbitration pointer to be parked on the highest priority master. In round-robin mode, programming the timeout enable and lockout bits MPARK[13,11:8] will have no effect on the arbitration. 8.5.2.
Internal Bus Arbitration Table 8-7. MPARK Field Description Bits Name 31–26 — 25 M2_P_EN DMA bandwith control enable 0 disable the use of the DMA's bandwidth control to elevate the priority of its bus requests. 1 enable the use of the DMA's bandwidth control to elevate the priority of its bus requests. 24 BCR24BIT Enables the use of 24 bit byte count registers in the DMA module 0 DMA BCRs function as 16 bit counters. 1 DMA BCRs function as 24 bit counters.
System Access Control Unit (SACU) NOTE The M1_PRTY field should not be set for a priority higher than third (default). 8.6 System Access Control Unit (SACU) This section details the functionality of the System Access Control Unit (SACU) which provides the mechanism needed to implement secure bus transactions to the address space mapped to the internal modules. 8.6.1 Overview The SACU supports the traditional model of two privilege levels: supervisor and user.
System Access Control Unit (SACU) It should be noted that while the bus does not implement the concept of reference type (code versus data) and only supports the user/supervisor privilege level, the reference type attribute is supported by the system bus. Accordingly, the access checking associated with both privilege level and reference type is performed in the IPS controller using the attributes associated with the reference from the system bus.
System Access Control Unit (SACU) Table 8-8. SACU Register Memory Map (continued) IPSBAR Offset [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] 0x028 PACR4 — PACR5 PACR6 0x02c PACR7 — PACR8 — 0x030 GPACR0 GPACR1 — — 0x034 — — — — 0x038 — — — — 0x03C — — — — 8.6.3.1 Master Privilege Register (MPR) The MPR specifies the access privilege level associated with each bus master in the platform.
System Access Control Unit (SACU) modules only support operand reads and writes. Each PACR follows the format illustrated in Figure 8-9. For a list of PACRs and the modules that they control, refer to Table 8-12. 7 Field 6 LOCK1 4 3 ACCESS_CTRL1 Reset 2 LOCK0 0 ACCESS_CTRL0 0000_0000 R/W R/W Address IPSBAR + 0x24 + Offset Figure 8-9. Peripheral Access Control Register (PACRn) Table 8-10.
System Access Control Unit (SACU) Table 8-12. Peripheral Access Control Registers (PACRs) (continued) Modules Controlled IPSBAR Offset Name ACCESS_CTRL1 ACCESS_CTRL0 0x027 PACR3 UART2 — 0x028 PACR4 I 2C QSPI 0x029 — — — 0x02a PACR5 DTIM0 DTIM1 0x02b PACR6 DTIM2 DTIM3 0x02c PACR7 INTC0 INTC1 0x02d — — — 0x02e PACR8 FEC0 — At reset, these on-chip modules are configured to have only supervisor read/write access capabilities.
System Access Control Unit (SACU) Table 8-13. Grouped PeripheralAccess Control Register (GPACR) Field Descriptions Bits Name 7 LOCK 6–4 — 3–0 Description This bit, once set, prevents subsequent writes to the GPACR. Any attempted write to the GPACR generates an error termination and the contents of the register are not affected. Only a system reset clears this flag. Reserved, should be cleared. ACCESS_CTRL This 4-bit field defines the access control for the given memory region.
System Access Control Unit (SACU) Table 8-15.
Chapter 9 Clock Module The clock module allows the MCF5282 to be configured for one of several clocking methods. Clocking modes include internal phase-locked loop (PLL) clocking with either an external clock reference or an external crystal reference supported by an internal crystal amplifier. The PLL can also be disabled and an external oscillator can be used to clock the device directly. The clock module contains: • • • • • 9.
Low-power Mode Operation 9.2.2 1:1 PLL Mode In 1:1 PLL mode, the PLL synthesizes a frequency equal to the external clock input reference frequency. The post divider is not active. 9.2.3 External Clock Mode In external clock mode, the PLL is bypassed, and the external clock is applied to EXTAL. The resulting operating frequency is equal to the external clock frequency. 9.3 Low-power Mode Operation This subsection describes the operation of the clock module in low-power and halted modes of operation.
Block Diagram There is also a fast wakeup option for quickly enabling the system clocks during stop recovery. This eliminates the wakeup recovery time but at the risk of sending a potentially unstable clock to the system. To prevent a non-locked PLL frequency overshoot when using the fast wakeup option, change the RFD divisor to the current RFD value plus one before entering stop mode. In external clock mode, there are no wakeup periods for oscillator startup or PLL lock. 9.
Signal Descriptions CLKMOD[1:0] RSTOUT STPMD LOCKS LOCK DETECT LOCK LOLRE TO RESET MODULE PLLMODE LOCEN LOCRE LOSS OF CLOCK DETECT REFERENCE CLOCK PHASE AND FREQUENCY DETECT LOCS CHARGE PUMP FILTER VCO RFD[2:0] SCALED PLL CLOCK OUT PLLSEL DISCLK MDF[2:0] CLKOUT ÷ MFD (4–18) PLL CLOCK OUT Figure 9-2. PLL Block Diagram 9.5 Signal Descriptions The clock module signals are summarized in Table 9-2 and a brief description follows.
Memory Map and Registers 9.5.2 XTAL This output is an internal oscillator connection to the external crystal. 9.5.3 CLKOUT This output reflects the internal system clock. 9.5.4 CLKMOD[1:0] These inputs are used to select the clock mode during chip configuration. 9.5.5 RSTOUT The RSTOUT pin is asserted by one of the following: • • 9.6 Internal system reset signal FRCRSTOUT bit in the reset control status register (RCR); see Section 28.4.1, “Reset Control Register (RCR).
Memory Map and Registers 9.6.2 Register Descriptions This subsection provides a description of the clock module registers. 9.6.2.1 Synthesizer Control Register (SYNCR) Field 15 14 13 12 11 10 9 8 LOLRE MFD2 MFD1 MFD0 LOCRE RFD2 RFD1 RFD0 Reset 0010_0001 R/W Field R/W 7 6 5 4 3 2 1 0 LOCEN DISCLK FWKUP — STPMD1 STPMD0 — — Reset 0000_0000 R/W R/W Address R R/W R IPSBAR + 0x0012_0000 Figure 9-3. Synthesizer Control Register (SYNCR) Table 9-4.
Memory Map and Registers Table 9-4. SYNCR Field Descriptions (continued) Bit(s) Name Description 14–12 MFD Multiplication Factor Divider. Contain the binary value of the divider in the PLL feedback loop. The MFD[2:0] value is the multiplication factor applied to the reference frequency. When MFD[2:0] are changed or the PLL is disabled in stop mode, the PLL loses lock. In 1:1 PLL mode, MFD[2:0] are ignored, and the multiplication factor is one.
Memory Map and Registers Table 9-4. SYNCR Field Descriptions (continued) Bit(s) Name Description 5 FWKUP Fast wakeup determines when the system clocks are enabled during wakeup from stop mode.
Memory Map and Registers Table 9-5. SYNSR Field Descriptions Bit(s) Name Description 7 PLLMODE Clock mode bit. The PLLMODE bit is configured at reset and reflects the clock mode as shown in Table 9-6. 1 PLL clock mode 0 External clock mode 6 PLLSEL PLL select. Configured at reset and reflects the PLL mode as shown in Table 9-6. 1 Normal PLL mode 0 1:1 PLL mode 5 PLLREF PLL reference. Configured at reset and reflects the PLL reference source in normal PLL mode as shown in Table 9-6.
Functional Description Table 9-5. SYNSR Field Descriptions (continued) Bit(s) Name Description 2 LOCS Sticky indication of whether a loss-of-clock condition has occurred at any time since exiting reset in normal PLL and 1:1 PLL modes. LOCS = 0 when the system clocks are operating normally. LOCS = 1 when system clocks have failed due to a reference failure or PLL failure.
Functional Description Table 9-7. Clock Out and Clock In Relationships PLL Options 1 System Clock Mode Normal PLL clock mode fsys = fref × 2(MFD + 2)/2RFD 1:1 PLL clock mode fsys = fref External clock mode fsys = fref 1 fref = input reference frequency fsys = CLKOUT frequency MFD ranges from 0 to 7. RFD ranges from 0 to 7. CAUTION XTAL must be tied low in external clock mode when reset is asserted. If it is not, clocks could be suspended indefinitely.
Functional Description 3. Write the MFD value from step 1 to the SYNCR. 4. Monitor the LOCK flag in SYNSR. When the PLL achieves lock, write the RFD value from step 1 to the RFD field of the SYNCR. This changes the system clocks frequency to the required frequency. NOTE Keep the maximum system clock frequency below the limit given in the Electrical Characteristics. 9.7.4 PLL Operation In PLL mode, the PLL synthesizes the system clocks.
Functional Description The feedback clock comes from one of the following: • • • CLKOUT in 1:1 PLL mode VCO output divided by two if CLKOUT is disabled in 1:1 PLL mode VCO output divided by the MFD in normal PLL mode When the frequency of the feedback clock equals the frequency of the reference clock, the PLL is frequency-locked. If the falling edge of the feedback clock lags the falling edge of the reference clock, the PFD pulses the UP signal.
Functional Description frequency is six times the reference frequency. The presence of the MFD in the loop allows the PLL to perform frequency multiplication, or synthesis. In 1:1 PLL mode, the MFD is bypassed, and the effective multiplication factor is one. 9.7.4.5 PLL Lock Detection The lock detect logic monitors the reference frequency and the PLL feedback frequency to determine when frequency lock is achieved. Phase lock is inferred by the frequency relationship, but is not guaranteed.
Functional Description Start with Tight Lock Criteria Loss of Lock Detected Set Tight Lock Criteria and Notify System of Loss of Lock Condition Reference Count Reference Count ≠ Feedback Count ≠ Feedback Count Count N Reference Cycles and Compare Number of Feedback Cycles Elapsed Reference Count = Feedback Count = N In Same Count/Compare Sequence Lock Detected.
Functional Description In external clock mode, the PLL cannot lock. Therefore, a loss of lock condition cannot occur, and the LOLRE bit has no effect. 9.7.4.8 Loss of Clock Detection The LOCEN bit in the SYNCR enables the loss of clock detection circuit to monitor the input clocks to the phase and frequency detector (PFD). When either the reference or feedback clock frequency falls below the minimum frequency, the loss of clock circuit sets the sticky LOCS flag in the SYNSR.
Functional Description A special loss-of-clock condition occurs when both the reference and the PLL fail. The failures may be simultaneous, or the PLL may fail first. In either case, the reference clock failure takes priority and the PLL attempts to operate in SCM. If successful, the PLL remains in SCM until the next reset. If the PLL cannot operate in SCM, the system remains static until the next reset. Both the reference and the PLL must be functioning properly to exit reset. 9.7.4.
Functional Description NRM NRM NRM 0 0 0 Off On 0 Lose lock 0 0 0 Off On 1 Lose lock 0 0 0 On On 0 MODE Out NRM Lose reference clock or no lock regain Stuck Lose reference clock, regain NRM ‘LK 1 ‘LC Block LOCKS from being cleared No lock regain Unstable NRM 0–>‘L K 0–>1 ‘LC Block LOCKS until lock regained Lose reference clock or no f.b.
Functional Description NRM NRM NRM NRM NRM NRM 1 0 0 Off Off 0 Lose lock, f.b. clock, reference clock 1 0 0 Off On 0 Lose lock, f.b. clock 1 0 0 Off On 1 Lose lock, f.b. clock 1 0 0 On On 0 1 0 0 On On 1 1 0 1 On On X — — — MODE Out NRM No regain Stuck Regain NRM No f.b. clock or lock regain Stuck Lose reference clock SCM 0 0 Regain f.b. clock Unstable NRM 0–>‘L K 0–>1 ‘LC No f.b.
Functional Description NRM 1 1 0 On On 0 NRM NRM X Lose lock, f.b.
Functional Description SCM 1 0 0 On On 1 — — Lose reference clock MODE Out SCM 0 0 LOCS PLL Action During Stop LOCK Expected PLL Action at Stop LOCKSS FWKUP OSC MODE In LOCEN LOCRE LOLRE PLL Table 9-10. Stop Mode Operation (Sheet 5 of 5) Comments 1 SCM Note: PLL = PLL enabled during STOP mode. PLL = On when STPMD[1:0] = 00 or 01 OSC = Oscillator enabled during STOP mode.
Functional Description 9-22 MCF5282 User’s Manual MOTOROLA
Chapter 10 Interrupt Controller Modules This section details the functionality for the MCF5282 interrupt controllers (INTC0, INTC1).
68K/ColdFire Interrupt Architecture Overview correct operation, the ColdFire requires that, once asserted, the interrupt source remain asserted until explicitly disabled by the interrupt service routine. During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode and then fetches an 8-bit vector from the interrupt controller.
68K/ColdFire Interrupt Architecture Overview 10.1.1 Interrupt Controller Theory of Operation To support the interrupt architecture of the 68K/ColdFire programming model, the combined 63 interrupt sources are organized as 7 levels, with each level supporting up to 9 prioritized requests. Consider the priority structure within a single interrupt level (from highest to lowest priority) as shown in Table 10-1. Table 10-1.
68K/ColdFire Interrupt Architecture Overview The decoded priority levels from all the interrupt controllers are logically summed together and the highest enabled interrupt request is then encoded into a 3-bit priority level that is sent to the processor core during this prioritization phase. 10.1.1.3 Interrupt Vector Determination Once the core has sampled for pending interrupts and begun interrupt exception processing, it generates an interrupt acknowledge cycle (IACK).
Memory Map 10.2 Memory Map The register programming model for the interrupt controllers is memory-mapped to a 256-byte space. In the following discussion, there are a number of program-visible registers greater than 32 bits in size. For these control fields, the physical register is partitioned into two 32-bit values: a register “high” (the upper longword) and a register “low” (the lower longword). The nomenclature H and L is used to reference these values.
Register Descriptions Table 10-3.
Register Descriptions 31 16 Field INT[63:48] Reset 0000_0000_0000_0000 R/W R 15 0 Field INT[47:32] Reset 0000_0000_0000_0000 R/W R IPSBAR + 0xC00, 0xD00 Figure 10-1. Interrupt Pending Register High (IPRHn) Table 10-4. IPRHn Field Descriptions Bits Name Description 31–0 INT Interrupt pending. Each bit corresponds to an interrupt source. The corresponding IMRHn bit determines whether an interrupt condition can generate an interrupt.
Register Descriptions 10.3.2 Interrupt Mask Register (IMRHn, IMRLn) The IMRHn and IMRLn registers are each 32 bits in size and provide a bit map for each interrupt to allow the request to be disabled (1 = disable the request, 0 = enable the request). The IMRn is set to all ones by reset, disabling all interrupt requests. The IMRn can be read and written. A write that sets bit 0 of the IMR forces the other 63 bits to be set, disabling all interrupt sources, and providing a global mask-all capability. .
Register Descriptions Table 10-7. IMRLn Field Descriptions Bits Name Description 31–1 INT_MASK Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRLn bit determines whether an interrupt condition can generate an interrupt. The corresponding IPRLn bit reflects the state of the interrupt signal even if the corresponding IMRLn bit is set. 0 The corresponding interrupt source is not masked 1 The corresponding interrupt source is masked 0 MASKALL Mask all interrupts.
Register Descriptions . 31 16 Field INTFRCL[31:16] Reset 0000_0000_0000_0000 R/W R 15 1 Field INTFRCL[16:1] Reset 0000_0000_0000_0000 R/W R 0 — IPSBAR + 0xC14, 0xD14 Figure 10-6. Interrupt Force Register Low (INTFRCLn) Table 10-9. INTFRCLn Field Descriptions Bits 31–1 0 Name Description INTFRC Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes.
Register Descriptions 10.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn) Each time an IACK is performed, the interrupt controller responds with the vector number of the highest priority source within the level being acknowledged. In addition to providing the vector number directly for the byte-sized IACK read, this 8-bit register is also loaded with information about the interrupt level and priority being acknowledged.
Register Descriptions 7 Field 6 5 — 3 2 IL Reset 0 IP 0000_0000 R/W R/W (Read only for ICRn1-ICRn7) Address See Table 10-2 and Table 10-3 for register offsets Figure 10-9. Interrupt Control Register (ICRnx) Table 10-12. ICRnx Field Descriptions Bits Name Description 7–6 — Reserved, should be cleared. 5–3 IL Interrupt level. Indicates the interrupt level assigned to each interrupt input. 2–0 IP Interrupt priority.
Register Descriptions Table 10-13.
Register Descriptions Table 10-13.
Register Descriptions Table 10-14.
Prioritization Between Interrupt Controllers This interrupt controller design also supports the concept of a software IACK. A software IACK is a useful concept that allows an interrupt service routine to determine if there are other pending interrupts so that the overhead associated with interrupt exception processing (including machine state save/restore functions) can be minimized.
Low-Power Wakeup Operation 10.5 Low-Power Wakeup Operation The System Control Module (SCM) contains an 8-bit low-power interrupt control register (LPICR) used explicitly for controlling the low-power stop mode. This register must explicitly be programmed by software to enter low-power mode. Each interrupt controller provides a special combinatorial logic path to provide a special wake-up signal to exit from the low-power stop mode.
Low-Power Wakeup Operation 10-18 MCF5282 User’s Manual MOTOROLA
Chapter 11 Edge Port Module (EPORT) 11.1 Introduction The edge port module (EPORT) has seven external interrupt pins, IRQ7–IRQ1. Each pin can be configured individually as a level-sensitive interrupt pin, an edge-detecting interrupt pin (rising edge, falling edge, or both), or a general-purpose input/output (I/O) pin. See Figure 11-1.
Interrupt/General-Purpose I/O Pin Descriptions NOTE The low-power interrupt control register (LPICR) in the System Control Module specifies the interrupt level at or above which is needed to bring the device out of a low-power mode. Table 11-1.
Memory Map and Registers 11.4 Memory Map and Registers This subsection describes the memory map and register structure. 11.4.1 Memory Map Refer to Table 11-2 for a description of the EPORT memory map. The EPORT has an IPSBAR offset for base address of 0x0013_0000. Table 11-2.
Memory Map and Registers 11.4.2.1 EPORT Pin Assignment Register (EPPAR) 15 Field 14 13 EPPA7 12 11 EPPA6 10 9 EPPA5 Reset 8 7 EPPA4 6 5 EPPA3 4 3 EPPA2 2 EPPA1 1 0 — 0000_0000_0000_0000 R/W R/W Address R IPSBAR + 0x0013_0000, 0x0013_0001 Figure 11-2. EPORT Pin Assignment Register (EPPAR) Table 11-3. EPPAR Field Descriptions Bit(s) Name Description 15–2 EPPAx EPORT pin assignment select fields.
Memory Map and Registers Table 11-4. EPDD Field Descriptions Bit(s) Name Description 7–1 EPDDx Setting any bit in the EPDDR configures the corresponding pin as an output. Clearing any bit in EPDDR configures the corresponding pin as an input. Pin direction is independent of the level/edge detection configuration. Reset clears EPDD7-EPDD1. To use an EPORT pin as an external interrupt request source, its corresponding bit in EPDDR must be clear.
Memory Map and Registers Table 11-6. EPDR Field Descriptions Bit(s) Name Description 7–1 EPDx Edge port data bits. Data written to EPDR is stored in an internal register; if any pin of the port is configured as an output, the bit stored for that pin is driven onto the pin. Reading EDPR returns the data stored in the register. Reset sets EPD7-EPD1. 0 — 11.4.2.5 Reserved, should be cleared.
Memory Map and Registers Table 11-8. EPFR Field Descriptions Bit(s) Name Description 7–1 EPFx Edge port flag bits. When an EPORT pin is configured for edge triggering, its corresponding read/write bit in EPFR indicates that the selected edge has been detected. Reset clears EPF7-EPF1. Bits in this register are set when the selected edge is detected on the corresponding pin. A bit remains set until cleared by writing a 1 to it. Writing 0 has no effect.
Memory Map and Registers 11-8 MCF5282 User’s Manual MOTOROLA
Chapter 12 Chip Select Module This chapter describes the MCF5282 chip select module, including the operation and programming model of the chip select registers, which include the chip select address, mask, and control registers. NOTE Unless otherwise noted, in this chapter, “clock” refers to the CLKOUT used for the bus. 12.
Chip Select Module Signals Table 12-2 shows the interaction of the byte-enable/byte-write enables with related signals. Table 12-2.
Chip Select Operation 12.3 Chip Select Operation Each chip select has a dedicated set of registers for configuration and control. • • • Chip select address registers (CSARn) control the base address of the chip select. See Section 12.4.1.1. Chip select mask registers (CSMRn) provide 16-bit address masking and access control. See Section 12.4.1.2. Chip select control registers (CSCRn) provide port size and burst capability indication, wait-state generation, and automatic acknowledge generation features.
Chip Select Operation Table 12-3. Accesses by Matches in CSARs and DACRs Number of CSCR Matches Number of DACR Matches Type of Access 0 0 External 1 0 Defined by CSAR Multiple 0 External, burst-inhibited, 32-bit 0 1 Defined by DACRs 1 1 Undefined Multiple 1 Undefined 0 Multiple Undefined 1 Multiple Undefined Multiple Multiple Undefined 12.3.1.1 8-, 16-, and 32-Bit Port Sizing Static bus sizing is programmable through the port size bits, CSCR[PS]. See Section 12.4.1.
Chip Select Registers CS[6:1] can be used. At reset, the port size function of the external boot chip select is determined by the logic levels of the inputs on D[19:18]. Table 12-4 and Table 12-4 list the various reset encodings for the configuration signals multiplexed with D[19:18]. Table 12-4.
Chip Select Registers Table 12-5. Chip Select Registers (continued) IPSBAR Offset [31:24] [23:16] [15:8] [7:0] 0x00_00AC Reserved1 Chip select control register—bank 3 (CSCR3) [p. 12-8] 0x00_00B0 Chip select address register—bank 4 (CSAR4) [p. 12-6] Reserved1 0x00_00B4 Chip select mask register—bank 4 (CSMR4) [p. 12-7] 0x00_00B8 Reserved1 Chip select control register—bank 4 (CSCR4) [p. 12-8] 0x00_00BC Chip select address register—bank 5 (CSAR5) [p.
Chip Select Registers Table 12-6. CSARn Field Description Bits 15–0 Name Description BA Base address. Defines the base address for memory dedicated to chip select CS[6:0]. BA is compared to bits 31–16 on the internal address bus to determine if chip select memory is being accessed. 12.4.1.2 Chip Select Mask Registers (CSMR0–CSMR6) The CSMRs, Figure 12-3, are used to specify the address mask and allowable access types for the respective chip selects. .
Chip Select Registers Table 12-7. CSMRn Field Descriptions (continued) Bits 5–1 Name Description C/I, SC, Address space mask bits. These bits determine whether the specified accesses can occur to the SD, UC, address space defined by the BAM for this chip select.
Chip Select Registers Table 12-8. CSCRn Field Descriptions Bits Name 15–14 — 13–10 WS 9 — Reserved, should be cleared. 8 AA Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for accesses specified by the chip select address. 0 No internal TA is asserted. Cycle is terminated externally. 1 Internal TA is asserted as specified by WS.
Chip Select Registers 12-10 MCF5282 User’s Manual MOTOROLA
Chapter 13 External Interface Module (EIM) This chapter describes data-transfer operations, error conditions, and reset operations. Chapter 15, “Synchronous DRAM Controller Module,” describes DRAM cycles. NOTE: Unless otherwise noted, in this chapter, “clock” refers to the CLKOUT used for the bus. 13.
Bus Characteristics Table 13-1. ColdFire Bus Signal Summary (Continued) Signal Name 1 Description I/O CLKOUT Edge TA Transfer acknowledge I Rising TIP Transfer in progress O Rising TS Transfer start O Rising These signals change after the falling edge. In the Electrical Specifications, these signals are specified off of the rising edge because CLKIN is squared up internally. 13.3 Bus Characteristics The MCF5282 uses its system clock to generate CLKOUT.
Data Transfer Operation The address bus, write data, TS, and all attribute signals change on the rising edge of CLKOUT. Read data is latched into the MCF5282 on the rising edge of CLKOUT. The MCF5282 bus supports byte, word, and longword operand transfers and allows accesses to 8-, 16-, and 32-bit data ports.
Data Transfer Operation (configured in CSCR0–CSCR7) and DRAM block 0 and 1 address and control registers (configured in DACR0 and DACR1). If the driven address compares with one of the programmed chip selects or DRAM blocks, the appropriate chip select is asserted or the DRAM block is selected using the specifications programmed by the user in the respective configuration register.
Data Transfer Operation 3. The last clock of the bus cycle uses what would be an idle clock between cycles to provide hold time for address, attributes and write data. Figure 13-6 and Figure 13-8 show the basic read and write operations. 13.4.2 Data Transfer Cycle States The data transfer operation in the MCF5282 is controlled by an on-chip state machine. Each bus clock cycle is divided into two states. Even states occur when CLKOUT is high and odd states occur when CLKOUT is low.
Data Transfer Operation Table 13-3. Bus Cycle States (Continued) State S3 Cycle Read/write (skipped for fast termination) CLKOUT Low Read S4 All S5 The MCF5282 waits for TA assertion. If TA is not sampled as asserted before the rising edge of CLKOUT at the end of the first clock cycle, the MCF5282 inserts wait states (full clock cycles) until TA is sampled as asserted.
Data Transfer Operation System MCF5282 1. Set R/W to read 2. Place address on A[31:0] 3. Assert TIP, and SIZ[1:0] 4. Assert TS 5. Negate TS 1. 1. 1. Sample TA low and latch data Start next cycle Decode address and select the appropriate slave device. 2. Drive data on D[31:0] 3. Assert TA 1. Negate TA. 2. Stop driving D[31:0] Figure 13-5. Read Cycle Flowchart The read cycle timing diagram is shown in Figure 13-6.
Data Transfer Operation • In S4, the external device can stop driving data after the rising edge of CLKOUT. However data could be driven up to S5. • For a read cycle, the external device stops driving data between S4 and S5. States are described in Table 13-3. 13.4.4 Write Cycle During a write cycle, the MCF5282 sends data to the memory or to a peripheral device. The write cycle flowchart is shown in Figure 13-7. System MCF5282 1. Set R/W to write 2. Place address on A[31:0] 3.
Data Transfer Operation 13.4.5 Fast Termination Cycles Two clock cycle transfers are supported on the MCF5282 bus. In most cases, this is impractical to use in a system because the termination must take place in the same half-clock during which TS is asserted. As this is atypical, it is not referred to as the zero-wait-state case but is called the fast-termination case. Fast termination cycles occur when the external device or memory asserts TA less than one clock after TS is asserted.
Data Transfer Operation 13.4.6 Back-to-Back Bus Cycles The MCF5282 runs back-to-back bus cycles whenever possible. For example, when a longword read is started on a word-size bus, the processor performs two back-to-back word read accesses. Back-to-back accesses are distinguished by the continuous assertion of TIP throughout the cycle. Figure 13-11 shows a read back-to-back with a write.
Data Transfer Operation CSCRn[BSTR,BSTW]. A line access to a burst-inhibited region first accesses the MCF5282 bus encoded as a line access. The SIZ[1:0] encoding does not exceed the programmed port size. The address changes if internal termination is used but does not change if external termination is used, as shown in Figure 13-12 and Figure 13-13. 13.4.7.1 Line Transfers A line is a 16-byte-aligned, 16-byte value.
Data Transfer Operation Figure 13-13 shows timing when internal termination is used. S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 CLKOUT A[31:0] A[31:0], SIZ[1:0] R/W TIP TS CSn, BSn, OE Read D[31:0] Read Read Read TA Figure 13-13. Line Read Burst (2-1-1-1), Internal Termination Figure 13-14 shows a line access read with one wait state programmed in CSCRn to give the peripheral or memory more time to return read data.
Data Transfer Operation S0 S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 A[3:2] = 10 A[3:2] = 11 S6 S7 CLKOUT A[3:2] = 00 A[31:0] A[3:2] = 01 R/W TIP SIZ[1:0] Line Longword TS CSn, BSn, OE Read D[31:0] Read Read Read Fast Fast Fast TA Basic Figure 13-15. Line Read Burst-Inhibited, Fast Termination, External Termination 13.4.7.3 Line Write Bus Cycles Figure 13-16 shows a line access write with zero wait states.
Misaligned Operands Figure 13-17 shows a line burst write with one wait-state insertion. S0 S1 S2 S3 WS S4 S5 WS S6 S7 WS S8 S9 WS S10S11 CLKOUT A[31:0] R/W, TIP SIZ[1:0] TS CSn, OE, BSn Write D[31:0] Write Write Write TA Figure 13-17. Line Write Burst (3-2-2-2) with One Wait State Figure 13-18 shows a burst-inhibited line write. The external device executes a basic write cycle while determining that a line is being transferred.
Misaligned Operands misaligned at an odd address, and a longword is misaligned at an address not a multiple of four. Although the MCF5282 enforces no alignment restrictions for data operands (including program counter (PC) relative data addressing), additional bus cycles are required for misaligned operands. Instruction words and extension words (opcodes) must reside on word boundaries. Attempting to prefetch a misaligned instruction word causes an address error exception.
Misaligned Operands 13-16 MCF5282 User’s Manual MOTOROLA
Chapter 14 Signal Descriptions This chapter describes MCF5282 signals. It includes an alphabetical listing of signals that characterizes each signal as an input or output, defines its state at reset, and identifies whether a pull-up resistor should be used. Chapter 13, “External Interface Module (EIM),” describes how these signals interact. NOTE The terms ‘assertion’ and ‘negation’ are used to avoid confusion when dealing with a mixture of active-low and active-high signals.
Overview RSTI Reset Controller RSTO TCLK TMS/BKPT JTAG Port TDI/DSI TRST/DSCLK TEA 4 JTAG_EN TEST CLKMOD1 TDO/DSO PST[3:0] Chip Configuration Power Management RCON CLKMOD0 TA TS 4 External Interface Module OE DDATA[3:0] R/W VDDF TIP 32 D[31:0] SDRAM_CS[1:0] DIV EMAC VSTBY Chip Selects Edgeport IRQ[7:1] 64K SRAM System Control Module (SCM) 7 Flash Module 2-Kbyte D-Cache/I-Cache 24 A[23:0] CS[6:0] 4 ColdFire V2 Core Interrupt Controller 0 Interrupt Controller 1 2 DMA C
Overview Table 14-1 lists the MCF5282 signals grouped by functionality. NOTE: The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO will default to their GPIO functionality. Table 14-1. MCF5282 Signal Description Signal Name Abbreviation Function I/O Page External Memory Interface Address A[23:0] Define the address of external byte, word, longword, and 16-byte burst accesses. I/O 14-18 Data D[31:0] Data bus.
Overview Table 14-1. MCF5282 Signal Description (Continued) Signal Name Abbreviation Function I/O Page SDRAM write enable DRAMW Asserted to signify that a DRAM write cycle is underway. Negated to indicate a read cycle. O 14-21 SDRAM bank selects SDRAM_CS[1:0] Interface to the chip-select lines of the SDRAMs within a memory block. O 14-21 SDRAM clock enable SCKE SDRAM clock enable. O 14-21 Clock and Reset Signals Reset in RSTI Asserted to enter reset exception processing.
Overview Table 14-1. MCF5282 Signal Description (Continued) Signal Name Abbreviation Function I/O Page Receive data valid ERXDV Asserted to indicate that the PHY has valid nibbles present on the MII. I 14-24 Receive data 0 ERXD0 Ethernet input data transferred from the PHY to the media access controller (when ERXDV is asserted). I 14-24 Carrier receive sense ECRS Asserted to indicate that the transmit or receive medium is not idle.
Overview Table 14-1. MCF5282 Signal Description (Continued) Signal Name Abbreviation Function I/O Page Clear-to-send UCTS[1:0] Signals UART that it can begin data transmission. I 14-27 Request to send URTS[1:0] Automatic UART request to send outputs. O 14-27 General Purpose Timer Signals GPTA GPTA[3:0] Provide the external interface to the timer A functions. I/O 14-27 GPTB GPTB[3:0] Provide the external interface to the timer B functions.
Overview Table 14-1. MCF5282 Signal Description (Continued) Signal Name Abbreviation Function I/O Page Development serial output/Test data DSO/TDO Provides single-bit communication for debug module responses (DSO). Provides serial data port for outputting JTAG logic data (TDO). O 14-31 Test clock TCLK JTAG test logic clock. I 14-31 Debug data DDATA[3:0] Display captured processor addresses, data, and breakpoint status. O 14-32 Processor status outputs PST[3:0] Indicate core status.
Overview Table 14-2. MCF5282 Alphabetical Signal Index Abbreviation 14-8 Function I/O A[23:0] Define the address of external byte, word, longword, and 16-byte burst accesses. AN[0:3]/AN[W:Z] Direct analog input ANn, or multiplexed input ANx. AN[52:53]/MA[0:1] Direct analog input ANn, or multiplexed output MAn. MAn selects the output of the external multiplexer. AN[55:56]/ TRIG[1:2] Direct analog input ANn, or input TRIGn. TRIGn causes one of the two queues to execute.
Overview Table 14-2. MCF5282 Alphabetical Signal Index (Continued) Abbreviation Function I/O EMDIO Transfers control information between the external PHY and the media access controller. ERXCLK Provides a timing reference for ERXDV, ERXD[3:0], and ERXER. I ERXD[3:1] Contain the Ethernet input data transferred from the PHY to the media access controller (when ERXDV is asserted in MII mode).
Overview Table 14-2. MCF5282 Alphabetical Signal Index (Continued) Abbreviation 14-10 Function I/O QADC analog supply Supplies positive power to the ESD structures in the QADC pads. I QSPI_CLK Provides the serial clock from the QSPI. O QSPI_CS[3:0] Provide QSPI peripheral chip selects. O QSPI_DIN Provides serial data to the QSPI. I QSPI_DOUT Provides serial data from the QSPI. O R/W Indicates the direction of the data transfer on the bus. I/O RCON Reset configuration select.
Overview Table 14-2. MCF5282 Alphabetical Signal Index (Continued) Abbreviation Function I/O UTXD[2:0] Transmitter serial data outputs. O XTAL Internal oscillator connection to the external crystal. O Table 14-3.
Overview Table 14-3.
Overview Table 14-3.
Overview Table 14-3.
Overview Table 14-3.
Overview Table 14-3.
Overview listing of signals that do not default to a GPIO function. Table 14-4. Pin Reset States at Reset (Single-Chip Mode) Signal Reset I/O Clock and Reset Signals RSTI — I RSTO Low O EXTAL — I XTAL XTAL O CLKOUT CLKOUT O Debug Support Signals JTAG_EN — I DSCLK/TRST — I BKPT/TMS — I DSI/TDI — I DSO/TDO High O TCLK — I DDATA[3:0] DDATA{3:0] O PST[3:0] PST[3:0] O 14.1.
MCF5282 External Signals Table 14-5. Default Signal Functions After System Reset (External Boot Mode) (Continued) Signal Reset I/O TS High O TIP High O CS[6:0] High O 14.2 MCF5282 External Signals The bus signals provide the external bus interface to the MCF5282. 14.2.1 External Interface Module (EIM) Signals These signals are used for doing transactions on the external bus. 14.2.1.
MCF5282 External Signals these outputs act as the byte select signals that indicate valid data is to be latched or driven onto a byte lane when driven low. For SRAM or Flash devices, the BS[3:0] outputs should be connected to individual byte strobe signals. For SDRAM devices, the BS[3:0] should be connected to individual SDRAM DQM signals. Note that most SDRAMs associate DQM3 with the MSB, in which case BS3 is connected to the SDRAM's DQM3 input. These pins can also be configured as GPIO PJ[7:4]. 14.2.1.
MCF5282 External Signals Table 14-6. Transfer Size Encoding SIZ[1:0] Transfer Size 00 Longword 01 Byte 10 Word 11 16-byte line Note that for misaligned transfers, SIZ[1:0] indicate the size of each transfer. For example, if a longword access occurs at a misaligned offset of 0x1, a byte is transferred first (SIZ[1:0] = 01), a word is next transferred at offset 0x2 (SIZ[1:0] = 10), then the final byte is transferred at offset 0x4 (SIZ[1:0] = 01).
MCF5282 External Signals port size and burst-capability indication, wait-state generation, and internal/external termination. Reset clears all chip select programming; CS0 is the only chip select initialized out of reset. CS0 is also unique because it can function at reset as a global chip select that allows boot ROM to be selected at any defined address space.
MCF5282 External Signals 14.2.3 Clock and Reset Signals The clock and reset signals configure the MCF5282 and provide interface signals to the external system. 14.2.3.1 Reset In (RSTI) Asserting RSTI causes the MCF5282 to enter reset exception processing. When RSTI is recognized the address bus, data bus, SIZ, R/W, AS, and TS are three-stated. RSTO is asserted automatically when RSTI is asserted. 14.2.3.
MCF5282 External Signals 14.2.5 External Interrupt Signals 14.2.5.1 External Interrupts (IRQ[7:1]) These inputs are the external interrupt sources. See Chapter 11, “Edge Port Module (EPORT)” for more information on these interrupt sources and their corresponding registers. These pins are configured as GPIO PNQ[7:1] in single-chip mode. 14.2.6 Ethernet Module Signals The following signals are used by the Ethernet module for data and clock signals. 14.2.6.
MCF5282 External Signals This pin can also be configured as GPIO PEH5. 14.2.6.6 Collision (ECOL) The ECOL input is asserted upon detection of a collision and remains asserted while the collision persists. This signal is not defined for full-duplex mode. This pin can also be configured as GPIO PEH4. 14.2.6.7 Receive Clock (ERXCLK) The receive clock (ERXCLK) input provides a timing reference for ERXDV, ERXD[3:0], and ERXER. This pin can also be configured as GPIO PEH3. 14.2.6.
MCF5282 External Signals These pins can also be configured as GPIO PEL4. 14.2.6.13 Receive Data 1–3 (ERXD[3:1]) These pins contain the Ethernet input data transferred from the PHY to the media-access controller when ERXDV is asserted in MII mode operation. These pins can also be configured as GPIO PEL[3:1]. 14.2.6.14 Receive Error (ERXER) ERXER is an input signal which when asserted along with ERXDV signals that the PHY has detected an error in the current frame.
MCF5282 External Signals 14.2.8 FlexCAN Signals 14.2.8.1 FlexCAN Transmit (CANTX) Controller Area Network Transmit data output. This pin can also be configured as GPIO PAS2. 14.2.8.2 FlexCAN Receive (CANRX) Controller Area Network Transmit data input. This pin can also be configured as GPIO PAS3. 14.2.9 I2C Signals The I2C module acts as a two-wire, bidirectional serial interface between the MCF5282 and peripherals with an I2C interface (such as LCD controller, A-to-D converter, or D-to-A converter).
MCF5282 External Signals 14.2.10.2 Receive Serial Data Input (URXD[2:0]) URXD[2:0] are the receiver serial data inputs for the UART modules. Data received on these pins is sampled on the rising edge of the serial clock source lsb first. When the UART clock is stopped for power-down mode, any transition on this pin restarts it. The URXD[1:0] pins can be configured as GPIO ports PUA3 and PUA1.
MCF5282 External Signals 14.2.12 DMA Timer Signals This section describes the signals of the four DMA timer modules. 14.2.12.1 DMA Timer 0 Input (DTIN0) The DMA timer 0 input (DTIN0) can be programmed to cause events to occur in DMA timer 0. It can either clock the event counter or provide a trigger to the timer value capture logic. This pin can also be configured as GPIO PTD1, secondary function UCTS1, or secondary function UCTS0. 14.2.12.
MCF5282 External Signals 14.2.12.7 DMA Timer 3 Input (DTIN3) The DMA timer 3 input (DTIN3) can be programmed as an input that causes events to occur in DMA timer 3. This can either clock the event counter or provide a trigger to the timer value capture logic. This pin can also be configured as GPIO PTC3, secondary function URTS1, or secondary function URTS0. 14.2.12.8 DMA Timer 3 Output (DTOUT3) The programmable DMA timer output (DTOUT0) pulse or toggle on various timer events.
MCF5282 External Signals pin can also be configured as an output signal, MA0, to select the output of the external multiplexer. This pin can also be configured as GPIO PQA0. 14.2.13.6 QADC Analog Input (AN53/MA1) This PQA signal is the direct analog input AN53. When using external multiplexing this pin can also be configured as an output signal, MA1, to select the output of the external multiplexer. This pin can also be configured as GPIO PQA1. 14.2.13.
MCF5282 External Signals asserted-to-negated transition only while TMS is held high. TRST has an internal pull-up resistor so if it is not driven low, it defaults to a logic level of 1. If TRST is not used, it can be tied to ground or, if TCK is clocked, to VDD. Tying TRST to ground places the JTAG controller in test logic reset state immediately. Tying it to VDD causes the JTAG controller (if TMS is a logic level of 1) to eventually enter test logic reset state after 5 TCK clocks. 14.2.14.
MCF5282 External Signals 14.2.14.7 Debug Data (DDATA[3:0]) Debug data signals (DDATA[3:0]) display captured processor addresses, data and breakpoint status. These pins can also be configured as GPIO PDD[7:4]. 14.2.14.8 Processor Status Outputs (PST[3:0]) PST[3:0] outputs indicate core status, as shown below in Table 14-7. Debug mode timing is synchronous with the processor clock; status is unrelated to the current bus transfer. These pins can also be configured as GPIO PDD[3:0]. Table 14-7.
MCF5282 External Signals 14.2.16 Power and Reference Signals These signals provide system power, ground and references to the device. Multiple pins are provided for adequate current capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression. 14.2.16.1 QADC Analog Reference (VRH, VRL) These signals serve as the high (VRH) and low (VRL) reference potentials for the analog converter in the QADC. 14.2.16.
MCF5282 External Signals 14-34 MCF5282 User’s Manual MOTOROLA
Chapter 15 Synchronous DRAM Controller Module This chapter describes configuration and operation of the synchronous DRAM (SDRAM) controller. It begins with a general description and brief glossary, and includes a description of signals involved in DRAM operations. The remainder of the chapter describes the programming model and signal timing, as well as the command set required for synchronous operations.
Overview 15.1.2 Block Diagram and Major Components The basic components of the SDRAM controller are shown in Figure 15-1.
SDRAM Controller Operation • • Address multiplexing—Multiplexes addresses to allow column and row addresses to share pins. This allows glueless interface to SDRAMs. Data Generation—Controls the data input and data output transmission between the on-platform and off-platform data buses. 15.2 SDRAM Controller Operation By running synchronously with the system clock, SDRAM can (after an initial latency period) be accessed on every clock; 5-1-1-1 is a typical MCF5282 burst rate to the SDRAM.
SDRAM Controller Operation 15.2.1 DRAM Controller Signals Table 15-2 describes the behavior of DRAM signals in synchronous mode. Table 15-2. Synchronous DRAM Signal Connections Signal Description SRAS Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the SDRAM. SRAS should be connected to the corresponding SDRAM SRAS. SCAS Synchronous column address strobe. Indicates a valid column address is present and can be latched by the SDRAM.
SDRAM Controller Operation 15.2.2.1 DRAM Control Register (DCR) The DCR, shown in Figure 15-2, controls refresh logic. 15 Field 14 — 13 12 NAM COC 11 IS 10 9 8 0 RTIM RC Reset Uninitialized R/W R/W Addr IPSBAR + 0x040 Figure 15-2. DRAM Control Register (DCR) Table 15-4 describes DCR fields. Table 15-4. DCR Field Descriptions Bits Name 15-14 — Description Reserved, should be cleared. 13 NAM No address multiplexing. Some implementations require external multiplexing.
SDRAM Controller Operation 15.2.2.2 DRAM Address and Control Registers (DACR0/DACR1) The DACRn registers, shown in Figure 15-3, contain the base address compare value and the control bits for memory blocks 0 and 1 of the SDRAM controller. Address and timing are also controlled by bits in DACRn.
SDRAM Controller Operation Table 15-5. DACRn Field Descriptions (continued) Bit 10–8 Name Description CBM Command and bank MUX [2:0]. Because different SDRAM configurations cause the command and bank select lines to correspond to different addresses, these resources are programmable. CBM determines the addresses onto which these functions are multiplexed.
SDRAM Controller Operation 15.2.2.3 DRAM Controller Mask Registers (DMR0/DMR1) The DMRn, Figure 15-4, includes mask bits for the base address and for address attributes. 31 18 17 Field 9 BAM — Reset 8 7 WP — 6 5 4 3 2 1 0 C/I AM SC SD UC UD V Uninitialized 0 R/W R/W Addr IPSBAR + 0x04C (DMR0), 0x054 (DMR1) Figure 15-4. DRAM Controller Mask Registers (DMRn) Table 15-6 describes DMRn fields. Table 15-6.
SDRAM Controller Operation 15.2.3 General Synchronous Operation Guidelines To reduce system logic and to support a variety of SDRAM sizes, the DRAM controller provides SDRAM control signals as well as a multiplexed row address and column address to the SDRAM. 15.2.3.1 Address Multiplexing Table 15-7 shows the generic address multiplexing scheme for SDRAM configurations. All possible address connection configurations can be derived from this table.
SDRAM Controller Operation Table 15-8. MCF5282 to SDRAM Interface (8-Bit Port, 9-Column Address Lines) MCF5282 A17 A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 Pins Row 17 16 15 14 13 12 11 10 9 Column 0 1 2 3 4 5 6 7 8 SDRAM Pins 18 19 20 21 22 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 Table 15-9.
SDRAM Controller Operation Table 15-13. MCF5282 to SDRAM Interface (16-Bit Port, 8-Column Address Lines) MCF5282 A16 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 Pins Row 16 15 14 13 12 11 10 9 Column 1 2 3 4 5 6 7 8 SDRAM Pins 17 18 19 20 21 22 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 Table 15-14.
SDRAM Controller Operation Table 15-18. MCF5282 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines) MCF5282 Pins A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 Row 16 15 14 13 12 11 10 9 18 20 22 Column 1 2 3 4 5 6 7 8 17 19 21 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Table 15-19.
SDRAM Controller Operation Table 15-23. MCF5282 to SDRAM Interface (32-Bit Port, 12-Column Address Lines) MCF5282 Pins 15.2.3.2 A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A23 Row 15 14 13 12 11 10 9 17 19 21 23 Column 2 3 4 5 6 7 8 16 18 20 22 SDRAM Pins A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 SDRAM Byte Strobe Connections Figure 15-5 shows SDRAM connections for port sizes of 32, 16, or 8 bits.
SDRAM Controller Operation the port size of the associated SDRAM. The primary cycle of the transfer generates the ACTV and READ or WRITE commands; secondary cycles generate only READ or WRITE commands. As soon as the transfer completes, the PALL command is generated to prepare for the next access. Note that in synchronous operation, burst mode and address incrementing during burst cycles are controlled by the MCF5282 DRAM controller.
SDRAM Controller Operation CLKOUT A[31:0] Row Column Column Column Column SRAS tRP SCAS tCASL = 2 tRWL DRAMW D[31:0] SDRAM_CS[0] or [1] BS[3:0] ACTV NOP WRITE WRITE WRITE WRITE NOP PALL Figure 15-7. Burst Write SDRAM Access Accesses in synchronous burst page mode always cause the following sequence: 1. ACTV command 2. NOP commands to assure SRAS-to-SCAS delay (if CAS latency is 1, there are no NOP commands). 3.
SDRAM Controller Operation request flag. This refresh cycle includes a delay from any precharge to the auto-refresh command, the auto-refresh command, and then a delay until any ACTV command is allowed. Any SDRAM access initiated during the auto-refresh cycle is delayed until the cycle is completed. Figure 15-8 shows the auto-refresh timing. In this case, there is an SDRAM access when the refresh request becomes active.
SDRAM Controller Operation CLKOUT SRAS SCAS tRCD = 2 tRC = 6 DRAMW SDRAM_CS[0] or [1] SCKE (DCR[COC] = 0) PALL SELF SELFX SelfRefresh Active First Possible ACTV Figure 15-9. Self-Refresh Operation 15.2.4 Initialization Sequence Synchronous DRAMs have a prescribed initialization sequence. The DRAM controller supports this sequence with the following procedure: 1. SDRAM control signals are reset to idle state. Wait the prescribed period after reset before any action is taken on the SDRAMs.
SDRAM Controller Operation 15.2.4.1 Mode Register Settings It is possible to configure the operation of SDRAMs, namely their burst operation and CAS latency, through the SDRAM component’s mode register. CAS latency is a function of the speed of the SDRAM and the bus clock of the DRAM controller. The DRAM controller operates at a CAS latency of 1, 2, or 3. Although the MCF5282 DRAM controller supports bursting operations, it does not use the bursting features of the SDRAMs.
SDRAM Example CLKOUT A[31:0] SRAS, SCAS DRAMW D[31:0] SD_CS[1] or [0] MRS Figure 15-10. Mode Register Set (MRS) Command 15.3 SDRAM Example This example interfaces a 512K x 32-bit x 4 bank SDRAM component to a MCF5282 operating at 40 MHz. Table 15-25 lists design specifications for this example. Table 15-25.
SDRAM Example 15.3.1 SDRAM Interface Configuration To interface this component to the MCF5282 DRAM controller, use the connection table that corresponds to a 32-bit port size with 8 columns (Table 15-24). Two pins select one of four banks when the part is functional. Table 15-26 shows the proper hardware connections. Table 15-26.
SDRAM Example Accessible Memory SDRAM Component Bank 0 Bank 1 512 Kbyte 1 Mbyte Bank 2 512 Kbyte 1 Mbyte 512 Kbyte Bank 3 512 Kbyte 1 Mbyte 512 Kbyte 512 Kbyte 1 Mbyte 512 Kbyte 512 Kbyte Figure 15-12. SDRAM Configuration The DACRs should be programmed as shown in Figure 15-13.
SDRAM Example Table 15-28. DACR Initialization Values (continued) Bits Name Setting 3 IP 0 2–0 — Description Indicates precharge has not been initiated. Reserved. Don’t care. 15.3.4 DMR Initialization Again, in this example only the second 512-Kbyte block of each 1-Mbyte space is accessed in each bank. In addition, the SDRAM component is mapped only to readable and writable supervisor and user data. The DMRs have the following configuration.
SDRAM Example 15.3.5 Mode Register Initialization When DACR[IMRS] is set, a bus cycle initializes the mode register. If the mode register setting is read on A[10:0] of the SDRAM on the first bus cycle, the bit settings on the corresponding MCF5282 address pins must be determined while being aware of masking requirements. Table 15-30 lists the desired initialization setting: Table 15-30.
SDRAM Example 15.3.6 Initialization Code The following assembly code initializes the SDRAM example. Power-Up Sequence: move.w move.w move.l move.l move.l move.l #0x0026, d0//Initialize DCR d0, DCR #0xFF880300, d0 //Initialize DACR0 d0, DACR0 #0x00740075, d0//Initialize DMR0 d0, DMR0 Precharge Sequence: move.l move.l move.l move.l #0xFF880308, d0//Set DACR0[IP] d0, DACR0 #0xBEADDEED, d0//Write and value to memory location to init. precharge d0, 0xFF880000 Refresh Sequence: move.l move.
SDRAM Example MOTOROLA Chapter 15.
SDRAM Example 15-26 MCF5282 User’s Manual MOTOROLA
Chapter 16 DMA Controller Module This chapter describes the MCF5282 Direct Memory Access (DMA) controller module. It provides an overview of the module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail. NOTE The designation “n” is used throughout this section to refer to registers or signals associated with one of the four identical DMA channels: DMA0, DMA1, DMA2 or DMA3. 16.
Overview Channel 0 Channel 1 Channel 2 Internal Bus External Requests SAR0 SAR1 SAR2 SAR3 DAR0 DAR1 DAR2 DAR3 BCR0 BCR1 BCR2 BCR3 DCR0 DCR1 DCR2 DCR3 DSR0 DSR1 DSR2 DSR3 Channel Requests System Bus Address MUX MUX Control Read Data Bus Interrupts Channel Attributes Channel Enables Data Path Channel 3 System Bus Size Current Master Attributes Arbitration/ Control Data Path Control Write Data Bus Bus Interface Registered Bus Signals Figure 16-1.
DMA Request Control (DMAREQC) 16.2 DMA Request Control (DMAREQC) The DMAREQC register provides a software-controlled connection matrix for DMA requests. It logically routes DMA requests from the DMA timers and UARTs to the four channels of the DMA controller. Writing to this register determines the exact routing of the DMA request to the four channels of the DMA modules. If DCRn[EEXT] is set and the channel is idle, the assertion of the appropriate DREQn activates channel n.
DMA Transfer Overview 16.3 DMA Transfer Overview The DMA module can transfer data faster than the ColdFire core. The term “direct memory access” refers to a fast method of moving data within system memory (including memory and peripheral devices) with minimal processor intervention, greatly improving overall system performance. The DMA module consists of four independent, functionally equivalent channels, so references to DMA in this chapter apply to any of the channels.
DMA Controller Module Programming Model 16.4 DMA Controller Module Programming Model This section describes each internal register and its bit assignment. Note that modifying DMA control registers during a DMA transfer can result in undefined operation. Table 16-2 shows the mapping of DMA controller registers. Note the differences for the byte count registers depending on the value of MPARK[BCR24BIT]. See Section 8.5.3, “Bus Master Park Register (MPARK)” for further information. Table 16-2.
DMA Controller Module Programming Model 16.4.1 Source Address Registers (SAR0–SAR3) SARn, shown in Figure 16-4, contains the address from which the DMA controller requests data. 31 0 Field SAR Reset 0000_0000_0000_0000_0000_0000_0000_0000 R/W R/W Address IPSBAR + 0x100, 0x140, 0x180, 0x1C0 Figure 16-4. Source Address Registers (SARn) NOTE The backdoor enable bit must be set in both the core and SCM in order to enable backdoor accesses from the DMA to SRAM. See Section 8.4.
DMA Controller Module Programming Model NOTE The DMA does not maintain coherency with the MCF5282 cache. Therefore, DMAs should not transfer data to cacheable memory unless software is used to maintain the cache coherency. NOTE The DMA should not be used to write data to the UART transmit FIFO in cycle steal mode. When the UART interrupt is used as a DMA request it does not negate fast enough to get a single transfer. The UART transmit FIFO only has one entry so the data from the second byte would be lost.
DMA Controller Module Programming Model When a transfer sequence is initiated and BCRn[BCR] is not a multiple of 16, 4, or 2 when the DMA is configured for line, longword, or word transfers, respectively, DSRn[CE] is set and no transfer occurs. See Section 16.4.5, “DMA Status Registers (DSR0–DSR3).” 16.4.4 DMA Control Registers (DCR0–DCR3) DCRn, shown in Figure 16-8, is used for configuring the DMA controller module. Note that DCRn[AT] is available only if MPARK[BCR24BIT] is set. See Section 8.5.
DMA Controller Module Programming Model Table 16-3. DCRn Field Descriptions (continued) Bits Name Description 27–25 BWC Bandwidth control. Indicates the number of bytes in a block transfer. When the byte count reaches a multiple of the BWC value, the DMA releases the bus. For example, if BCR24BIT is 0, BWC is 001 (512 bytes or value of 0x0200), and BCR is 0x1000, the bus is relinquished after BCR values of 0x0E00, 0x0C00, 0x0A00, 0x0800, 0x0600, 0x0400, and 0x0200.
DMA Controller Module Programming Model Table 16-3. DCRn Field Descriptions (continued) Bits Name Description 15 AT AT is available only if MPARK[BCR24BIT] = 1. DMA acknowledge type. Controls whether acknowledge information is provided for the entire transfer or only the final transfer. 0 Entire transfer. DMA acknowledge information is displayed anytime the channel is selected as the result of an external request. 1 Final transfer (when BCR reaches zero).
DMA Controller Module Functional Description Table 16-4. DSRn Field Descriptions (continued) Bits Name 1 BSY 0 Description Busy 0 DMA channel is inactive. Cleared when the DMA has finished the last transaction. 1 BSY is set the first time the channel is enabled after a transfer is initiated. DONE Transactions done. Set when all DMA controller transactions complete, as determined by transfer count or error conditions. When BCR reaches zero, DONE is set when the final transfer completes successfully.
DMA Controller Module Functional Description • external request is initiated by asserting DREQn while DCRn[EEXT] is set. Note that multiple transfers will occur if DREQn is continuously asserted. Continuous mode (DCRn[CS] = 0)—After an internal or external request, the DMA continuously transfers data until BCRn reaches zero or a multiple of DCRn[BWC] or until DSRn[DONE] is set.
DMA Controller Module Functional Description 16.5.3 Channel Initialization and Startup Before a block transfer starts, channel registers must be initialized with information describing configuration, request-generation method, and the data block. 16.5.3.1 Channel Prioritization The four DMA channels are prioritized in ascending order (channel 0 having highest priority and channel 3 having the lowest) or in an order determined by DCRn[BWC].
DMA Controller Module Functional Description BCRn[BCR] must be loaded with the number of byte transfers to occur. It is decremented by 1, 2, 4, or 16 at the end of each transfer, depending on the transfer size. DSRn[DONE] must be cleared for channel startup. As soon as the channel has been initialized, it is started by writing a one to DCRn[START] or asserting DREQn, depending on the status of DCRn[EEXT].
DMA Controller Module Functional Description 16.5.4.2 Bandwidth Control Bandwidth control makes it possible to force the DMA off the bus to allow access to another device. DCRn[BWC] provides seven levels of block transfer sizes. If the BCRn decrements to a multiple of the decode of the BWC, the DMA bus request negates until the bus cycle terminates. If a request is pending, the arbiter may then pass bus mastership to another device.
DMA Controller Module Functional Description 16-16 MCF5282 User’s Manual MOTOROLA
Chapter 17 Fast Ethernet Controller (FEC) This chapter provides a feature-set overview, a functional block diagram, and transceiver connection information for both the 10 and 100 Mbps MII (Media Independent Interface), as well as the 7-wire serial interface. Additionally, detailed descriptions of operation and the programming model are included. 17.1 Overview The Ethernet Media Access Controller (MAC) is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks.
Modes of Operation • • Automatic internal flushing of the receive FIFO for runts (collision fragments) and address recognition rejects (no processor bus utilization) Address recognition — Frames with broadcast address may be always accepted or always rejected — Exact match for single 48-bit individual (unicast) address — Hash (64-bit hash) check of individual (unicast) addresses — Hash (64-bit hash) check of group (multicast) addresses — Promiscuous mode 17.
Modes of Operation 17.2.2.2 10 Mpbs 7-Wire Interface Operation The FEC supports a 7-wire interface as used by many 10 Mbps ethernet transceivers. The RCR[MII_MODE] bit controls this functionality. If this bit is deasserted, the MII mode is disabled and the 10 Mbps, 7-wire mode is enabled. 17.2.3 Address Recognition Options The address options supported are promiscuous, broadcast reject, individual address (hash or exact match), and multicast hash match.
FEC Top-Level Functional Diagram 17.3 FEC Top-Level Functional Diagram The block diagram of the FEC is shown below. The FEC is implemented with a combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE 802.3 standards.
Functional Description NOTE DMA references in this section refer to the FEC’s DMA engine. This DMA engine is for the transfer of FEC data only, and is not related to the DMA controller described in Chapter 16, “DMA Controller Module,” nor to the DMA timers described in Chapter 21, “DMA Timers (DTIM0–DTIM3).” The RAM is the focal point of all data flow in the Fast Ethernet Controller and is divided into transmit and receive FIFOs. The FIFO boundaries are programmable using the FRSR register.
Functional Description 17.4.1 Initialization Sequence This section describes which registers are reset due to hardware reset, which are reset by the FEC RISC, and what locations the user must initialize prior to enabling the FEC. 17.4.1.1 Hardware Controlled Initialization In the FEC, registers and control logic that generate interrupts are reset by hardware. A hardware reset deasserts output signals and resets general configuration bits. Other registers reset when the ECR[ETHER_EN] bit is cleared.
Functional Description Table 17-2. User Initialization (Before ECR[ETHER_EN]) (continued) Description MSCR (optional) Clear MIB_RAM (locations IPSBAR + 0x1200-0x12FC) FEC FIFO/DMA registers that require initialization are defined in Table 17-3. Table 17-3. FEC User Initialization (Before ECR[ETHER_EN]) Description Initialize FRSR (optional) Initialize EMRBR Initialize ERDSR Initialize ETDSR Initialize (Empty) Transmit Descriptor ring Initialize (Empty) Receive Descriptor ring 17.4.
Functional Description 17.4.5 Network Interface Options The FEC supports both an MII interface for 10/100 Mbps Ethernet and a 7-wire serial interface for 10 Mbps Ethernet. The interface mode is selected by the RCR[MII_MODE] bit. In MII mode (RCR[MII_MODE] = 1), there are 18 signals defined by the IEEE 802.3 standard and supported by the EMAC. These signals are shown in Table 17-5 below. Table 17-5.
Functional Description 17.4.6 FEC Frame Transmission The Ethernet transmitter is designed to work with almost no intervention from software. Once ECR[ETHER_EN] is asserted and data appears in the transmit FIFO, the Ethernet MAC is able to transmit onto the network. When the transmit FIFO fills to the watermark (defined by the TFWR), the MAC transmit logic will assert ETXEN and start transmitting the preamble (PA) sequence, the start frame delimiter (SFD), and then the frame information from the FIFO.
Functional Description 17.4.7 FEC Frame Reception The FEC receiver is designed to work with almost no intervention from the host and can perform address recognition, CRC checking, short frame checking, and maximum frame length checking. When the driver enables the FEC receiver by asserting ECR[ETHER_EN], it will immediately start processing receive frames. When ERXDV asserts, the receiver will first check for a valid PA/SFD header.
Functional Description 17.4.8 Ethernet Address Recognition The FEC filters the received frames based on destination address (DA) type — individual (unicast), group (multicast), or broadcast (all-ones group address). The difference between an individual address and a group address is determined by the I/G bit in the destination address field. A flowchart for address recognition on received frames is illustrated in the figures below.
Functional Description Accept/Reject Frame True Broadcast Addr ? False Receive Address Recognition False Receive Frame Set BC bit in RCV BD True Hash Match ? BC_REJ = 1 ? False True Receive Frame Set MC bit in RCV BD if multicast Exact Match ? True False Pause Frame True ? False PROM = 1 ? Reject Frame Flush from FIFO True Receive Frame Set M (Miss) bit in Rcv BD Set MC bit in Rcv BD if multicast Set BC bit in Rcv BD if broadcast False Reject Frame Flush from FIFO Receive Frame NOTES:
Functional Description Receive Address Recognition Group False Pause Address ? False Exact Match ? Hash Search Individual Table Receive Frame True True Receive Frame Reject Frame Flush from FIFO True True Receive Frame Hash Search Group Table Match ? Individual False True FCE ? False I/G Address ? Match ? False Receive Frame Reject Frame Flush from FIFO NOTES: FCE - field in RCR register (Flow Control Enable) I/G - Individual/Group bit in Destination Address (least significant bit in
Functional Description The effectiveness of the hash table declines as the number of addresses increases. The hash table registers must be initialized by the user. The CRC32 polynomial to use in computing the hash is: X 32 + X 26 + X 23 + X 22 + X 16 + X 12 + X 11 + X 10 + X 8 + X 7 + X 5 + X 4 + X 2 + X + 1 A table of example Destination Addresses and corresponding hash values is included below for reference. Table 17-7.
Functional Description Table 17-7.
Functional Description Table 17-7. Destination Address to 6-Bit Hash (continued) 48-bit DA 6-bit Hash (in hex) Hash Decimal Value 0d:ff:ff:ff:ff:ff 0x39 57 5d:ff:ff:ff:ff:ff 0x3a 58 7d:ff:ff:ff:ff:ff 0x3b 59 fd:ff:ff:ff:ff:ff 0x3c 60 dd:ff:ff:ff:ff:ff 0x3d 61 9d:ff:ff:ff:ff:ff 0x3e 62 bd:ff:ff:ff:ff:ff 0x3f 63 17.4.10 Full Duplex Flow Control Full-duplex flow control allows the user to transmit pause frames and to detect received pause frames.
Functional Description To transmit a pause frame, the FEC must operate in full-duplex mode and the user must assert flow control pause (TCR[TFC_PAUSE]). On assertion of transmit flow control pause (TCR[TFC_PAUSE]), the transmitter asserts TCR[GTS] internally. When the transmission of data frames stops, the EIR[GRA] (graceful stop complete) interrupt asserts. Following EIR[GRA] assertion, the pause frame is transmitted.
Functional Description Both internal and external loopback are configured using combinations of the LOOP and DRT bits in the RCR register and the FDEN bit in the TCR register. For both internal and external loopback set FDEN = 1. For internal loopback set RCR[LOOP] = 1 and RCR[DRT] = 0. ETXEN and ETXER will not assert during internal loopback.
Functional Description 17.4.14.1.4 Heartbeat Some transceivers have a self-test feature called “heartbeat” or “signal quality error.” To signify a good self-test, the transceiver indicates a collision to the FEC within 4 microseconds after completion of a frame transmitted by the Ethernet controller. This indication of a collision does not imply a real collision error on the network, but is rather an indication that the transceiver still seems to be functioning properly.
Programming Model 17.4.14.2.5 Truncation When the receive frame length exceeds 2047 bytes the frame is truncated and the TR bit is set in the receive BD. 17.5 Programming Model This section gives an overview of the registers, followed by a description of the buffers. The FEC is programmed by a combination of control/status registers (CSRs) and buffer descriptors. The CSRs are used for mode control and to extract global status information.
Programming Model Table 17-10.
Programming Model Table 17-11.
Programming Model Table 17-11.
Programming Model in the network or transceiver are HBERR, BABR, BABT, LC and RL. Interrupts resulting from internal errors are HBERR and UN. Some of the error interrupts are independently counted in the MIB block counters. Software may choose to mask off these interrupts since these errors will be visible to network management via the MIB counters.
Programming Model Table 17-12. EIR Field Descriptions (continued) Bits Name Description 28 GRA Graceful stop complete. This interrupt will be asserted for one of three reasons. Graceful stop means that the transmitter is put into a pause state after completion of the frame currently being transmitted. 1) A graceful stop, which was initiated by the setting of the TCR[GTS] bit is now complete. 2) A graceful stop, which was initiated by the setting of the TCR[TFC_PAUSE] bit is now complete.
Programming Model 17.5.4.2 Interrupt Mask Register (EIMR) The EIMR register controls which interrupt events are allowed to generate actual interrupts. All implemented bits in this CSR are read/write. This register is cleared upon a hardware reset. If the corresponding bits in both the EIR and EIMR registers are set, the interrupt will be signalled to the CPU. The interrupt signal will remain asserted until a 1 is written to the EIR bit (write 1 to clear) or a 0 is written to the EIMR bit.
Programming Model The RDAR register is cleared at reset and when ECR[ETHER_EN] is cleared. 31 25 Field — Reset 24 23 R_DES_ACTIVE 16 — 0000_0000_0000_0000 R/W R/W 15 0 Field — Reset 0000_0000_0000_0000 R/W R/W Address IPSBAR + 0x1010 Figure 17-6. Receive Descriptor Active Register (RDAR) Table 17-14. RDAR Field Descriptions Bits Name 31–25 — 24 23–0 Description Reserved, should be cleared. R_DES_ACTIVE Set to one when this register is written, regardless of the value written.
Programming Model 31 25 Field — Reset 24 23 X_DES_ACTIVE 16 — 0000_0000_0000_0000 R/W R/W 15 0 Field — Reset 0000_0000_0000_0000 R/W R/W Address IPSBAR + 0x1014 Figure 17-7. Transmit Descriptor Active Register (TDAR) Table 17-15. TDAR Field Descriptions Bits Name 31–25 — 24 23–0 Description Reserved, should be cleared. X_DES_ACTIVE Set to one when this register is written, regardless of the value written.
Programming Model Table 17-16. ECR Field Descriptions Bits Name Description 31-2 — 1 ETHER_EN When this bit is set, the FEC is enabled, and reception and transmission are possible. When this bit is cleared, reception is immediately stopped and transmission is stopped after a bad CRC is appended to any currently transmitted frame. The buffer descriptor(s) for an aborted transmit frame are not updated after clearing this bit.
Programming Model Table 17-17. MMFR Field Descriptions Bit Name Description 31–30 ST Start of frame delimiter. These bits must be programmed to 01 for a valid MII management frame. 29–28 OP Operation code. This field must be programmed to 10 (read) or 01 (write) to generate a valid MII management frame. A value of 11 will produce “read” frame operation while a value of 00 will produce “write” frame operation, but these frames will not be MII compliant. 27–23 PA PHY address.
Programming Model If the MMFR register is written while frame generation is in progress, the frame contents will be altered. Software should use the MII_STATUS register and/or the MII interrupt to avoid writing to the MMFR register while frame generation is in progress. 17.5.4.
Programming Model If the system clock is 25 MHz, programming this register to 0x0000_0005 will result in an EMDC frequency of 25 MHz * 1/10 = 2.5 MHz. A table showing optimum values for MII_SPEED as a function of system clock frequency is provided below. Table 17-19. Programming Examples for MSCR System Clock Frequency MII_SPEED (field in reg) EMDC frequency 25 MHz 0x5 2.5 MHz 33 MHz 0x7 2.36 MHz 40 MHz 0x8 2.5 MHz 50 MHz 0xA 2.5 MHz 66 MHz 0xD 2.5 MHz 17.5.4.
Programming Model 17.5.4.9 Receive Control Register (RCR) The RCR is programmed by the user. The RCR controls the operational mode of the receive block and should be written only when ECR[ETHER_EN] = 0 (initialization time). 31 27 26 Field 16 — MAX_FL Reset 0000_0101_1110_1110 R/W R/W 15 6 Field — Reset 5 4 3 2 1 0 FCE BC_REJ PROM MII_MODE DRT LOOP 0000_0000_0000_0001 R/W R/W Address IPSBAR + 0x1084 Figure 17-12. Receive Control Register (RCR) Table 17-21.
Programming Model Table 17-21. RCR Field Descriptions (continued) Bits Name Description 1 DRT Disable receive on transmit. 0 Receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half duplex mode). 1 Disable reception of frames while transmitting (normally used for half duplex mode). 0 LOOP Internal loopback. If set, transmitted frames are looped back internal to the device and the transmit output signals are not asserted.
Programming Model Table 17-22. TCR Field Descriptions Bits Name Description 31–5 — 4 RFC_PAUSE Receive frame control pause. This read-only status bit will be asserted when a full duplex flow control pause frame has been received and the transmitter is paused for the duration defined in this pause frame. This bit will automatically clear when the pause duration is complete. 3 TFC_PAUSE Transmit frame control pause. Transmits a PAUSE frame when asserted.
Programming Model 31 16 Field PADDR1 Reset Uninitialized R/W R/W 15 0 Field PADDR1 Reset Uninitialized R/W R/W Address IPSBAR + 0x10E4 Figure 17-14. Physical Address Low Register (PALR) Table 17-23. PALR Field Descriptions Bits Name 31–0 PADDR1 Description Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8) and 3 (bits 7:0) of the 6-byte individual address to be used for exact match, and the Source Address field in PAUSE frames. 17.5.4.
Programming Model Table 17-24. PAUR Field Descriptions BIts Name Description 31–16 PADDR2 Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address to be used for exact match, and the Source Address field in PAUSE frames. 15–0 TYPE Type field in PAUSE frames. These 16-bits are a constant value of 0x8808. 17.5.4.13 Opcode/Pause Duration Register (OPD) The OPD is read/write accessible.
Programming Model 31 16 Field IADDR1 Reset Uninitialized R/W R/W 15 0 Field IADDR1 Reset Uninitialized R/W R/W Address IPSBAR + 0x1118 Figure 17-17. Descriptor Individual Upper Address Register (IAUR) Table 17-26. IAUR Field Descriptions Bits Name Descriptions 31–0 IADDR1 The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
Programming Model Table 17-27. IALR Field Descriptions Bits Name Description 31–0 IADDR2 The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0. 17.5.4.16 Descriptor Group Upper Address (GAUR) The GAUR is written by the user.
Programming Model 31 16 Field GADDR2 Reset Uninitialized R/W R/W 15 0 Field GADDR2 Reset Uninitialized R/W R/W Address IPSBAR + 0x1124 Figure 17-20. Descriptor Group Lower Address Register (GALR) Table 17-29. GALR Field Descriptions Bits Name Description 31–0 GADDR2 The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. Bit 31 of GADDR2 contains hash index bit 31.
Programming Model Table 17-30. TFWR Field Descriptions Bits Name 31–2 — 1–0 X_WMRK Descriptions Reserved, should be cleared. Number of bytes written to transmit FIFO before transmission of a frame begins 0x 64 bytes written 10 128 bytes written 11 192 bytes written 17.5.4.19 FIFO Receive Bound Register (FRBR) The FRBR is an 8-bit register that the user can read to determine the upper address bound of the FIFO RAM.
Programming Model 17.5.4.20 FIFO Receive Start Register (FRSR) The FRSR is an 8-bit register programmed by the user to indicate the starting address of the receive FIFO. FRSR marks the boundary between the transmit and receive FIFOs. The transmit FIFO uses addresses from the start of the FIFO to the location four bytes before the address programmed into the FRSR. The receive FIFO uses addresses from FRSR to FRBR inclusive. The FRSR register is initialized by hardware at reset.
Programming Model 31 16 Field R_DES_START Reset Uninitialized R/W R/W 15 2 Field 1 R_DES_START Reset 0 — Uninitialized R/W R/W Address IPSBAR + 0x1180 Figure 17-24. Receive Descriptor Ring Start Register (ERDSR) Table 17-33. ERDSR Field Descriptions Bits 31–2 1–0 Name Descriptions R_DES_START Pointer to start of receive buffer descriptor queue. — Reserved, should be cleared. 17.5.4.22 Transmit Buffer Descriptor Ring Start (ETSDR) The ETSDR is written by the user.
Programming Model Table 17-34. ETDSR Field Descriptions Bits Name 31–2 Descriptions X_DES_START Pointer to start of transmit buffer descriptor queue. 1–0 — Reserved, should be cleared. 17.5.4.23 Receive Buffer Size Register (EMRBR) The EMRBR is a 9-bit register programmed by the user. The EMRBR register dictates the maximum size of all receive buffers. Note that because receive frames will be truncated at 2k-1 bytes, only bits 10–4 are used.
Buffer Descriptors 17.6 Buffer Descriptors This section provides a description of the operation of the driver/DMA via the buffer descriptors. It is followed by a detailed description of the receive and transmit descriptor fields. 17.6.1 Driver/DMA Operation with Buffer Descriptors The data for the FEC frames must reside in memory external to the FEC. The data for a frame is placed in one or more buffers.
Buffer Descriptors provided by the driver in one of the transmit buffers. The Ethernet MAC can append the Ethernet CRC to the frame. Whether the CRC is appended by the MAC or by the driver is determined by the TC bit in the transmit BD which must be set by the driver. The driver (TxBD software producer) should set up Tx BDs in such a way that a complete transmit frame is given to the hardware at once.
Buffer Descriptors field for the end of frame buffer will be written with the length of the entire frame, not just the length of the last buffer. For simplicity the driver may assign the default receive buffer length to be large enough to contain an entire frame, keeping in mind that a malfunction on the network or out of spec implementation could result in giant frames.
Buffer Descriptors Table 17-36. Receive Buffer Descriptor Field Definitions Word Location Field Name Description Offset + 0 Bit 15 E Empty. Written by the FEC (=0) and user (=1). 0 The data buffer associated with this BD has been filled with received data, or data reception has been aborted due to an error condition. The status and length fields have been updated as required. 1 The data buffer associated with this BD is empty, or reception is currently in progress.
Buffer Descriptors Table 17-36. Receive Buffer Descriptor Field Definitions (continued) 1 Word Location Field Name Description Offset + 0 Bit 1 OV Overrun. Written by the FEC. A receive FIFO overrun occurred during frame reception. If this bit is set, the other status bits, M, LG, NO, CR, and CL lose their normal meaning and will be zero. This bit is valid only if the L-bit is set. Offset + 0 Bit 0 TR Will be set if the receive frame is truncated (frame length > 2047 bytes).
Buffer Descriptors 15 Offset + 0 14 R 13 TO1 W 12 TO2 11 10 L TC Offset + 2 9 8 7 6 5 4 3 2 1 0 ABC Data Length Offset + 4 Tx Data Buffer Pointer - A[31:16] Offset + 6 Tx Data Buffer Pointer - A[15:0] Figure 17-28. Transmit Buffer Descriptor (TxBD) Table 17-37. Transmit Buffer Descriptor Field Definitions Word Location Field Name Description Offset + 0 Bit 15 R Ready. Written by the FEC and the user. 0 The data buffer associated with this BD is not ready for transmission.
Buffer Descriptors Table 17-37. Transmit Buffer Descriptor Field Definitions (continued) 1 Word Location Field Name Description Offset + 2 Bits [15:0] Data Length Data Length, written by user. Data length is the number of octets the FEC should transmit from this BD’s data buffer. It is never modified by the FEC. Bits [15:5] are used by the DMA engine, bits[4:0] are ignored.
Buffer Descriptors 17-52 MCF5282 User’s Manual MOTOROLA
Chapter 18 Watchdog Timer Module 18.1 Introduction The watchdog timer is a 16-bit timer used to help software recover from runaway code. The watchdog timer has a free-running down-counter (watchdog counter) that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown by servicing the watchdog. 18.2 Low-Power Mode Operation This subsection describes the operation of the watchdog module in low-power modes and halted mode of operation.
Block Diagram In halted mode with the WCR[HALTED] bit set, watchdog timer module operation stops. In halted mode with the WCR[HALTED] bit cleared, the watchdog timer continues to operate normally. When halted mode is exited, watchdog timer operation continues from the state it was in before entering halted mode, but any updates made in halted mode remain. 18.
Memory Map and Registers Table 18-2. Watchdog Timer Module Memory Map IPSBAR Offset 1 Bits 15–8 Access 1 Bits 7–0 0x0014_0000 Watchdog Control Register (WCR) S 0x0014_0002 Watchdog Modulus Register (WMR) S 0x0014_0004 Watchdog Count Register (WCNTR) S/U 0x0014_0006 Watchdog Service Register (WSR) S/U S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error.
Memory Map and Registers Table 18-3. WCR Field Descriptions Bit(s) Name 15–4 — 3 WAIT Wait mode bit. Controls the function of the watchdog timer in wait mode. Once written, the WAIT bit is not affected by further writes except in halted mode. Reset sets WAIT. 1 Watchdog timer stopped in wait mode 0 Watchdog timer not affected in wait mode 2 DOZE Doze mode bit. Controls the function of the watchdog timer in doze mode.
Memory Map and Registers Table 18-4. WMR Field Descriptions Bit(s) Name Description 15–0 WM Watchdog modulus. Contains the modulus that is reloaded into the watchdog counter by a service sequence. Once written, the WM[15:0] field is not affected by further writes except in halted mode. Writing to WMR immediately loads the new modulus value into the watchdog counter. The new value is also used at the next and all subsequent reloads. Reading WMR returns the value in the modulus register.
Memory Map and Registers Field 15 14 13 12 11 10 9 8 WS15 WS14 WS13 WS12 WS11 WS10 WS9 WS8 Reset 0000_0000 R/W R/W Field 7 6 5 4 3 2 1 0 WS7 WS6 WS5 WS4 WS3 WS2 WS1 WS0 Reset 0000_0000 R/W R/W Address IPSBAR + 0x0014_0006, 0x0014_0007 Figure 18-5.
Chapter 19 Programmable Interrupt Timer Modules (PIT0–PIT3) 19.1 Overview The programmable interrupt timer (PIT) is a 16-bit timer that provides precise interrupts at regular intervals with minimal processor intervention. The timer can either count down from the value written in the modulus register, or it can be a free-running down-counter. This device has four programmable interrupt timers, PIT0–PIT3. 19.
Low-Power Mode Operation 19.3 Low-Power Mode Operation This subsection describes the operation of the PIT modules in low-power modes and halted mode of operation. Low-power modes are described in the Power Management Module. Table 19-1 shows the PIT module operation in low-power modes, and how it can exit from each mode. NOTE The low-power interrupt control register (LPICR) in the System Control Module specifies the interrupt level at or above which the device can be brought out of a low-power mode.
Memory Map and Registers 19.5 Memory Map and Registers This subsection describes the memory map and register structure for PIT0–PIT3. 19.5.1 Memory Map Refer to Table 19-2 for a description of the memory map. This device has four programmable interrupt timers with the following IPSBAR offset for base address locations for each timer. PIT0: 0x0015_0000 PIT1: 0x0016_0000 PIT2: 0x0017_0000 PIT3: 0x0018_0000 Table 19-2.
Memory Map and Registers 19.5.2.1 PIT Control and Status Register (PCSR) 15 12 Field — Reset 9 8 PRE3 PRE2 PRE1 PRE0 R R/W 7 6 5 4 3 2 1 0 — DOZE HALTED OVW PIE PIF RLD EN Reset R/W 10 0000_0000 R/W Field 11 0000_0000 R R/W Address IPSBAR + 0x0015_0000 and 0x0015_0001 (PIT0); 0x0016_0000 and 0x0016_0001 (PIT1); 0x0017_0000 and 0x0017_0001 (PIT2); 0x0018_0000 and 0x0018_0001 (PIT3) Figure 19-2. PIT Control and Status Register (PCSR) Table 19-3.
Memory Map and Registers Table 19-3. PCSR Field Descriptions (continued) Bit(s) Name Description 6 DOZE Doze mode bit. The read/write DOZE bit controls the function of the PIT in doze mode. Reset clears DOZE. 0 PIT function not affected in doze mode 1 PIT function stopped in doze mode When doze mode is exited, timer operation continues from the state it was in before entering doze mode. 5 HALTED Halted mode bit. Controls the function of the PIT in halted mode. Reset clears HALTED.
Functional Description Field 15 14 13 12 11 10 9 8 PM15 PM14 PM13 PM12 PM11 PM10 PM9 PM8 Reset 1111_1111 R/W R/W Field 7 6 5 4 3 2 1 0 PM7 PM6 PM5 PM4 PM3 PM2 PM1 PM0 Reset 1111_1111 R/W R/W Address IPSBAR + 0x0015_0002 and 0x0015_0003 (PIT0); 0x0016_0002 and 0x0016_0003 (PIT1); 0x0017_0002 and 0x0017_0003 (PIT2); 0x0018_0002 and 0x0018_0003 (PIT3) Figure 19-3. PIT Modulus Register (PMR) 19.5.2.
Functional Description When the OVW bit is set in PCSR, the counter can be directly initialized by writing to PMR without having to wait for the count to reach 0x0000. PIT CLOCK COUNTER 0x0002 0x0001 MODULUS 0x0000 0x0005 0x0005 PIF Figure 19-5. Counter Reloading from the Modulus Latch 19.6.2 Free-Running Timer Operation This mode of operation is selected when the RLD bit in PCSR is clear.
Interrupt Operation 19.7 Interrupt Operation Table 19-4 shows the interrupt request generated by the PIT. Table 19-4. PIT Interrupt Requests Interrupt Request Flag Enable Bit Timeout PIF PIE The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR.
Chapter 20 General Purpose Timer Modules (GPTA and GPTB) The MCF5282 has two 4-channel general purpose timer modules (GPTA and GPTB). Each consists of a 16-bit counter driven by a 7-stage programmable prescaler. A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter.
Block Diagram 20.2 Block Diagram CLK[1:0] System Clock SYNCx Pin PR[2:0] PACLK PACLK/256 PACLK/65536 Divide by 2 MUX Channel 3 Output Compare X Prescaler TCRE CxI GPTCNTH:GPTCNTL CxF Clear Counter 16-Bit Counter TOF Interrupt Logic TOI TE Interrupt Request Channel 0 16-Bit Comparator Edge Detect C0F IOS0 GPTC0H:GPTC0L 16-Bit Latch EDG0A OM:OL0 EDG0B TOV0 CH. 0 Capture PT0 LOGIC CH.
Low-Power Mode Operation 20.3 Low-Power Mode Operation This subsection describes the operation of the general purpose time module in low-power modes and halted mode of operation. Low-power modes are described in the Power Management Module. Table 3-1 shows the general purpose timer module operation in the low-power modes, and shows how this module may facilitate exit from each mode. Table 20-1.
Memory Map and Registers 20.4.2 GPTn3 The GPTn3 pin is for channel 3 input capture and output compare functions or for the pulse accumulator input. This pin is available for general-purpose I/O when not configured for timer functions. 20.4.3 SYNCn The SYNCn pin is for synchronization of the timer counter. It can be used to synchronize the counter with externally-timed or clocked events. A high signal on this pin clears the counter. 20.
Memory Map and Registers Table 20-3.
Memory Map and Registers Table 20-4. GPTIOS Field Descriptions Bit(s) Name 7–4 — 3–0 IOS Description Reserved, should be cleared. I/O select. The IOS[3:0] bits enable input capture or output compare operation for the corresponding timer channels. These bits are read anytime (always read 0x00), write anytime. 1 Output compare enabled 0 Input capture enabled 20.5.
Memory Map and Registers Table 20-6. GPTOC3M Field Descriptions Bit(s) Name 7–4 — 3–0 OC3M Description Reserved, should be cleared. Output compare 3 mask. Setting an OC3M bit configures the corresponding PORTTn pin to be an output. OC3Mn makes the GPT port pin an output regardless of the data direction bit when the pin is configured for output compare (IOSx = 1). The OC3Mn bits do not change the state of the PORTTnDDR bits. These bits are read anytime, write anytime.
Memory Map and Registers Table 20-8. GPTCNT Field Descriptions Bit(s) Name Description 15–0 CNTR Read-only field that provides the current count of the timer counter. To ensure coherent reading of the timer counter, such that a timer rollover does not occur between two back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. A write to GPTCNT may have an extra cycle on the first count because the write is not synchronized with the prescaler clock.
Memory Map and Registers Write GPTFLG1 Register Data Bit n CnF Clear CnF Flag TFFCA Read GPTCn Registers Write GPTCn Registers Figure 20-8. Fast Clear Flag Logic 20.5.7 GPT Toggle-On-Overflow Register (GPTTOV) 7 6 Field 5 4 3 0 — TOV Reset 0000_0000 R/W R/W Address IPSBAR + 0x1A_0008, 0x1B_0008 Figure 20-9. GPT Toggle-On-Overflow Register (GPTTOV) Table 20-10. GPTTOV Field Description Bit(s) Name 7–4 — 3–0 TOV Description Reserved, should be cleared.
Memory Map and Registers Table 20-11. GPTCL1 Field Descriptions Bit(s) Name Description 7–0 OMx/OLx Output mode/output level. Selects the output action to be taken as a result of a successful output compare on each channel. When either OMn or OLn is set and the IOSn bit is set, the pin is an output regardless of the state of the corresponding DDR bit. These bits are read anytime, write anytime.
Memory Map and Registers Table 20-13. GPTIE Field Descriptions Bit(s) Name Description 7–4 — Reserved, should be cleared. 3–0 CnI Channel interrupt enable. Enables the C[3:0]F flags in GPT flag register 1 to generate interrupt requests for each channel. These bits are read anytime, write anytime. 1 Corresponding channel interrupt requests enabled 0 Corresponding channel interrupt requests disabled 20.5.
Memory Map and Registers 20.5.12 GPT Flag Register 1 (GPTFLG1) 7 6 Field 5 4 3 — 0 CF Reset 0000_0000 R/W R/W Address IPSBAR + 0x1A_000E, 0x1B_000E Figure 20-14. GPT Flag Register 1 (GPTFLG1) Table 20-15. GPTFLG1 Field Descriptions Bit(s) Name 7–4 — 3–0 CnF Description Reserved, should be cleared. Channel flags. A channel flag is set when an input capture or output compare event occurs. These bits are read anytime, write anytime (writing 1 clears the flag, writing 0 has no effect).
Memory Map and Registers 20.5.14 GPT Channel Registers (GPTCn) 15 0 Field CCNT Reset 0000_0000_0000_0000 R/W R/W Address IPSBAR + 0x1A_0010, 0x1A_0012, 0x1A_0014, 0x1A_0016, 0x1B_0010, 0x1B_0012, 0x1B_0014, 0x1B_0016 Figure 20-16. GPT Channel[0:3] Register (GPTCn) Table 20-17.
Memory Map and Registers Table 20-18. GPTPACTL Field Descriptions (continued) Bit(s) Name Description 4 PEDGE Pulse accumulator edge. Selects falling or rising edges on the PAI pin to increment the counter. In event counter mode (PAMOD = 0): 1 Rising PAI edge increments counter 0 Falling PAI edge increments counter In gated time accumulation mode (PAMOD = 1): 1 Low PAI input enables divide-by-64 clock to pulse accumulator and trailing rising edge on PAI sets PAIF flag.
Memory Map and Registers Table 20-19. GPTPAFLG Field Descriptions Bit(s) Name Description 7–2 — 1 PAOVF Pulse accumulator overflow flag. Set when the 16-bit pulse accumulator rolls over from 0xFFFF to 0x0000. If the GPTPACTL[PAOVI] bit is also set, PAOVF generates an interrupt request. Clear PAOVF by writing a 1 to it. This bit is read anytime, write anytime. (Writing 1 clears the flag; writing 0 has no effect.
Memory Map and Registers 20.5.18 GPT Port Data Register (GPTPORT) 7 6 Field 5 4 3 0 — PORTT Reset 0000_0000 R/W R/W Address IPSBAR + 0x1A_001D, 0x1B_001D Figure 20-20. GPT Port Data Register (GPTPORT) Table 20-21. GPTPORT Field Descriptions Bit(s) Name Description 7–4 — 3–0 PORTT Reserved, should be cleared. GPT port input capture/output compare data. Data written to GPTPORT is buffered and drives the pins only when they are configured as general-purpose outputs.
Functional Description 20.6 Functional Description The General Purpose Timer (GPT) module is a 16-bit, 4-channel timer with input capture and output compare functions and a pulse accumulator. 20.6.1 Prescaler The prescaler divides the module clock by 1, 2, 4, 8, 16, 32, 64, or 128. The PR[2:0] bits in GPTSCR2 select the prescaler divisor. 20.6.2 Input Capture Clearing an I/O select bit, IOSn, configures channel n as an input capture channel.
Functional Description reset the GPT counter. A channel 3 output compare can reset the GPT counter even if the OC3/PAI pin is being used as the pulse accumulator input. An output compare overrides the data direction bit of the output compare pin but does not change the state of the data direction bit. Writing to the PORTTn bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch.
Functional Description 20.6.6 Gated Time Accumulation Mode Setting the PAMOD bit configures the PA for gated time accumulation operation. An active level on the PAI pin enables a divide-by-64 clock to drive the PA. The PA edge bit, PEDGE, selects low levels or high levels to enable the divide-by-64 clock. The trailing edge of the active level at the PAI pin sets the PA input flag, PAIF. The PA input interrupt enable bit, PAI, enables the PAIF flag to generate interrupt requests.
Functional Description To configure a pin for input capture: 1. Clear the pin’s IOS bit in GPTIOS. 2. Clear the pin’s DDR bit in PORTTnDDR. 3. Write to GPTCTL2 to select the input edge to detect. PORTTnDDR does not affect the data direction of an output compare pin. The output compare function overrides the data direction register but does not affect the state of the data direction register. To configure a pin for output compare: 1. 2. 3. 4. Set the pin’s IOS bit in GPTIOS.
Reset Table 20-23. GPT Settings and Pin Functions (continued) 1 2 3 4 5 6 1 1 1 X <> 0 0 Out OC action Output compare Pin driven by OC action(5) 1 0 1 X X 1 Out OC action/ Output compare Pin readable only if DDR = 0 6 OC3Dn (ch 3) 1 1 1 X X 1 Out OC action/ Output compare/ Pin driven by channel OC action and OC3Dn OC3Dn OC3Dn via channel 3 OC(6) (ch 3) When DDR set the pin as input (0), reading the data register will return the state of the pin.
Interrupts 20.8.1 GPT Channel Interrupts (CnF) A channel flag is set when an input capture or output compare event occurs. Clear a channel flag by writing a 1 to it. NOTE When the fast flag clear all bit, GPTSCR1[TFFCA], is set, an input capture read or an output compare write clears the corresponding channel flag. When a channel flag is set, it does not inhibit subsequent output compares or input captures 20.8.
Interrupts NOTE When the GPT channel 3 registers contain 0xFFFF and TCRE is set, TOF does not get set even though the GPT counter registers go from 0xFFFF to 0x0000. When the fast flag clear all bit, GPTSCR1[TFFCA], is set, any access to the GPT counter registers clears GPT flag register 2. When TOF is set, it does not inhibit future overflow events. MOTOROLA Chapter 20.
Interrupts 20-24 MCF5282 User’s Manual MOTOROLA
Chapter 21 DMA Timers (DTIM0–DTIM3) This chapter describes the configuration and operation of the four Direct Memory Access (DMA) timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit timers provide input capture and reference compare capabilities with optional signaling of events using interrupts or triggers. Additionally, programming examples are included.
DMA Timer Programming Model 0 7 15 System Clock (÷1 or ÷16) DMA Timer Mode Register (DTMRn) Prescaler Mode Bits DMA Timer Clock Generator DTINn clock Divider 31 Capture 0 DMA Timer Extended Mode Register (DTXMRn) 0 DMA Timer Counter Register (DTCNn) (contains incrementing value) Detection 31 0 31 DMA Timer Capture Register (DTCRn) (latches DTCN value when triggered by DTINn) 0 DMA Timer Reference Register (DTRRn) (reference value for comparison with DTCN) 0 7 DTOUTn IRQn DREQn DMA Time
DMA Timer Programming Model DTMRn[CLK] selects the clock input source. A programmable prescaler divides the clock input by values from 1 to 256. The prescaler output is an input to the 32-bit counter, DTCNn. 21.2.2 Capture Mode Each DMA timer has a 32-bit timer capture register (DTCRn) that latches the counter value when the corresponding input capture edge detector senses a defined DTINn transition.
DMA Timer Programming Model Table 21-1.
DMA Timer Programming Model Table 21-2 describes the DTMRn fields. Table 21-2. DTMRn Field Descriptions Bits Name Description 15–8 PS Prescaler value. The prescaler is programmed to divide the clock input (system clock/(16 or 1) or clock on DTINn) by values from 1 (PS = 0x00) to 256 (PS = 0xFF). 7–6 CE Capture edge. 00 Disable capture event output 01 Capture on rising edge only 10 Capture on falling edge only 11 Capture on any edge 5 OM Output mode.
DMA Timer Programming Model Table 21-3 describes the DTXMRn fields. Table 21-3. DTXMRn Field Descriptions Bits Name 7 DMAEN 6–1 — 0 MODE16 Description DMA request. Enables DMA request output on counter reference match or capture edge event. 0 DMA request disabled 1 DMA request enabled Reserved, should be cleared. Selects the increment mode for the timer.
DMA Timer Programming Model Table 21-4 describes the DTERn fields. Table 21-4. DTERn Field Descriptions Bits Name Description 7–2 — 1 REF Output reference event. The counter value, DTCNn equals the reference value, DTRRn. Writing a one to REF clears the event condition. Writing a zero has no effect. If REF = 1 and DTMRn[ORRI], DTXMRn[DMAEN] 00 No DMA request or interrupt asserted 01 No DMA request or interrupt asserted 10 Assert an interrupt 11 Assert a DMA request 0 CAP Capture event.
Using the DMA Timer Modules 31 0 Field CAP (32-bit capture counter value) Reset 0000_0000_0000_0000_0000_0000_0000_0000 R/W R Address IPSBAR + 0x408 (DTCR0); + 0x448 (DTCR1); + 0x488 (DTCR2); + 0x4C8 (DTCR3) Figure 21-6. DTCRn Bit Definitions 21.2.11 DMA Timer Counters (DTCNn) The current value of the 32-bit DTCNs can be read at anytime without affecting counting. Writing to DTCNn, shown in Figure 21-7, clears it.
Using the DMA Timer Modules NOTE DTINn may not be configured as a clock source when the timer capture mode is selected or indeterminate operation will result. • • • The 8-bit DTMRn[PS] prescaler value is set Using DTMRn[RST] the counter is cleared and started Timer events are either handled with an interrupt service routine, a DMA request or by a software polling mechanism 21.3.
Using the DMA Timer Modules move.l #0x0000,D0 move.l D0,TCN0 ;reset the counter to 0x0000 move.b #0x03,D0 move.b D0,TER0 ;writing ones to TER0[REF,CAP] ;clears the event flags move.w TMR0,D0 bset #0,D0 move.w D0,TMR0 ;save the contents of TMR0 while setting ;the 0 bit. This enables timer 0 and starts counting ;load the value back into the register, setting TMR0[RST] T0_LOOP move.b TER0,D1 btst #1,D1 beq T0_LOOP ;load TER0 and see if ;TER0[REF] has been set addi.l #1,D2 cmp.
Chapter 22 Queued Serial Peripheral Interface (QSPI) Module This chapter describes the queued serial peripheral interface (QSPI) module. Following a feature set overview is a description of operation including details of the QSPI’s internal RAM organization. The chapter concludes with the programming model and a timing diagram. 22.1 Overview The queued serial peripheral interface module provides a serial peripheral interface with queued transfer capability.
Module Description 22.3.1 Interface and Signals The module provides access to as many as 15 devices with a total of seven signals: QSPI_Dout, QSPI_Din, QSPI_CLK, QSPI_CS0, QSPI_CS1, QSPI_CS2, and QSPI_CS3. Peripheral chip-select signals, QSPI_CS[3:0], are used to select an external device as the source or destination for serial data transfer. Signals are asserted at a logic level corresponding to the value of the QSPI_CS[3:0] bits in the command RAM whenever a command in the queue is executed.
Operation Table 22-1. QSPI Input and Output Signals and Functions Signal Name Hi-Z or Actively Driven Function QSPI Data Output (QSPI_Dout) Configurable Serial data output from QSPI QSPI Data Input (QSPI_Din) N/A Serial data input to QSPI Serial Clock (QSPI_CLK) Actively driven Clock output from QSPI Peripheral Chip Selects (QSPI_CS[3:0]) Actively driven Peripheral selects 22.3.
Operation • • The completed queue pointer, QWR[CPTQP], points to the last command executed. The end queue pointer, QWR[ENDQP], points to the final command in the queue. The internal pointer is initialized to the same value as QWR[NEWQP]. During normal operation, the following sequence repeats: 1. The command pointed to by the internal pointer is executed. 2. The value in the internal pointer is copied into QWR[CPTQP]. 3. The internal pointer is incremented.
Operation 16 bytes of commands. A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR] and causes the value in QAR to increment. Correspondingly, a read at QDR returns the data in the RAM at the address specified by QAR[ADDR]. This also causes QAR to increment. A read access requires a single wait state. Relative Address Register 0x00 QTR0 0x01 QTR1 . . . . . . 0x0F QTR15 0x10 QRR0 0x11 QRR1 . . . . . . 0x1F QRR15 0x20 QCR0 0x21 QCR1 . . . . . .
Operation 22.4.1.2 Transmit RAM Data to be transmitted by the QSPI is stored in the transmit RAM segment located at addresses 0x0 to 0xF. The user normally writes 1 word into this segment for each queue command to be executed. The user cannot read data in the transmit RAM. Out-bound data must be written to transmit RAM in a right-justified format. The unused bits are ignored. The QSPI copies the data to its data serializer (shift register) for transmission.
Operation The desired QSPI_CLK baud rate is related to the system clock and QMR[BAUD] by the following expression: QMR[BAUD] = fSYS / [2 × (desired QSPI_CLK baud rate)] Table 22-2. QSPI_CLK Frequency as Function of System Clock and Baud Rate System Clock QMR [BAUD] 66.67 MHz 2 16.5 MHz 4 8.25 MHz 8 4.125 MHz 16 2.063 MHz 32 1.031 MHz 255 129.4 kHz 22.4.3 Transfer Delays The QSPI supports programmable delays for the QSPI_CS signals before and after a transfer.
Operation Delay after transfer = 32 × QDLYR[DTL] /fSYS (DT = 1) where QDLYR[DTL] has a range of 1–255. A zero value for DTL causes a delay-after-transfer value of 8192/fSYS. Standard delay after transfer = 17/fSYS (DT = 0) Adequate delay between transfers must be specified for long data streams because the QSPI module requires time to load a transmit RAM entry for transfer. Receiving devices need at least the standard delay between successive transfers.
Programming Model In wraparound mode, the QSPI cycles through the queue continuously, even while requesting interrupt service. QDLYR[SPE] is not cleared when the last command in the queue is executed. New receive data overwrites previously received data in the receive RAM. Each time the end of the queue is reached, QIR[SPIFE] is set. QIR[SPIF] is not automatically reset. If interrupt driven QSPI service is used, the service routine must clear QIR[SPIF] to abort the current request.
Programming Model 22.5.1 QSPI Mode Register (QMR) The QMR, shown in Figure 22-3, determines the basic operating modes of the QSPI module. Parameters such as QSPI_CLK polarity and phase, baud rate, master mode operation, and transfer size are determined by this register. The data output high impedance enable, DOHIE, controls the operation of QSPI_Dout between data transfers. When DOHIE is cleared, QSPI_Dout is actively driven between transfers. When DOHIE is set, QSPI_Dout assumes a high impedance state.
Programming Model Table 22-4. QMR Field Descriptions (continued) Bits Name Description 8 CPHA Clock phase. Defines the QSPI_CLK clock-phase. 0 Data captured on the leading edge of QSPI_CLK and changed on the following edge of QSPI_CLK. 1 Data changed on the leading edge of QSPI_CLK and captured on the following edge of QSPI_CLK. 7–0 BAUD Baud rate divider. The baud rate is selected by writing a value in the range 2–255. A value of zero disables the QSPI. A value of 1 is an invalid setting.
Programming Model Table 22-5 gives QDLYR field descriptions. Table 22-5. QDLYR Field Descriptions Bits Name Description 15 SPE QSPI enable. When set, the QSPI initiates transfers in master mode by executing commands in the command RAM. Automatically cleared by the QSPI when a transfer completes. The user can also clear this bit to abort transfer unless QIR[ABRTL] is set. The recommended method for aborting transfers is to set QWR[HALT]. 14–8 QCD QSPICLK delay.
Programming Model 22.5.4 QSPI Interrupt Register (QIR) Figure 22-7 shows the QIR register. 15 14 Field WCEFB ABRTB 13 12 — ABRT L 11 10 WCEFE ABRTE 9 8 — SPIFE Reset 0000_0000_0000_0000 R/W R/W Address 7 4 — 3 2 1 0 WCEF ABRT — SPIF IPSBAR + 0x34C Figure 22-7. QSPI Interrupt Register (QIR) Table 22-7 describes QIR fields. Table 22-7. QIR Field Descriptions BIts Name Description 15 WCEFB Write collision access error enable.
Programming Model The command and data RAM in the QSPI are indirectly accessible with QDR and QAR as 48 separate locations that comprise 16 words of transmit data, 16 words of receive data, and 16 bytes of commands. A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR]. This also causes the value in QAR to increment. Correspondingly, a read at QDR returns the data in the RAM at the address specified by QAR[ADDR]. This also causes QAR to increment.
Programming Model 22.5.7 Command RAM Registers (QCR0–QCR15) The command RAM is accessed using the upper byte of QDR. The QSPI cannot modify information in command RAM. There are 16 bytes in the command RAM. Each byte is divided into two fields. The chip select field enables external peripherals for transfer. The command field provides transfer operations. NOTE The command RAM is accessed only using the most significant byte of QDR and indirect addressing based on QAR[ADDR].
Programming Model NOTE In order to keep the chip selects asserted for all transfers, the QWR[CSIV] bit must be set to control the level that the chip selects return to after the first transfer. QSPICS[3:0] QS1 QSPI_CLK QS2 QSPI_DOUT QS3 QS5 QS4 QSPI_DIN Min Max 1T1 QS1: QSPICS to QSPI_CLK 20 ns QS2: QSPI_CLK to QSPI_DOUT VALID QS3: QSPI_CLK to QSPI_DOUT HOLD 0 ns QS4: QSPI_DIN to QSPI_CLK SETUP 10 ns QS5: QSPI_DIN to QSPI_CLK HOLD 10 ns 1 T1 is defined as the clock period in ns.
Programming Model 3. Write QIR with 0xD00F to enable write collision, abort bus errors, and clear any interrupts. 4. Write QAR with 0x0020 to select the first command RAM entry. 5. Write QDR with 0x7E00, 0x7E00, 0x7E00, 0x7E00, 0x7D00, 0x7D00, 0x7D00, 0x7D00, 0x7B00, 0x7B00, 0x7B00, 0x7B00, 0x7700, 0x7700, 0x7700, and 0x7700 to set up four transfers for each chip select. The chip selects are active low in this example. 6. Write QAR with 0x0000 to select the first transmit RAM entry. 7.
Programming Model 22-18 MCF5282 User’s Manual MOTOROLA
Chapter 23 UART Modules This chapter describes the use of the universal asynchronous receiver/transmitters (UARTs) implemented on the MCF5282 and includes programming examples. NOTE The designation “n” is used throughout this section to refer to registers or signals associated with one of the three identical UART modules: UART0, UART1, or UART2. 23.1 Overview The MCF5282 contains three independent UARTs. Each UART can be clocked by the system clock, eliminating the need for an external UART clock.
Serial Module Overview The serial communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter deriving an operating frequency from the system clock or an external clock using the timer pin. The transmitter converts parallel data from the CPU to a serial bit stream, inserting appropriate start, stop, and parity bits. It outputs the resulting stream on the channel transmitter serial data output (UTXDn). See Section 23.5.2.1, “Transmitter.
Register Descriptions 23.3 Register Descriptions This section contains a detailed description of each register and its specific function. Flowcharts in Section 23.5.6, “Programming,” describe basic UART module programming. The operation of the UART module is controlled by writing control bytes into the appropriate registers. Table 23-1 is a memory map for UART module registers. Table 23-1.
Register Descriptions Table 23-1. UART Module Memory Map (continued) IPSBAR Offset [31:24] UART0 UART1 UART2 0x23C 0x27C 0x2BC [23:16] [15:8] (Read) Do not access2 — (Write) UART output port bit reset command registers—(UOP0n3) [p. 23-15] — [7:0] 1 UMR1n, UMR2n, and UCSRn should be changed only after the receiver/transmitter is issued a software reset command. That is, if channel operation is not disabled, undesirable results may occur. 2 This address is for factory testing.
Register Descriptions Table 23-2 describes UMR1n fields. Table 23-2. UMR1n Field Descriptions Bits Name Description 7 RxRTS Receiver request-to-send. Allows the RTS output to control the CTS input of the transmitting device to prevent receiver overrun. If both the receiver and transmitter are incorrectly programmed for RTS control, RTS control is disabled for both. Transmitter RTS control is configured in UMR2n[TxRTS]. 0 The receiver has no effect on RTS.
Register Descriptions 23.3.2 UART Mode Register 2 (UMR2n) The UMR2n registers control UART module configuration. UMR2n can be read or written when the mode register pointer points to it, which occurs after any access to UMR1n. UMR2n accesses do not update the pointer. 7 Field 6 CM 5 4 3 TxRTS TxCTS 0 SB Reset 0000_0000 R/W R/W Address IPSBAR + 0x200 (UART0), 0x240 (UART1), 0x280 (UART2). After UMR1n is read or written, the pointer points to UMR2n. Figure 23-3.
Register Descriptions Table 23-3. UMR2n Field Descriptions (continued) Bits Name Description 3–0 SB Stop-bit length control. Selects the length of the stop bit appended to the transmitted character. Stop-bit lengths of 9/16th to 2 bits are programmable for 6–8 bit characters. Lengths of 1 1/16th to 2 bits are programmable for 5-bit characters.
Register Descriptions Table 23-4. USRn Field Descriptions (continued) Bits Name Description 5 PE Parity error. Valid only if RxRDY = 1. 0 No parity error occurred. 1 If UMR1n[PM] = 0x (with parity or force parity), the corresponding character in the FIFO was received with incorrect parity. If UMR1n[PM] = 11 (multidrop), PE stores the received address or data (A/D) bit. PE is valid only when RxRDY = 1. 4 OE Overrun error. Indicates whether an overrun occurs. 0 No overrun occurred.
Register Descriptions Table 23-5. UCSRn Field Descriptions Bits Name Description 7–4 RCS Receiver clock select. Selects the clock source for the receiver channel. 1101 Prescaled system clock 1110 DTIN divided by 16 1111 DTIN 3–0 TCS Transmitter clock select. Selects the clock source for the transmitter channel. 1101 Prescaled system clock 1110 DTIN divided by 16 1111 DTIN 23.3.5 UART Command Registers (UCRn) The UCRs, shown in Figure 23-6, supply commands to the UART.
Register Descriptions Table 23-6. UCRn Field Descriptions Bits Value Command Description 6–4 MISC Field (This field selects a single command.) 000 NO COMMAND — 001 RESET MODE Causes the mode register pointer to point to UMR1n. REGISTER POINTER 010 RESET RECEIVER Immediately disables the receiver, clears USRn[FFULL,RxRDY], and reinitializes the receiver FIFO pointer. No other registers are altered.
Register Descriptions Table 23-6. UCRn Field Descriptions (continued) Bits Value Command Description 1–0 RC (This field selects a single command) 00 NO ACTION TAKEN Causes the receiver to stay in its current mode. If the receiver is enabled, it remains enabled; if disabled, it remains disabled. 01 RECEIVER ENABLE If the UART module is not in multidrop mode (UMR1n[PM] ≠ 11), RECEIVER ENABLE enables the channel's receiver and forces it into search-for-start-bit state.
Register Descriptions Figure 23-8 shows UTBn. TB contains the character in the transmit buffer. 7 0 Field TB Reset 0000_0000 R/W Write only Address IPSBAR + 0x20C(UTB0), 0x24C(UTB1), 0x28C(UTB2) Figure 23-8. UART Transmit Buffer (UTBn) 23.3.8 UART Input Port Change Registers (UIPCRn) The UIPCRs, shown in Figure 23-9, hold the current state and the change-of-state for CTS.
Register Descriptions 23.3.9 UART Auxiliary Control Register (UACRn) The UACRs, shown in Figure 23-7, control the input enable. 7 1 Field — IEC Reset 0000_0000 R/W W Address 0 IPSBAR + 0x210 (UACR0), 0x250 (UACR1), 0x290 (UACR2) Figure 23-10. UART Auxiliary Control Register (UACRn) Table 23-8 describes UACRn fields. Table 23-8. UACRn Field Descriptions Bits Name 7–1 — 0 IEC Description Reserved, should be cleared. Input enable control.
Register Descriptions Table 23-9 describes UISRn and UIMRn fields. Table 23-9. UISRn/UIMRn Field Descriptions Bits Name Description 7 COS 6–3 — Reserved, should be cleared. 2 DB Delta break. 0 No new break-change condition to report. Section 23.3.5, “UART Command Registers (UCRn),” describes the RESET BREAK-CHANGE INTERRUPT command. 1 The receiver detected the beginning or end of a received break. Change-of-state. 0 UIPCRn[COS] is not selected.
Register Descriptions NOTE The minimum value that can be loaded on the concatenation of UBG1n with UBG2n is 0x0002. Both UBG1n and UBG2n are write-only and cannot be read by the CPU. 23.3.12 UART Input Port Register (UIPn) The UIPn registers, shown in Figure 23-14, show the current state of the CTS input. 7 1 Field 0 — CTS Reset 1111_1111 R/W R Address IPSBAR + 0x234 (UIP0), 0x274 (UIP1), 0x2B4 (UIP2) Figure 23-14. UART Input Port Register (UIPn) Table 23-10 describes UIPn fields.
Register Descriptions Table 23-11. UOP1/UOP0 Field Descriptions Bits Name 7–1 — 0 RTS 23-16 Description Reserved, should be cleared. Output port output. Controls assertion (UOP1)/negation (UOP0) of RTS output. 0 Not affected. 1 Asserts RTS with a write to UOP1. Negates RTS with a write to UOP0.
UART Module Signal Definitions 23.4 UART Module Signal Definitions Figure 23-16 shows both the external and internal signal groups. System Clock or External Clock (DTIN) Clock Source Generator UART Module Internal Bus Output Port URTS Input Port UCTS Control Interface to CPU Address Bus Internal Control Logic Data To Interrupt Controller or DMA Four-Character Receive Buffer URXD Two-Character Transmit Buffer UTXD External Interface Signals IRQ Figure 23-16.
Operation Table 23-12. UART Module Signals Signal Description Transmitter Serial UTXDn is held high (mark condition) when the transmitter is disabled, idle, or operating in the local Data Output loop-back mode. Data is shifted out on UTXDn on the falling edge of the clock source, with the least (UTXDn) significant bit (lsb) sent first. Receiver Serial Data Input (URXDn) Data received on URXDn is sampled on the rising edge of the clock source, with the lsb received first.
Operation • The system clock supplies an asynchronous clock source that is divided by 32 and then divided by the 16-bit value programmed in UBG1n and UBG2n. See Section 23.3.11, “UART Baud Rate Generator Registers (UBG1n/UBG2n).” The choice of DTIN or system clock is programmed in the UCSR.
Operation 66MHz Divider = ---------------------------- = 215 ( decimal ) = 00D6 ( hexadecimal ) [ 32 x 9600 ] therefore UBG1n = 0x00 and UBG2n = 0xD6. 23.5.1.2.2 External Clock An external source clock (DTINn) can be used as is or divided by 16. Externalclockfrequency Baudrate = ---------------------------------------------------------------[ 16or1 ] [ 16bitdivider ] 23.5.
Operation from the CPU to a serial bit stream on UTXDn. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The lsb is sent first. Data is shifted from the transmitter output on the falling edge of the clock source. After the stop bits are sent, if no new character is in the transmitter holding register, the UTXDn output remains high (mark condition) and the transmitter empty bit, USRn[TxEMP], is set.
Operation C1 in transmission C11 UTXDn C2 C3 C4 Break C6 Transmitter Enabled USRn[TxRDY] internal module select W2 W W C11 C2 C3 Start break W W W W W C4 Stop break C5 not transmitted C6 UCTSn3 URTSn4 Manually asserted by BIT-SET command Manually asserted 1 Cn = transmit characters 2 W = write 3 UMR2n[TxCTS] = 1 4 UMR2n[TxRTS] = 1 Figure 23-20. Transmitter Timing Diagram 23.5.2.2 Receiver The receiver is enabled through its UCRn, as described in Section 23.3.
Operation After the stop bit is detected, the receiver immediately looks for the next start bit. However, if a non-zero character is received without a stop bit (framing error) and URXD remains low for one-half of the bit period after the stop bit is sampled, the receiver operates as if a new start bit were detected.
Operation register and loaded into the top empty receiver holding register position of the FIFO. Thus, data flowing from the receiver to the CPU is quadruple-buffered. In addition to the data byte, three status bits, parity error (PE), framing error (FE), and received break (RB), are appended to each data character in the FIFO; OE (overrun error) is not appended. By programming the ERR bit in the channel’s mode register (UMR1n), status is provided in character or block modes.
Operation 23.5.3 Looping Modes The UART can be configured to operate in various looping modes as shown in Figure 23-21. These modes are useful for local and remote system diagnostic functions. The modes are described in the following paragraphs and in Section 23.3, “Register Descriptions.” The UART’s transmitter and receiver should be disabled when switching between modes. The selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted.
Operation • • UTXDn is held marking The receiver is clocked by the transmitter clock. The transmitter must be enabled, but the receiver need not be. 23.5.3.3 Remote Loop-Back Mode In remote loop-back mode, shown in Figure 23-24, the channel automatically transmits received data bit by bit on the UTXDn output. The local CPU-to-transmitter link is disabled. This mode is useful in testing receiver and transmitter operation of a remote channel. For this mode, the transmitter uses the receiver clock.
Operation Master Station A/D UTXDn ADD1 1 A/D A/D C0 ADD2 1 Transmitter Enabled USRn[TxRDY] internal module select UMR1n[PM] = 11 UMR1n[PT] = 1 C0 ADD 1 UMR1n[PT] = 0 ADD 2 UMR1n[PT] = 2 Peripheral Station URXDn A/D A/D 0 ADD1 1 A/D C0 A/D A/D ADD2 1 0 Receiver Enabled USRn[RxRDY] internal module select UMR1n[PM] = 11 UMR1n[PM] = 11 ADD 1 Status Data (C0) Status Data (ADD 2) Figure 23-25.
Operation detection, if 8-bit characters are not required, is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character. 23.5.5 Bus Operation This section describes bus operation during read, write, and interrupt acknowledge cycles to the UART module. 23.5.5.1 Read Cycles The UART module responds to reads with byte data. Reserved registers return zeros. 23.5.5.2 Write Cycles The UART module accepts write data as bytes.
Operation 23.5.6.1 23.5.6.1.1 Interrupt and DMA Request Initialization Setting up the UART to Generate Core Interrupts The list below gives the steps needed to properly initialize the UART to generate an interrupt request to the core. 1. Initialize ICRx register in the interrupt controller (ICR13 for UART0, ICR14 for UART1, and ICR15 for UART2) 2. Unmask appropriate bits in IMR in the interrupt controller (bits 13-15 for UART0-UART2 respectively) 3.
Operation Although the UART receive buffer is quadruple-buffered, the receiver shift register is still shifting its characters when the DMA request is ready to read its contents; therefore, the maximum number of data bytes read during a UART DMA request transfer is three. When the DMA is configured for cycle steal, only one character will be transferred on a DMA request. This mode should be used for DMA requests on FIFO not empty.
Operation ENABLE SERIAL MODULE ANY ERRORS ? SINIT Y N INITIATE: CHANNEL INTERRUPTS ENABLE RECEIVER CHK1 ASSERT REQUEST TO SEND CALL CHCHK SINITR SAVE CHANNEL STATUS RETURN Figure 23-26. UART Mode Programming Flowchart (Sheet 1 of 5) MOTOROLA Chapter 23.
Operation CHCHK CHCHK PLACE CHANNEL IN LOCAL LOOPBACK MODE ENABLE TRANSMITTER CLEAR STATUS WORD TxCHK N IS TRANSMITTER READY ? Y SNDCHR N WAITED TOO LONG ? Y SET TRANSMITTERNEVER-READY FLAG Y SET RECEIVERNEVER-READY FLAG SEND CHARACTER TO TRANSMITTER RxCHK N HAS CHARACTER BEEN RECEIVED ? Y N WAITED TOO LONG ? A B Figure 23-26.
Operation A B FRCHK RSTCHN HAVE FRAMING ERROR ? N SET FRAMING ERROR FLAG DISABLE TRANSMITTER RESTORE TO ORIGINAL MODE PRCHK HAVE PARITY ERROR ? N RETURN Y SET PARITY ERROR FLAG CHRCHK GET CHARACTER FROM RECEIVER SAME AS TRANSMITTED CHARACTER ? Y N SET INCORRECT CHARACTER FLAG B Figure 23-26. UART Mode Programming Flowchart (Sheet 3 of 5) MOTOROLA Chapter 23.
Operation INCH SIRQ ABRKI WAS IRQ CAUSED BY BEGINNING OF A BREAK ? N DOES CHANNEL A RECEIVER HAVE A CHARACTER ? N Y Y PLACE CHARACTER IN D0 CLEAR CHANGE-INBREAK STATUS BIT ABRKI1 HAS END-OF-BREAK IRQ ARRIVED YET ? N RETURN Y CLEAR CHANGE-INBREAK STATUS BIT REMOVE BREAK CHARACTER FROM RECEIVER FIFO REPLACE RETURN ADDRESS ON SYSTEM STACK AND MONITOR WARM START ADDRESS SIRQR RTE Figure 23-26.
Operation OUTCH IS TRANSMITTER READY ? N Y SEND CHARACTER TO TRANSMITTER RETURN Figure 23-26. UART Mode Programming Flowchart (Sheet 5 of 5) MOTOROLA Chapter 23.
Operation 23-36 MCF5282 User’s Manual MOTOROLA
Chapter 24 I2C Interface This chapter describes the MCF5282MCF523x I2C module, including I2C protocol, clock synchronization, and I2C programming model registers. It also provides extensive programming examples. 24.1 Overview I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications that require occasional communication between many devices over a short distance.
Interface Features • • Acknowledge bit generation/detection Bus-busy detection Figure 24-1 is a block diagram of the I2C module. Internal Bus IRQ Address Data Address Decode Data MUX Registers and ColdFire Interface I2C Frequency Divider Register (IFDR) I2C Control Register (I2CR) I2C Status Register (I2SR) Clock Control Start, Stop, and Arbitration Control I2C Data I/O Register (I2DR) I2C Address Register (IADR) In/Out Data Shift Register Address Compare Input Sync SCL SDA Figure 24-1.
I2C System Configuration 24.3 I2C System Configuration The I2C module uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. For I2C compliance, all devices connected to these two signals must have open drain or open collector outputs. The logic AND function is exercised on both lines with external pull-up resistors. Out of reset, the I2C default state is as a slave receiver.
I2C Protocol The slave whose address matches that sent by the master pulls SDA low at the ninth serial clock (D) to return an acknowledge bit. 3. Data transfer—When successful slave addressing is achieved, the data transfer can proceed (E) on a byte-by-byte basis in the direction specified by the R/W bit sent by the calling master. Data can be changed only while SCL is low and must be held stable while SCL is high, as Figure 24-2 shows. SCL is pulsed once for each data bit, with the msb being sent first.
I2C Protocol determines the relative priority of competing devices. A device loses arbitration if it sends logic high while another sends logic low; it immediately switches to slave-receive mode and stops driving SDA. In this case, the transition from master to slave mode does not generate a STOP condition. Meanwhile, hardware sets I2SR[IAL] to indicate loss of arbitration. 24.4.2 Clock Synchronization Since wire-AND logic is used, a high-to-low transition on SCL affects all devices connected to the bus.
Programming Model 24.5 Programming Model Table 24-1 lists the configuration registers used in the I2C interface. Table 24-1. I2C Interface Memory Map IPSBAR Offset [31:24] [23:16] [15:8] 0x300 I2C Address Register (I2ADR) [p. 24-6] Reserved 0x304 I2C Frequency Divider Register (I2FDR) [p. 24-7] Reserved 0x308 I2C Reserved 0x30C I2C Status Register (I2SR) [p. 24-9] Reserved 0x310 I2C Reserved Control Register (I2CR) [p. 24-8] Data I/O Register (I2DR) [p. 24-10] [7:0] 24.5.
Programming Model 24.5.2 I2C Frequency Divider Register (I2FDR) The I2FDR, shown in Figure 24-6, provides a programmable prescaler to configure the I2C clock for bit-rate selection. 7 Field 6 5 0 — IC Reset 0000_0000 R/W R/W Address IPSBAR + 0x304 Figure 24-6. I2C Frequency Divider Register (I2FDR) Table 24-3 describes I2FDR[IC]. Table 24-3. I2FDR Field Descriptions Bits Name 7–6 — Reserved, should be cleared. 5–0 IC I2C clock rate. Prescales the clock for bit-rate selection.
Programming Model 24.5.3 I2C Control Register (I2CR) The I2CR is used to enable the I2C module and the I2C interrupt. It also contains bits that govern operation as a slave or a master. Field 7 6 5 4 3 2 IEN IIEN MSTA MTX TXAK RSTA Reset 0000_0000 R/W R/W Address 1 0 — IPSBAR + 0x308 Figure 24-7. I2C Control Register (I2CR) Table 24-4 describes I2CR fields. Table 24-4. I2CR Field Descriptions Bits Name Description 7 IEN I2C enable.
Programming Model 24.5.4 I2C Status Register (I2SR) This I2SR contains bits that indicate transaction direction and status. Field 7 6 5 4 3 2 1 0 ICF IAAS IBB IAL — SRW IIF RXAK R/W R Reset R/W 1000_0001 R R R/W Address IPSBAR + 0x30C Figure 24-8. I2CR Status Register (I2SR) Table 24-5 describes I2SR fields. Table 24-5. I2SR Field Descriptions Bits Name 7 ICF 6 IAAS 5 IBB I2C bus busy bit. Indicates the status of the bus. 0 Bus is idle.
I2C Programming Examples Table 24-5. I2SR Field Descriptions (continued) Bits Name 1 IIF 0 Description I2C interrupt. Must be cleared by software by writing a zero to it in the interrupt routine. 0 No I2C interrupt pending 1 An interrupt is pending, which causes a processor interrupt request (if IIEN = 1).
I2C Programming Examples NOTE If I2SR[IBB] is set when the I2C bus module is enabled, execute the following code sequence before proceeding with normal initialization code. This issues a STOP command to the slave device, placing it in idle state as if it were just power-cycled on. I2CR = 0x0 I2CR = 0xA0 dummy read of I2DR I2SR = 0x0 I2CR = 0x0 24.6.2 Generation of START After completion of the initialization procedure, serial data can be transmitted by selecting the master transmitter mode.
I2C Programming Examples the interrupt routine. I2SR[ICF] is cleared either by reading from I2DR in receive mode or by writing to I2DR in transmit mode. Software can service the I2C I/O in the main program by monitoring IIF if the interrupt function is disabled. Polling should monitor IIF rather than ICF because that operation is different when arbitration is lost. When an interrupt occurs at the end of the address cycle, the master is always in transmit mode; that is, the address is sent.
I2C Programming Examples For a master receiver to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last data byte. This is done by setting I2CR[TXAK] before reading the next-to-last byte. Before the last byte is read, a STOP signal must be generated, as in the following example. MASR ENMASR NXMAR MOVE.B RXCNT,D0 SUBQ.L #1,D0 MOVE.B D0,RXCNT BEQ.S ENMASR MOVE.B RXCNT,D1 EXTB.L D1 SUBI.L #1,D1; BNE.S NXMAR LAMAR BSET.B #3,I2CR BRA NXMAR ;Decrease RXCNT BCLR.
I2C Programming Examples 24.6.7 Arbitration Lost If several devices try to engage the bus at the same time, one becomes master. Hardware immediately switches devices that lose arbitration to slave receive mode. Data output to SDA stops, but SCL is still generated until the end of the byte during which arbitration is lost. An interrupt occurs at the falling edge of the ninth clock of this transfer with I2SR[IAL] = 1 and I2CR[MSTA] = 0.
I2C Programming Examples Clear IIF Y TX TX/Rx ? Master Mode? N Y RX Arbitration Lost? N Last Byte Transmitted ? N RXAK= 0 ? Clear IAL Y Last Byte to be Read ? N Y Y N Y N End of ADDR Cycle (Master RX) ? N Write Next Byte to I2DR Y (Read) Y N Data Cycle SRW=1 ? Generate STOP Signal Read Data from I2DR And Store RX TX Y Set TX Mode Switch to Rx Mode Generate STOP Signal Tx/Rx ? N (WRITE) N ACK from Receiver ? N Read Data from I2DR and Store Tx Next Byte Write Data to I2DR
I2C Programming Examples 24-16 MCF5282 User’s Manual MOTOROLA
Chapter 25 FlexCAN The FlexCAN module is a communication controller implementing the controller area network (CAN) protocol, an asynchronous communications protocol used in automotive and industrial control systems. It is a high speed (1 Mbit/sec), short distance, priority based protocol which can communicate using a variety of mediums (for example, fiber optic cable or an unshielded twisted pair of wires).
Features • • • • • • • • • • “Time Stamp”, based on 16-bit free-running timer Global network time, synchronized by a specific message Programmable I/O modes Maskable interrupts Independent of the transmission medium (external transceiver is assumed) Open network architecture Multimaster bus High immunity to EMI Short latency time for high-priority messages Low-power “sleep” mode, with programmable “wake up” on bus activity A block diagram describing the various submodules of the FlexCAN module is shown i
Features 25.1.1 FlexCAN Memory Map The FlexCAN module address space is split into 128 bytes starting at the base address, and then an extra 256 bytes starting at the base address +128. The upper 256 are fully used for the message buffer structures, as described in Section 25.3.2, “Message Buffer Memory Map.” Out of the lower 128 bytes, only part is occupied by various registers. Table 25-1.
The CAN System 25.2 The CAN System A typical CAN system is shown below in Figure 25-2. CAN Station 2 CAN Station 1 CAN Station n MCF5282 FlexCAN CANTX CANRX Transceiver CAN Bus Figure 25-2. Typical CAN system Each CAN station is connected physically to the CAN bus through a transceiver. The transceiver provides the transmit drive, waveshaping, and receive/compare functions required for communicating on the CAN bus.
Message Buffers 0x0 15–8 7–4 3–0 TIME STAMP CODE LENGTH 0x2 ID[28:18] 0x4 SRR IDE ID[17-15] ID[14-0] ID_HIGH RTR ID_LOW 0x6 DATA BYTE 0 DATA BYTE 1 0x8 DATA BYTE 2 DATA BYTE 3 0xA DATA BYTE 4 DATA BYTE 5 0xC DATA BYTE 6 DATA BYTE 7 0xE CONTROL/STATUS Reserved Figure 25-3.
Message Buffers Table 25-2. Common Extended/Standard Format Frames Field Description Time Stamp Contains a copy of the high byte of the free running timer, which is captured at the beginning of the identifier field of the frame on the CAN bus. Code Refer to Table 25-3 and Table 25-4. Rx Length Length (in bytes) of the Rx data stored in offset 0x6 through 0xD of the buffer. This field is written by the FlexCAN module, copied from the data length code (DLC) field of the received frame.
Message Buffers 25.3.1.2 Fields for Extended Format Frames Table 25-5 describes the message buffer fields used only for extended identifier format frames. Table 25-5. Extended Format Frames Field Description ID[28:18]/[17:15] Contains the 14 most significant bits of the extended identifier, located in the ID HIGH word of the message buffer. Substitute Contains a fixed recessive bit, used only in extended format. Should be set to one by the user for Remote Request Tx buffers.
Functional Overview Message Buffers FlexCAN Base Address Offset 0x80-0x8F 0x82 0x84 0x86 0x8C 0x8E Control/Status ID_HIGH ID_LOW 8 bytes Data field Message Buffer 0 Reserved 0x90 Message Buffer 1 0x9E 0xA0 Message Buffer 2 0xAE Message Buffer 3 0xB0 through 0x16E Message Buffer 14 0x170 Message Buffer 15 0x17E Figure 25-5. FlexCAN Memory Map 25.
Functional Overview 25.4.1 Transmit Process The CPU prepares or changes an MB for transmission by executing the following steps: • • • • Writing the Control/Status word to hold Tx MB inactive (code = 1000). Writing the ID_HIGH and ID_LOW words.
Functional Overview the MB, the ID field, data field (8 bytes at most) and the LENGTH field are stored, the Code field is updated and a status flag is set in the IFLAG register. The CPU should read a receive frame from its MB in the following way: • • • • Control/status word (mandatory—activates internal lock for this buffer). ID (Optional—needed only if a mask was used). Data field word(s). Free-running timer (Releases internal lock —optional). The read of the free-running timer is not mandatory.
Functional Overview 25.4.3.1 Serial Message Buffers (SMBs) To allow double buffering of messages, the FlexCAN has two shadow buffers called serial message buffers. These two buffers are used by the FlexCAN for buffering both received messages and messages to be transmitted. Only one SMB is active at a time, and its function depends upon the operation of the FlexCAN at that time. At no time does the user have access to or visibility of these two buffers. 25.4.3.
Functional Overview 25.4.3.4 Locking and Releasing Message Buffers The lock/release/busy mechanism is designed to guarantee data coherency during the receive process. The following examples demonstrate how the lock/release/busy mechanism will affect FlexCAN operation. 1. Reading a control/status word of a message buffer triggers a lock for that message buffer. A new received message frame which matches the message buffer cannot be written into this message buffer while it is locked. 2.
Functional Overview successfully, the transmit message buffer automatically becomes a receive message buffer, with the same ID as the remote frame which was transmitted. When a remote frame is received by the FlexCAN, the remote frame ID is compared to the IDs of all transmit message buffers programmed with a code of 1010. If there is an exact matching ID, the data frame in that message buffer is transmitted.
Functional Overview 25.4.8 Bit Timing The FlexCAN module uses three 8-bit registers to set up the bit timing parameters required by the CAN protocol. Control registers 1 and 2 (CANCTRL1, CANCTRL2) contain the PROPSEG, PSEG1, PSEG2, and the RJW fields which allow the user to configure the bit timing parameters. The prescaler divide register (PRESDIV) allows the user to select the ratio used to derive the S-clock from the system clock. The time quanta clock operates at the S-clock frequency.
Functional Overview 25.4.9 FlexCAN Error Counters There are two error counters in the FlexCAN: transmit error counter (TXECTR), and receive error counter (RXCTR). The rules for increasing and decreasing these counters are described in the CAN protocol, and are fully implemented in the FlexCAN.
Functional Overview • If the RXCTR increases to a value greater than 127, it is no longer incremented, even if more errors are detected while being a receiver. At the next successful message reception, the counter is set to a value between 119 and 127, in order to return to Error Active state. 25.4.
Functional Overview 25.4.11 Special Operating Modes 25.4.11.1 Debug Mode Debug mode is entered by setting the HALT bit in the CANMCR, or by assertion of the BKPT line. In both cases, the FRZ bit in CANMCR must also be set to allow HALT or BKPT to place the FlexCAN in debug mode. Once entry into debug mode is requested, the FlexCAN waits until an intermission or idle condition exists on the CAN bus, or until the FlexCAN enters the error passive or bus off state.
Functional Overview To exit low-power stop mode: • • • Reset the FlexCAN either by asserting RSTI or by setting the SOFTRST bit CANMCR. Clear the STOP bit in CANMCR. The FlexCAN module can optionally exit low-power stop mode via the self-wake mechanism. If the SELFWAKE bit in CANMCR was set at the time the FlexCAN entered stop mode, then upon detection of a recessive to dominant transition on the CAN bus, the FlexCAN clears the STOP bit in CANMCR and its clocks begin running.
Functional Overview • • • If the FlexCAN is in debug mode when the STOP bit is set, the FlexCAN will assume that debug mode should be exited. As a result, it will try to synchronize with the CAN bus, and only then will it await the conditions required for entry into low-power stop mode. Unlike other modules, the FlexCAN does not come out of reset in low-power stop mode. The basic FlexCAN initialization procedure (see Section 25.4.
Programmer’s Model interrupt routine can be fixed at compilation time. Each of the buffers is assigned a bit in the IFLAG register. The bit is set when the corresponding buffer completes a successful transmission or reception, and cleared when the CPU reads the interrupt flag register (IFLAG) while the associated bit is set, and then writes it back as ‘1’ (and no new event of the same type occurs between the read and the write actions).
Programmer’s Model Table 25-8. CANMCR Field Descriptions Bits Name Description STOP Low-power stop mode enable. The STOP bit may only be set by the CPU. It may be cleared either by the CPU or by the FlexCAN, if the SELFWAKE bit is set. 0 Enable FlexCAN clocks 1 Disable FlexCAN clocks 14 FRZ FREEZE assertion response. When FRZ = 1, the FlexCAN can enter debug mode when the BKPT line is asserted or the HALT bit is set. Clearing this bit field causes the FlexCAN to exit debug mode. Refer to Section 25.
Programmer’s Model Table 25-8. CANMCR Field Descriptions (continued) Bits 7 Name Description Supervisor/user data space. The SUPV bit places the FlexCAN registers in either supervisor or user data space. 0 Registers with access controlled by the SUPV bit are accessible in either user or supervisor privilege mode. 1 Registers with access controlled by the SUPV bit are restricted to supervisor mode. SUPV Self wake enable.
Programmer’s Model Table 25-9. CANCTRL0 Field Descriptions Bits Name Description 7 Bus off interrupt mask. The BOFF MASK bit provides a mask for the bus off interrupt. BOFFMSK 0 Bus off interrupt disabled. 1 Bus off interrupt enabled. 6 Error interrupt mask. The ERRMSK bit provides a mask for the error interrupt. ERRMSK 0 Error interrupt disabled. 1 Error interrupt enabled. 5–3 — Reserved Receive pin configuration control. This bit determines the polarity of the CANRX pin.
Programmer’s Model Table 25-11. CANCTRL1 Field Descriptions Bits Name Description 7 SAMP Sampling mode. The SAMP bit determines whether the FlexCAN module will sample each received bit one time or three times to determine its value. 0 One sample, taken at the end of phase buffer segment 1, is used to determine the value of the received bit. 1 Three samples are used to determine the value of the received bit.
Programmer’s Model Table 25-12. PRESDIV Field Descriptions Bits 7–0 Name Description PRES_DIV Prescaler divide factor. PRESDIV determines the ratio between the system clock frequency and the serial clock (S-clock). The S-clock is determined by the following calculation: f sys S-clock = --------------------------------------------2 ( PRESDIV + 1 ) The reset value of PRESDIV is 0x00, which forces the S-clock to default to the same frequency as the system clock.
Programmer’s Model 25.5.6 Free Running Timer (TIMER) 15 0 Field TIMER Reset 0000_0000_0000_0000 R/W R/W Address IPSBAR + 0x1C_000A Figure 25-11. Free Running Timer (TIMER) Table 25-14 describes the TIMER fields. Table 25-14. TIMER Field Descriptions Bits Name Description 15–0 TIMER The free running timer counter can be read and written by the CPU. The timer starts from zero after reset, counts linearly to 0xFFFF, and wraps around. The timer is clocked by the FlexCAN bit-clock.
Programmer’s Model Table 25-15. Mask examples for Normal/Extended Messages (continued) 1 2 3 4 5 6 7 Base ID ID28.................ID18 I D E Extended ID ID17......................................
Programmer’s Model Table 25-16. RXGMASK, RX14MASK, and RX15MASK Field Descriptions Bits Name Description 31–21 MID 20 — Reserved. The IDE bit of a received frame is always compared. Its location in the mask (bit 19) is always 1, regardless of any CPU write to this bit. 19 — Reserved. The RTR/SRR bit of a received frame is never compared to the corresponding bit in the MB ID field. Note, however, that remote request frames (RTR = 1) are never received into MBs.
Programmer’s Model Table 25-17. ESTAT Field Descriptions Bits Name Description 15–14 BITERR Transmit bit error. The BITERR[1:0] field is used to indicate when a transmit bit error occurs.
Programmer’s Model Table 25-17. ESTAT Field Descriptions (continued) Bits Name Description 3 — 2 BOFFINT Bus off interrupt. The BOFFINT bit is used to request an interrupt when the FlexCAN enters the bus off state. 0 No bus off interrupt requested. 1 When the FlexCAN state changes to bus off, this bit is set, and if the BOFFMSK bit in CANCTRL0 is set, an interrupt request is generated. This interrupt is not requested after reset. 1 ERRINT Error interrupt.
Programmer’s Model Table 25-18. IMASK Field Descriptions Bits Name Description 15–0 BUFnM IMASK contains one interrupt mask bit per buffer. It allows the CPU to designate which buffers will generate interrupts after successful transmission/reception. 0 The interrupt for the corresponding buffer is disabled. 1 The interrupt for the corresponding buffer is enabled. 25.5.10 Interrupt Flag Register (IFLAG) IFLAG contains one interrupt flag bit per buffer.
Programmer’s Model 25.5.11 FlexCAN Receive Error Counter (RXECTR) 7 0 Field RXECTR Reset 0000_0000 R/W R Address IPSBAR + 0x1C_0026 Figure 25-16. FlexCAN Receive Error Counter (RXECTR) Table 25-20 describes the RXECTR fields. Table 25-20. RXECTR Field Descriptions Bits 7–0 Name Description RXECTR Receive error counter. Indicates the current receive error count as defined in the CAN protocol. See Section 25.4.9, “FlexCAN Error Counters” for more details. 25.5.
Chapter 26 General Purpose I/O Module 26.1 Introduction Many of the pins associated with the external interface may be used for several different functions. Their primary function is to provide an external memory interface to access off-chip resources. When not used for their primary function, many of the pins may be used as general-purpose digital I/O pins. In some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported.
Introduction EMDIO / PAS5 / URXD2 D[31:24] / PA[7:0] PORT A D[23:16] / PB[7:0] PORT B D[15:8] / PC[7:0] D[7:0] / PD[7:0] A[23:21] / PF[7:5] / CS[6:4] SDA / PAS1 / URXD2 PORT AS PORT NQ1 QA1 PORT C PORT PORT D PORT QB1 SIZ1 / PE3 / SYNCA SIZ0 / PE2 / SYNCB TS / PE1 / SYNCA TIP / PE0 / SYNCB EMDC / PAS4 / UTXD2 CANRX / PAS3 / URXD2 CANTX / PAS2 / UTXD2 PORT E PORT F OE / PE7 TA / PE6 TEA / PE5 R/W / PE4 SDRAM_CS[1:0] / PSD[2:1] SCL / PAS0 / UTXD2 IRQ[7:1] / PNQ[7:1] AN56 / PQA4 / ETRIG2 A
Introduction 26.1.1 Overview The MCF5282 ports module controls the configuration for various external pins, including those used for: • • • • • • • • • • • External bus accesses Chip selects Debug data Processor status Ethernet data and control FlexCAN transmit/receive data I2C serial control QSPI SDRAM control 32-bit DMA timers UART transmit/receive 26.1.
External Signal Description 26.2 External Signal Description The MCF5282 ports control the functionality of several external pins. These pins are listed in Table 26-1. Table 26-1.
External Signal Description Table 26-1.
Memory Map/Register Definition Table 26-1.
Memory Map/Register Definition Table 26-2.
Memory Map/Register Definition 26.3.2 Register Descriptions 26.3.2.1 Port Output Data Registers (PORTn) The PORTn registers store the data to be driven on the corresponding port n pins when the pins are configured for digital output. Most PORTn registers have a full 8-bit implementation, as shown in Figure 26-2. The remaining PORTn registers use fewer than eight bits. Their bit definitions are shown in Figure 26-3, Figure 26-4, and Figure 26-5. At reset, all bits in the PORTn registers are set.
Memory Map/Register Definition 7 4 Field — Reset 3 2 1 0 PORTn3 PORTn2 PORTn1 PORTn0 0000_1111 R/W: R Address R/W IPSBAR + 0x10_000F (PORTTC), 0x10_0010 (PORTTD), 0x10_0011 (PORTUA) Figure 26-5. Port Output Data Registers (4-bit) PORTn bits are described in Table 26-3. Table 26-3. PORTn (8-bit, 7-bit, 6-bit, and 4-bit) Field Descriptions Register Bits Name 8-bit 7–0 PORTnx 7-bit 6–0 6-bit 5–0 4-bit 3–0 7-bit 7 6-bit 7–6 4-bit 7–4 26.3.2.
Memory Map/Register Definition Field 7 6 — DDRn6 0 DDRn5 DDRn4 Reset R/W: DDRn3 DDRn2 DDRn1 DDRn0 0000_0000 R R/W Address IPSBAR + 0x10_0021(DDRQS) Figure 26-7. Port Data Direction Register (7-bit) 7 Field 6 — 5 4 3 2 1 0 DDRn5 DDRn4 DDRn3 DDRn2 DDRn1 DDRn0 Reset 0000_0000 R/W: R R/W Address IPSBAR + 0x10_0020 (DDRAS), 0x10_0022 (DDRSD) Figure 26-8.
Memory Map/Register Definition 26.3.2.3 Port Pin Data/Set Data Registers (PORTnP/SETn) The PORTnP/SETn registers reflect the current pin states and control the setting of output pins when the pin is configured for digital I/O. Most PORTn registers have a full 8-bit implementation, as shown in Figure 26-10. The remaining PORTn registers use fewer than eight bits. Their bit definitions are shown in Figure 26-11, Figure 26-12, and Figure 26-13. The PORTnP/SETn registers are read/write.
Memory Map/Register Definition 7 4 3 2 1 0 PORTnP3/ SETn3 PORTnP2/ SETn2 PORTnP1/ SETn1 PORTnP0/ SETn0 Field — Reset 0000 Current Pin State R/W: — R/W Address IPSBAR + 0x10_0037 (PORTTCP/SETTC), 0x10_0038 (PORTTDP/SETTD), 0x10_0039 (PORTUAP/SETUA) Figure 26-13. Port Pin Data/Set Data Registers (4-bit) PORTnP/SETn bits are described in Table 26-5. Table 26-5.
Memory Map/Register Definition Field 7 6 5 4 3 2 1 0 — CLRn6 CLRn5 CLRn4 CLRn3 CLRn2 CLRn1 CLRn0 Reset R/W: 0000_0000 R R/W Address IPSBAR + 0x10_0049 (CLRQS) Figure 26-15. Port Clear Output Data Register (7-bit) 7 Field 6 — 5 4 3 2 1 0 CLRn5 CLRn4 CLRn3 CLRn2 CLRn1 CLRn0 Reset 0000_0000 R/W: R R/W Address IPSBAR + 0x10_0048 (CLRAS), 0x10_004A (CLRSD) Figure 26-16.
Memory Map/Register Definition 26.3.2.5 Port B/C/D Pin Assignment Register (PBCDPAR) The PBCDPAR controls the pin function of ports B, C, and D. The PBCDPAR register is read/write. Field 7 6 PBPA PCDPA — See Note 1 00_0000 R/W R Reset See Note 1 1 R/W: R/W 5 0 Address IPSBAR + 0x10_0050 Figure 26-18. Port B/C/D Pin Assignment Register (PBCDPAR) 1 Reset state determined during reset configuration as shown in Table 26-8. Table 26-7.
Memory Map/Register Definition 26.3.2.6 Port E Pin Assignment Register (PEPAR) The PEPAR controls the pin function of port E. The PEPAR register is read/write.
Memory Map/Register Definition Table 26-9. PEPAR Field Descriptions (continued) Bits Name Description 6 PEPA3 Port E pin assignment 3 This bit configures the port E3 pin for its alternate function (SYNCA) or digital I/O. 1 Port E3 pin configured for alternate function (SYNCA) 0 Port E3 pin configured for digital I/O NOTE: The SIZ1 primary function on the port E3 pin is enabled by the SZEN bit in the CCR register.
Memory Map/Register Definition 26.3.2.7 Port F Pin Assignment Register (PFPAR) The PFPAR controls the pin function of port F[7:5]. Field 7 6 5 PFPA7 PFPA6 PFPA5 4 0 — Reset See Note 1 1 0_0000 R/W: R/W R Address IPSBAR + 0x10_0051 Figure 26-20. Port F Pin Assignment Register (PFPAR) 1 Reset state determined during reset configuration. PFPAn = 1 in master mode and 0 in all other modes. Table 26-11. PFPAR Field Descriptions Bits Name Description 7 PFPA7 Port F pin assignment 1.
Memory Map/Register Definition 26.3.2.8 Port J Pin Assignment Register (PJPAR) The PJPAR controls the pin function of port J. Field 7 6 5 4 3 2 1 0 PJPA7 PJPA6 PJPA5 PJPA4 PJPA3 PJPA2 PJPA1 PJPA0 Reset See Note 1 1 R/W: R/W Address IPSBAR + 0x10_0054 Figure 26-21. Port J Pin Assignment Register (PJPAR) 1 Reset state determined during reset configuration. PJPAn = 1 in master mode and 0 in all other modes. Table 26-12.
Memory Map/Register Definition 26.3.2.9 Port SD Pin Assignment Register (PSDPAR) The PSDPAR controls the pin function of port SD. 7 Field 6 0 PSDPA — Reset See Note 1 1 R/W: 000_0000 R/W R Address IPSBAR + 0x10_0055 Figure 26-22. Port SD Pin Assignment Register (PSDPAR) 1 Reset state determined during reset configuration. PJPAn = 1 in master mode and 0 in all other modes. Table 26-13. PSDPAR Field Descriptions Bits Name Description 7 PSDPA Port SD pin assignment.
Memory Map/Register Definition Table 26-14. PASPAR Field Descriptions Bits Name Description 15–12 — 11–10 PASPA5 Port AS pin assignment 5. These bits configure the AS5 pin for its primary function (EMDIO), alternate function (URXD2), or digital I/O. 0x Port AS5 pin configured for digital I/0 10 Port AS5 pin configured for alternate function (URXD2) 11 Port AS5 pin configured for primary function (EMDIO) 9-8 PASPA4 Port AS pin assignment 4.
Memory Map/Register Definition Table 26-15. PEHLPAR Field Descriptions Bits Name Description 7 PEHPA Port EH pin assignment. This bit configures the port EH pins for its primary functions (ETXCLK, ETXEN, ETXD[0], ECOL, ERXCLK, ERXDV, ERXD[0], ECRS) or digital I/O. 1 Port EH pins configured for primary functions (ETXCLK, ETXEN, ETXD[0], ECOL, ERXCLK, ERXDV, ERXD[0], ECRS) 0 Port EH pins configured for digital I/O 6 PELPA Port EL pin assignment.
Memory Map/Register Definition Table 26-16. PQSPAR Field Description (continued) Bits Name Description 2 PQSPA2 Port QS pin assignment 2. This bit configures the port QS2 pin for its primary function (QSPI_CLK) or digital I/O. 1 Port QS2 pin configured for primary function (QSPI_CLK) 0 Port QS2 pin configured for digital I/O 1 PQSPA1 Port QS pin assignment 1. This bit configures the port QS1 pin for its primary function (QSPI_DIN) or digital I/O.
Memory Map/Register Definition Table 26-17. PTCPAR Field Descriptions (continued) Bits Name Description 3-2 PTCPA1 Port TC pin assignment 1. This field configures the port TC1 pin for its primary function (DTIN2), alternate 1 function (UCTS1), alternate 2 function (UCTS0) or digital I/O.
Memory Map/Register Definition Table 26-18. PTDPAR Field Descriptions (continued) Bits Name Description 3-2 PTDPA1 Port TD pin assignment 1. This field configures the port TD1 pin for its primary function (DTIN0), alternate 1 function (UCTS1), alternate 2 function (UCTS0) or digital I/O.
Functional Description 26.4 Functional Description 26.4.1 Overview The initial pin function is determined during reset configuration. The pin assignment registers allow the user to select between digital I/O or another pin function after reset. In single-chip mode, all pins are configured as digital I/O by default, except for debug data pins (DDATA[3:0]) and processor status pins (PST[3:0]). These pins are configured for their primary functions by default in all modes.
Initialization/Application Information Data written to the PORTn register of any pin configured as a digital output is immediately driven to its respective pin, as shown in Figure 26-30. CLKOUT OUTPUT DATA REGISTER OUTPUT PIN Figure 26-30. Digital Output Timing 26.5 Initialization/Application Information The initialization for the MCF5282 ports module is done during reset configuration.
Chapter 27 Queued Analog-to-Digital Converter (QADC) The queued analog-to-digital converter (QADC) is a 10-bit, unipolar, successive approximation converter. Up to eight analog input channels can be supported using internal multiplexing. A maximum of 18 input channels can be supported in the expanded, externally multiplexed mode. The QADC consists of an analog front-end and a digital control subsystem. The analog section includes input pins, an analog multiplexer, and sample and hold analog circuits.
Block Diagram • • • • — External edge trigger and gated trigger — Periodic/interval timer, within QADC module (queues 1 and 2) — Software command Single scan or continuous scan of queues 64 result registers Output data readable in three formats: — Right-justified unsigned — Left-justified signed — Left-justified unsigned Unused analog channels can be used as discrete input/output pins. 27.
Modes of Operation 27.3 Modes of Operation This subsection describes the two modes of operation in which the QADC does not perform conversions in a regular fashion: • • Debug mode Stop mode 27.3.1 Debug Mode The QDBG bit in the module configuration register (QADCMCR) governs behavior of the QADC when the CPU enters background debug mode. When QDBG is clear, the QADC operates normally and is unaffected by CPU background debug mode. See Section 27.6.1.
Signals • • • • • Aborts the conversion sequence in progress Makes the data direction register (DDRQA), port data registers (PORTQA and PORTQB), control registers (QACR2, QACR1, and QACR0) and the status registers (QASR1 and QASR0) read-only. Only the module configuration register (QADCMCR) remains writable.
Internal Digital Power Shared with Other Modules VSSI VDDI Analog Power and Ground VSSA VDDA Analog References VRH VRL Port QA Analog Inputs External Trigger Inputs External MUX Address Outputs Digital I/O AN0/ANW/PQB0 AN1/ANX/PQB1 AN2/ANY/PQB2 AN3/ANZ/PQB3 Analog Mux and Port Logic AN52/MA0/PQA0 AN53/MA1/PQA1 AN55/ETRIG1/PQA3 AN56/ETRIG2/PQA4 Analog Converter Digital Results and Control PORT QA Port QB Analog Inputs External MUX Inputs Digital Inputs PORT QB Signals Figure 27-2.
Signals 27.4.2.2 Port QB Digital I/O Signals Port QB signals are referred to as PQB[3:0] when used as a 4-bit digital input/output port. In addition to functioning as analog input signals, the port QB signals are also connected to the input of a synchronizer during reads and may be used as general-purpose digital inputs when the applied voltages meet VIH and VIL requirements. Each port QB signal is configured as an input or output by programming the port data direction register (DDRQB).
Memory Map Table 27-1. Multiplexed Analog Input Channels Multiplexed Analog Input Channels ANW Even numbered channels from 0 to 6 ANX Odd numbered channels from 1 to 7 ANY Even numbered channels from 16 to 22 ANZ Odd numbered channels from 17 to 23 27.4.6 Voltage Reference Signals VRH and VRL are the dedicated input signals for the high and low reference voltages.
Register Descriptions Table 27-2.
Register Descriptions 7 Field 6 0 SUPV — Reset R/W: 1000_0000 R/W Address R IPSBAR + 0x19_0000, 0x19_0001 Figure 27-3. QADC Module Configuration Register (QADCMCR) Table 27-3. QADCMCR Field Descriptions Bit(s) Name Description 15 QSTOP Stop enable. 1 Force QADC to idle state. 0 QADC operates normally. 14 QDBG Debug enable. 1 Finish any conversion in progress, then freeze in debug mode 0 QADC operates normally. 13–8 — 7 SUPV 6–0 — Reserved, should be cleared.
Register Descriptions 7 6 5 4 3 2 1 0 PQA4 (AN56) (ETRIG2) PQA3 (AN55) (ETRIG1) — PQA1 (AN53) (MA1) PQA0 (AN52) (MA0) Field — Reset 000 See Note 0 See Note R/W: R R/W R R/W Address IPSBAR + 0x19_0006 Figure 27-4. QADC Port QA Data Register (PORTQA) 7 6 5 4 3 2 1 0 PQB3 (AN3) (ANZ) PQB2 (AN2) (ANY) PQA1 (AN1) (ANX) PQA0 (AN0) (ANW) Field — Reset 0000 See Note R/W: R R/W Address IPSBAR + 0x19_0007 Figure 27-5.
Register Descriptions NOTE Use caution when mixing digital and analog inputs. They should be isolated as much as possible. Rise and fall times should be as large as possible to minimize ac coupling effects. 7 Field 6 5 — 4 3 2 1 0 DDQA4 DDQA3 — DDQA1 DDQA0 Reset 0000_0000 R/W: R R/W Address R R/W IPSBAR + 0x19_0008 Figure 27-6.
Register Descriptions 15 Field 14 13 MUX 12 — Field — 0000_0000 R/W R R/W R 7 6 5 4 3 2 1 0 — QPR6 QPR5 QPR4 QPR3 QPR2 QPR1 QPR0 Reset R/W: 8 TRG Reset R/W: 11 0001_0011 R R/W Address IPSBAR + 0x19_000a, 0x19_000b Figure 27-8. QADC Control Register 0 (QACR0) Table 27-4. QACR0 Field Descriptions Bit(s) Name Description 15 MUX Externally multiplexed mode.
Register Descriptions Table 27-5.
Register Descriptions 27.6.5.2 QADC Control Register 1 (QACR1) QACR1 is the mode control register for queue 1. This register governs queue operating mode and the use of completion and/or pause interrupts. Typically, these bits are written once when the QADC is initialized and are not changed thereafter. Stop mode resets this register.
Register Descriptions Table 27-7.
Register Descriptions 27.6.5.3 QADC Control Register 2 (QACR2) QACR2 is the mode control register for queue 2. This register governs queue operating mode and the use of completion and/or pause interrupts. Typically, these bits are written once when the QADC is initialized and not changed thereafter. QACR2 also includes a resume feature that selects the resumption point for queue 2 after its operation is suspended by a queue 1 trigger event.
Register Descriptions If BQ2[6:0] is changed while queue 1 is active, the effect of BQ2[6:0] as an end-of-queue indication for queue 1 is immediate. However, beware of the risk of losing the end-of-queue 1 when changing BQ2[6:0]. Using EOQ (channel 63) to end queue 1 is recommended. NOTE If BQ2[6:0] was assigned to the CCW that queue 1 is currently working on, then that conversion is completed before the change to BQ2[6:0] takes effect.
Register Descriptions Table 27-8. QACR2 Field Descriptions Bit(s) Name Description 15 CIE2 Queue 2 completion software interrupt enable. Enables an interrupt request upon completion of queue 2. The interrupt request is initiated when the conversion is complete for the last CCW in queue 2. 1 Enable queue 2 completion interrupt. 0 Disable queue 2 completion interrupt. 14 PIE2 Queue 2 pause interrupt enable. Enables an interrupt request when queue 2 enters the pause state.
Register Descriptions Table 27-9.
Register Descriptions • • When the current CCW contains the end-of-queue code (channel 63) instead of a valid channel number When the currently completed CCW is in the last location of the CCW RAM. Once PFn is set, the queue enters the paused state and waits for a trigger event to allow queue execution to continue. However, a special case occurs when the CCW with the pause bit set is the last CCW in a queue; queue execution is complete.
Register Descriptions gate, TORn is set. This is considered an overrun condition. In this case, CF1 has been set for the first end-of-queue condition and TORn sets for the second end-of-queue condition. For TOR1 to set, CF2 must not be cleared before the second end-of-queue. The QS field indicates the status of queue 1 and queue 2.
Register Descriptions When a queue enters the paused state, CWP points to the CCW with the pause bit set. While in pause, the CWP value is maintained until a trigger event occurs on either queue. Usually, the CWP is updated a few clock cycles before the queue status field shows that the queue has become active. For example, a read of CWP may point to a CCW in queue 2, while the queue status field shows queue 1 paused and queue 2 trigger pending.
Register Descriptions Table 27-10. QASR0 Field Descriptions Bit(s) Name Description 15, 13 CFn Queue completion flag. Indicates that a queue scan has been completed. CF[1:2] is set by the QADC when the input channel sample requested by the last CCW in the queue is converted, and the result is stored in the result table. When CFn is set and queue completion interrupts are enabled (QACRn[CIEn] = 1), the QADC requests an interrupt.
Register Descriptions Table 27-11. CCW Pause Bit Response (continued) Scan Mode Queue Operation PF Asserts? Interval timer continuous-scan Pauses Yes Software-initiated single-scan Continues Yes Software-initiated continuous-scan Continues Yes Externally gated single-scan Continues No Externally gated continuous-scan Continues No Table 27-12.
Register Descriptions Q2 Trigger Event Q1 Idle/ Q2 Active Q1 Trigger Event Q1 Idle/ Q2 Idle Q2 Complete Q1 Complete Q1 Active/ Q2 Idle Delayed Transition Q2 Pause Bit Set Q1 Pause Bit Set Q1 Idle/ Q2 Trigger Pending (Temporary) Q2 Trigger Event Q2 Trigger Event Q1 Trigger Event Q1 Trigger Event Q1 Complete Q1 Complete Q1 Idle/ Q2 Paused Q1 Trigger Event Q1 Paused/ Q2 Idle Q1 Active/ Q2 Trigger Pending Q1 Active/ Q2 Suspended Q1 Pause Bit Set Q1 Complete Q1 Paused/ Q2 Trigger Pending (Tem
Register Descriptions 27.6.6.2 QADC Status Register 1 (QASR1) Stop mode resets this register . 15 14 Field — 13 12 11 10 9 8 CWPQ15 CWPQ14 CWPQ13 CWPQ12 CWPQ11 CWPQ10 Reset 0011_1111 R/W: R 7 6 Field — 5 4 3 2 1 0 CWPQ25 CWPQ24 CWPQ23 CWPQ22 CWPQ21 CWPQ20 Reset 0011_1111 R/W: R Address IPSBAR + 0x19_0012, 0x19_0013 Figure 27-13. QADC Status Register 1 (QASR1) Table 27-13.
Register Descriptions the current CCW. The bits in this register are read anytime (except during stop mode), write anytime (except during stop mode). 15 10 9 8 P BYP Field — Reset 0000_00 Unaffected R/W: R R/W Field 7 6 5 4 3 2 1 0 IST1 IST0 CHAN5 CHAN4 CHAN3 CHAN2 CHAN1 CHAN0 Reset Undefined R/W: R Address IPSBAR + 0x19_0200, 0x19_027e Figure 27-14. Conversion Command Word Table (CCW) Table 27-14.
Register Descriptions Table 27-14. CCW Field Descriptions (continued) Bit(s) Name Description 7–6 IST Input sample time. Specifies the length of the sample window. The input sample time can be varied, under software control, to accommodate various input channel source impedances. Longer sample times permit more accurate A/D conversions of signals with higher source impedances. Table 27-15 shows the four selectable input sample times.
Register Descriptions Table 27-17.
Register Descriptions Table 27-18. RJURR Field Descriptions Bit(s) Name 15–10 — 9–0 RESULT 27.6.8.2 Reserved, should be cleared. The conversion result is unsigned, right-justified data. Left-Justified Signed Result Register (LJSRR) 15 Field Description 14 8 S RESULT Reset Undefined R/W: R/W 7 0 Field RESULT Reset Undefined R/W: R/W Address IPSBAR + 0x19_0300, 0x19_037e Figure 27-16. Left-Justified Signed Result Register (LJSRR) Table 27-19.
Functional Description 7 Field 6 5 0 RESULT — Reset Undefined R/W: R/W R Address IPSBAR + 0x19_0380, 0x19_03fe Figure 27-17. Left-Justified Unsigned Result Register (LJURR) Table 27-20. LJURR Field Descriptions Bit(s) Name 15–6 RESULT 5–0 — Description The conversion result is unsigned, left-justified data. Reserved, should be cleared. 27.7 Functional Description This subsection provides a functional description of the QADC. 27.7.
Functional Description For example, four 4-input multiplexer chips can be put at the connector where the analog signals first arrive on the printed circuit board. As a result, only four analog signals need to be shielded from noise as they approach the microcontroller chip, rather than having to protect 16 analog signals. However, external multiplexer chips may introduce additional noise and errors if not properly utilized.
Functional Description AN1 AN3 AN5 AN7 MUX MUX AN0/ANW/PQB0 AN1/ANX/PQB1 AN2/ANY/PQB2 AN3/ANZ/PQB3 Port QB AN0 AN2 AN4 AN6 AN55/ETRIG1PQA3 AN56/ETRIG2/PQA4 AN16 AN18 AN20 AN22 AN17 AN19 AN21 AN23 Port QA AN52/MA0/PQA0 AN53/MA1/PQA1 MUX MUX Figure 27-18. External Multiplexing Configuration When externally multiplexed mode is selected, the QADC automatically drives the MA output signals from the channel number in each CCW.
Functional Description directly connected signals. User software simply puts the channel number of externally multiplexed channels into CCWs. Figure 27-18 shows that the two MA signals may also be analog input signals. When external multiplexing is selected, none of the MA signals can be used for analog or digital inputs. They become multiplexed address outputs and are unaffected by DDRQA[1:0]. 27.7.2.
Functional Description 16 PQA4 Chan. Decode & MUX 16:1 PQA0 10-bit A/D Converter 4 CHAN[5:0] 6 Input Bias Circuit Internal Channel Decode Sample Buffer PQB0 PowerDown State Machine & Logic CSAMP VRH VRL VSSA 2 SAR Timing 10 Analog Power Comparator QCLK IST Start Conv End OF Conv SAR[9:0] 10 VDDA STOP RST 10 Signals From/to Queue Control Logic PQB3 Successive Approximation Register Figure 27-19. QADC Analog Subsystem Block Diagram 27.7.3.
Functional Description Buffer Sample Time: 2 Cycles Final Sample Time: n Cycles (2,4,8,16) Resolution Time: 10 Cycles QCLK Sample Time Successive Approximation Resolution Sequence Figure 27-20. Conversion Timing If the amplifier bypass mode is enabled for a conversion by setting the amplifier bypass (BYP) field in the CCW, the timing changes to that shown in Figure 27-21. See Section 27.6.7 for more information on the BYP field.
Digital Control Subsystem 27.7.3.5 Comparator The comparator output feeds into the SAR, which accumulates the A/D conversion result sequentially, beginning with the MSB. 27.7.3.6 Bias The bias circuit is controlled by the STOP signal to power-up and power-down all the analog circuits. 27.7.3.7 Successive Approximation Register (SAR) The input of the SAR is connected to the comparator output. The SAR sequentially receives the conversion value one bit at a time, starting with the MSB.
Digital Control Subsystem 27.8.1 Queue Priority Timing Examples This subsection describes the QADC priority scheme when trigger events on two queues overlap or conflict. 27.8.1.1 Queue Priority Queue 1 has priority over queue 2 execution. These cases show the conditions under which queue 1 asserts its priority: • • • • • When a queue is not active, a trigger event for queue 1 or queue 2 causes the corresponding queue execution to begin.
Digital Control Subsystem The choice of single-scan or continuous-scan applies to the full queue, and is not applied to each subqueue. Once a subqueue is initiated, each CCW is executed sequentially until the last CCW in the subqueue is executed and the pause state is entered. Execution can only continue with the next CCW, which is the beginning of the next subqueue. A subqueue cannot be executed a second time before the overall queue execution has been completed.
Digital Control Subsystem 27.8.1.2 Queue Priority Schemes Because there are two conversion command queues and only one A/D converter, a priority scheme determines which conversion occurs. Each queue has a variety of trigger events that are intended to initiate conversions, and they can occur asynchronously in relation to each other and other conversions in progress.
Digital Control Subsystem Below the queue execution flows are three sets of blocks that show the status information that is made available to the user. The first two rows of status blocks show the condition of each queue as: • • • • • Idle Active Pause Suspended (queue 2 only) Trigger pending The third row of status blocks shows the 4-bit QS status register field that encodes the condition of the two queues.
Digital Control Subsystem leaving little time to retrieve the previous results. Also, when trigger events are occurring at a high rate for queue 1, the lower priority queue 2 channels may not get serviced at all. T1 T1 T1 T1 T1 T2 Q1: C1 C2 C3 C4 C1 C2 C3 Q2: TOR1 TOR1 TOR1 T2 T2 C2 C3 C4 CF1 C1 CF1 TOR2 TOR2 Q1: IDLE ACTIVE IDLE 1000 QS: CF2 IDLE ACTIVE IDLE Q2: C4 1000 0000 ACTIVE IDLE 0010 0000 Figure 27-24.
Digital Control Subsystem T1 Q1: C1 C2 C3 C4 CF1 T2 C1 C2 C3 C4 Q2: CF2 Q1: IDLE QS: TRIGGERED IDLE Q2: IDLE ACTIVE 0000 1011 1000 ACTIVE IDLE 0010 0000 Figure 27-26. CCW Priority Situation 4 Situation S5 (Figure 27-27) shows that when multiple queue 2 trigger events are detected while queue 1 is busy, the trigger overrun error bit is set, but queue 1 execution is not disturbed.
Digital Control Subsystem when the RESUME control bit is set to 0. Situation S7 (Figure 27-29) shows that when pause operation is not used with queue 2, queue 2 suspension works the same way. T1 Q1: T1 C1 C2 C3 C4 RESUME = 0 T2 PF1 CF1 Q2: C1 C1 C2 C2 C3 C4 CF2 IDLE Q1: ACTIVE PAUSE IDLE Q2: 0000 QS IDLE ACTIVE SUSPEND ACTIVE IDLE 0110 1010 0010 0000 0100 1000 ACTIVE ACTIVE Figure 27-28. CCW Priority Situation 6 .
Digital Control Subsystem T1 Q1: T1 C1 C2 C3 C4 T2 PF1 CF1 Q2: C1 C2 C2 C3 RESUME=1 C4 CF2 IDLE Q1: ACTIVE PAUSE IDLE Q2: QS: 0000 IDLE ACTIVE SUSPEND ACTIVE IDLE 0110 1010 0010 0000 0100 1000 ACTIVE ACTIVE Figure 27-30.
Digital Control Subsystem T1 Q1: C1 T2 Q2: T1 C2 T2 C1 C3 PF1 T2 C1 C2 C2 TOR2 Q2: IDLE QS: 0000 ACTIVE 0010 T2 C3 ACTIVE 1010 0110 C4 ACTIVE PAUSE ACT 0101 IDLE SUSPEND 0110 RESUME = 0 CF2 TOR2 PAUSE SUSPEND CF1 C3 PF2 ACTIVE IDLE Q1: C4 IDLE ACTIVE 1010 0000 0010 Figure 27-32.
Digital Control Subsystem passed. Similarly, when freeze occurs while queue 2 is suspended, after freeze, queue 2 resumes execution as soon as queue 1 is finished. Situations 12 through 19 (Figure 27-34 to Figure 27-41) show examples of all of the freeze situations. FREEZE T1 C1 Q1: C2 C3 C4 CF1 Figure 27-34. CCW Freeze Situation 12 FREEZE T2 Q2: C1 C2 C3 C4 CF2 Figure 27-35. CCW Freeze Situation 13 TRIGGERS IGNORED FREEZE T1 Q1: T1 T1 C1 C2 C3 C4 T2 T2 CF1 Figure 27-36.
Digital Control Subsystem TRIGGERS IGNORED FREEZE T1 Q1: T1 C1 T1 C2 C3 C4 PF1 CF1 Figure 27-38. CCW Freeze Situation 16 TRIGGERS IGNORED FREEZE T2 T2 Q2: C1 T2 C2 C3 C4 PF2 CF2 Figure 27-39. CCW Freeze Situation 17 FREEZE T1 Q1: C1 C2 C3 C4 T2 CF1 TRIGGER CAPTURED, RESPONSE DELAYED AFTER FREEZE Q2: C1 C2 C3 C4 CF2 Figure 27-40. CCW Freeze Situation 18 FREEZE T1 Q1: C1 C2 C3 T2 Q2: C4 CF1 C1 C2 C3 C4 C4 CF2 Figure 27-41.
Digital Control Subsystem 27.8.2 Boundary Conditions The queue operation boundary conditions are: • • • • The first CCW in a queue specifies channel 63, the end-of-queue (EOQ) code. The queue becomes active and the first CCW is read. The end-of-queue is recognized, the completion flag is set, and the queue becomes idle. A conversion is not performed. BQ2 (beginning of queue 2) is set at the end of the CCW table (63) and a trigger event occurs on queue 2.
Digital Control Subsystem 27.8.3 Scan Modes The QADC queuing mechanism allows application software to utilize different requirements for automatically scanning input channels. In single-scan mode, a single pass through a sequence of conversions defined by a queue is performed. In continuous-scan mode, multiple passes through a sequence of conversions defined by a queue are executed.
Digital Control Subsystem • • Externally gated single-scan mode Interval timer single-scan mode NOTE Queue 2 cannot be programmed for externally gated single-scan mode. In all single-scan queue operating modes, queue execution is enabled by writing the single-scan enable bit to a 1 in the queue’s control register. The single-scan enable bits, SSE1 and SSE2, are provided for queue 1 and queue 2, respectively. Until a queue’s single-scan enable bit is set, any trigger events for that queue are ignored.
Digital Control Subsystem execution of the first CCW in the queue. If a pause occurs, another trigger event is generated internally, and then execution continues without pausing. The QADC automatically performs the conversions in the queue until an end-of-queue condition is encountered. The queue remains idle until the single-scan enable bit is again set.
Digital Control Subsystem While the gate is open, queue 1 executes one time. Each CCW is read and the indicated conversions are performed until an end-of-queue condition is encountered. When queue 1 completes, the QADC sets the completion flag (CF1) and clears the single-scan enable bit. Set the single-scan enable bit again to allow another scan of queue 1 to be initiated during the next open gate.
Digital Control Subsystem • • When the interrupt rate in the periodic timer continuous-scan mode would be too high In sensitive battery applications, where the interval timer single-scan mode uses less power than the software-initiated continuous-scan mode 27.8.7 Continuous-Scan Modes A continuous-scan queue operating mode is used to execute multiple passes through a sequence of conversions defined by a queue.
Digital Control Subsystem NOTE In continuous-scan modes, all samples are guaranteed to be taken during one pass through the queue (coherently), except when a queue 1 trigger event halts queue 2 execution. The time between consecutive conversions has been designed to be consistent. However, for queues that end with a CCW containing the EOQ code (channel 63), the time between the last queue conversion and the first queue conversion requires one additional CCW fetch cycle.
Digital Control Subsystem 27.8.7.2 Externally Triggered Continuous-Scan Mode The QADC provides external trigger signals for both queues. When externally triggered continuous-scan mode is selected, a transition on the associated external trigger signal initiates queue execution. The polarity of the external trigger signal is programmable, so that a mode which begins queue execution on the rising or falling edge can be selected.
Digital Control Subsystem 27.8.7.4 Periodic Timer Continuous-Scan Mode The QADC includes a dedicated periodic timer for initiating a scan sequence on queue 1 and/or queue 2. A programmable timer interval ranging from 27 to 217 times the QCLK period in binary multiples can be selected. The QCLK period is prescaled down from the MCU clock. When a periodic timer continuous-scan mode is selected, the timer begins counting.
Digital Control Subsystem QPR[6:0] System Clock Divide by 2 Prescaler SAR Control Input Sample Time from CCW ATD Converter State Machine 2 SAR 10 Binary Counter 27 28 29 210 211 212 213 214 215 216 217 Queue 1 and Queue 2 Timer Mode Rate Selection 8 Periodic Timer/Interval Timer Select 2 Periodic/Interval Trigger Event for Q1 and Q2 Figure 27-42. QADC Clock Subsystem Functions CAUTION A change in the prescaler value while a conversion is in progress is likely to corrupt the result.
Digital Control Subsystem NOTE Interval timer single-scan mode does not start the periodic/interval timer until the single-scan enable bit is set.
Digital Control Subsystem Conversion Command Word (CCW) Table 00 Result Word Table Beginning of Queue 1 00 • • • • • Beginning of Queue 2 63 • Channel Select, Sample, Hold, A/D Conversion End of Queue 1 • • • • • • 63 End of Queue 2 10-bit Conversion Command Word Format 10-bit Result, Readable in Three 16-BIT Formats 9 8 [7:6] [5:0] 15 14 13 12 11 10 [9:0] P BYP IST CHAN 0 0 0 0 0 0 RESULT Right-Justified, Unsigned Result P — Pause after Conversion until Next Trigger BYP —
Digital Control Subsystem During queue execution, the QADC reads each CCW from the active queue and executes conversions in three stages: • • • Initial sample Final sample Resolution During initial sample, a buffered version of the selected input channel is connected to the sample capacitor at the input of the sample buffer amplifier. During the final sample period, the sample buffer amplifier is bypassed, and the multiplexer input charges the sample capacitor directly.
Signal Connection Considerations • • • • Any conversion in progress for a queue is aborted when that queue’s operating mode is changed to disabled. Putting a queue into the disabled mode does not power down the converter. Changing a queue’s operating mode to another valid mode aborts any conversion in progress. The queue restarts at its beginning once an appropriate trigger event occurs. For low-power operation, the stop bit can be set to prepare the module for a loss of clocks.
Signal Connection Considerations 27.9.1 Analog Reference Signals No A/D converter can be more accurate than its analog reference. Any noise in the reference can result in at least that much error in a conversion. The reference for the QADC, supplied by signals VRH and VRL, should be low-pass filtered from its source to obtain a noise-free, clean signal. In many cases, simple capacitive bypassing may suffice. In extreme cases, inductors or ferrite beads may be necessary if noise or RF energy is present.
Signal Connection Considerations never transfer a full-scale value. If VRL is less than VSSA, the sample amplifier can never transfer a 0 value. Figure 27-45 shows the results of reference voltages outside the range defined by VDDA and VSSA. At the top of the input signal range, VDDA is 10 mV lower than VRH. This results in a maximum obtainable 10-bit conversion value 0x03fe.
Signal Connection Considerations Recall that when QS = 0, both queues are disabled; when QS = 8, queue 1 is active and queue 2 is idle; and when QS = 4; queue 1 is paused and queue 2 is disabled. TIME BETWEEN TRIGGERS CONVERSION TIME = 14 QCLKS CONVERSION TIME = 14 QCLKS QCLK TRIG1 EOC CWP 8 0 QS LAST 4 CCW0 LAST CWPQ1 8 CCW1 CCW0 CCW2 CCW1 R0 Q1 RES R1 Figure 27-46.
Signal Connection Considerations When the gate closes, the active conversion completes before the queue goes idle. When Q1 completes, both the CF1 bit sets and the SSE bit clears. In this mode, the PF1 bit sets to reflect that a gate closing occurred before the queue completed. Figure 27-48 shows the timing for conversions in externally gated continuous scan mode with the same assumptions as in Figure 27-47. At the end of Q1,the completion flag CF1 sets and the queue restarts.
Signal Connection Considerations TRIG1 (GATE) EOC QS CWP 0 8 LAST CCW0 CCW1 CCW2 CCW3 CCW0 CCW3 CCW0 CSPQ1 LAST CCW0 CCW1 CCW2 CCW3 CCW2 CCW3 Q1 RES LAST XX R0 R1 R2 R3 R2 R3 CF1 TOR1 Queue Restart Queue Restart Figure 27-48. Gated Mode, Continuous Scan Timing 27.9.4 Analog Supply Filtering and Grounding Two important factors influencing performance in analog integrated circuits are supply filtering and grounding.
Signal Connection Considerations The problem of how and when to combine digital and analog grounds arises from the large transients which the digital ground must handle. If the digital ground is not able to handle the large transients, the associated current can return to ground through the analog ground. It is this excess current overflowing into the analog ground which causes performance degradation by developing a differential voltage between the true analog ground and the microcontroller’s ground pins.
Signal Connection Considerations • • • • • Analog ground must be low impedance to all analog ground points in the circuit. Bypass capacitors should be as close to the power pins as possible. The analog ground should be isolated from the digital ground. This can be done by cutting a separate ground plane for the analog ground. Non-minimum traces should be utilized for connecting bypass capacitors and filters to their corresponding ground/power points. Minimum distance for trace runs when possible. 27.9.
Signal Connection Considerations VSTRESS RSTRESS IinjP + 10 kΩ RSELECTED IIN ANn Signal Under Stress Parasitic Device ANn+1 VIN VDDA Adjacent Signal Figure 27-51.
Signal Connection Considerations 27.9.6 Analog Input Considerations The source impedance of the analog signal to be measured and any intermediate filtering should be considered whether external multiplexing is used or not. Figure 27-52 shows the connection of eight typical analog signal sources to one QADC analog input signal through a separate multiplexer chip. Also, an example of an analog signal source connected directly to a QADC analog input channel is displayed. MOTOROLA Chapter 27.
Signal Connection Considerations Analog Signal Source RSource2 ~ Filtering and Interconnect RFilter2 Typical MUX Chip (MC54HC4051, MC74HC4051, MC54HC4052, MC74HC4052, MC54HC4053, etc.) Interconnect QADC 0.01 µF1 CSource RSource2 ~ CFilter RFilter2 CMUXIN 0.01 µF1 CSource RSource2 ~ CFilter RFilter2 CMUXIN 0.01 µF1 CSource RSource2 ~ CFilter RFilter2 RMUXOUT CMUXIN CMUXOUT 0.01µF1 CSource RSource2 ~ CFilter RFilter2 CPCB CMUXIN CP CSAMP CIn = CP + CSAMP 0.
Signal Connection Considerations 27.9.7 Analog Input Pins Analog inputs should have low AC impedance at the pins. Low AC impedance can be realized by placing a capacitor with good high frequency characteristics at the input signal of the device. Ideally, that capacitor should be as large as possible (within the practical range of capacitors that still have good high-frequency characteristics). This capacitor has two effects: • • It helps attenuate any noise that may exist on the input.
Signal Connection Considerations • • • • The external capacitor is perfect (no leakage, no significant dielectric absorption characteristics, etc.). All parasitic capacitance associated with the input signal is included in the value of the external capacitor. Inductance is ignored. The “on” resistance of the internal switches is 0 ohms and the “off” resistance is infinite. 27.9.7.
Interrupts 27.9.7.2 Error Resulting from Leakage A series resistor limits the current to a signal; therefore, input leakage acting through a large source impedance can degrade A/D accuracy. The maximum input leakage current is specified in MCF5282 Electrical Specifications. Input leakage is greater at higher operating temperatures. In the temperature range from 125°C to 50°C, the leakage current is halved for every 8°C to 12°C reduction in temperature. Assuming VRH–VRL = 5.
Interrupts Table 27-26. QADC Status Flags and Interrupt Sources Queue Queue 1 Queue 2 Status Flag Interrupt Enable Bit Result written for last CCW in queue 1 CF1 CIE1 Result written for a CCW with pause bit set in queue 1 PF1 PIE1 Result written for last CCW in queue 2 CF2 CIE2 Result written for a CCW with pause bit set in queue 2 PF2 PIE2 Queue Activity If interrupts are enabled for an event, the QADC requests interrupt service when the event occurs.
Chapter 28 Reset Controller Module The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the system, and then to keep a history of what caused the reset. The Low Voltage Detection module, which generates low-voltage detect (LVD) interrupts and resets, is implemented within the reset controller module. 28.
Block Diagram 28.2 Block Diagram Figure 28-1 illustrates the reset controller and is explained in the following sections. RSTI Pin Power-On Reset RSTO Pin Watchdog Timer Timeout Reset Controller PLL Loss of Clock To Internal Resets PLL Loss of Lock Software Reset LVD Detect Figure 28-1. Reset Controller Block Diagram 28.3 Signals Table 28-1 provides a summary of the reset controller signal properties. The signals are described in the following paragraphs. Table 28-1.
Memory Map and Registers 28.4 Memory Map and Registers The reset controller programming model consists of these registers: • • Reset control register (RCR), which selects reset controller functions Reset status register (RSR), which reflects the state of the last reset source See Table 28-2 for the memory map and the following paragraphs for a description of the registers. Table 28-2.
Memory Map and Registers Table 28-3. RCR Field Descriptions (continued) Bit(s) Name Description 4 LVDF LVD flag. Indicates the low-voltage detect status if LVDE is set. Write a 1 to clear the LVDF bit. 1 Low voltage has been detected 0 Low voltage has not been detected NOTE: The setting of this flag causes an LVD interrupt if LVDE and LVDIE bits are set and LVDRE is cleared when the supply voltage VDD drops below VDD (minimum). The vector for this interrupt is shared with INT0 of the EPORT module.
Memory Map and Registers Table 28-4. RSR Field Descriptions Bit(s) Name 7 — 6 LVD Low voltage detect. Indicates that the last reset state was caused by an LVD reset. 1 Last reset state was caused by an LVD reset 0 Last reset state was not caused by an LVD reset 5 SOFT Software reset flag. Indicates that the last reset was caused by software. 1 Last reset caused by software 0 Last reset not caused by software 4 WDR Watchdog timer reset flag.
Functional Description 28.5 Functional Description 28.5.1 Reset Sources Table 28-5 defines the sources of reset and the signals driven by the reset controller. Table 28-5.
Functional Description 28.5.1.2 External Reset Asserting the external RSTI for at least four rising CLKOUT edges causes the external reset request to be recognized and latched. The bus monitor is enabled and the current bus cycle is completed. The reset controller asserts RSTO for approximately 512 cycles after RSTI is negated and the PLL has acquired lock. The part then exits reset and begins operation. In low-power stop mode, the system clocks are stopped.
Functional Description 28.5.2 Reset Control Flow The reset logic control flow is shown in Figure 28-4. In this figure, the control state boxes have been numbered, and these numbers are referred to (within parentheses) in the flow description that follows. All cycle counts given are approximate.
Functional Description 0 1 LOSS OF CLOCK? POR OR LVD Y N 2 Y LOSS OF LOCK? 5 ENABLE BUS MONITOR N 3 RSTI PIN OR WD TIMEOUT OR SW RESET? Y 6 BUS CYCLE COMPLETE? N N 4 ASSERT RSTO AND LATCH RESET STATUS Y 7 ASSERT RSTO AND LATCH RESET STATUS 8 N RSTI NEGATED? Y 9 PLL MODE? Y 9A PLL LOCKED? Y N 10 12 NEGATE RSTO WAIT 512 CLKOUT CYCLES 11A 11 RCON ASSERTED? Y LATCH CONFIGURATION N Figure 28-4. Reset Control Flow MOTOROLA Chapter 28.
Functional Description 28.5.2.1 Synchronous Reset Requests In this discussion, the reference in parentheses refer to the state numbers in Figure 28-4. All cycle counts given are approximate. If the external RSTI signal is asserted by an external device for at least four rising CLKOUT edges (3), if the watchdog timer times out, or if software requests a reset, the reset control logic latches the reset request internally and enables the bus monitor (5).
Functional Description If a loss-of-clock or loss-of-lock condition is detected while waiting for the current bus cycle to complete (5, 6) for an external reset request, the cycle is terminated. The reset status bits are latched (7) and reset processing waits for the external RSTI pin to negate (8). If a loss-of-clock or loss-of-lock condition is detected during the 512 cycle wait, the reset sequence continues after a PLL lock (9, 9A). 28.5.3.
Functional Description 28-12 MCF5282 User’s Manual MOTOROLA
Chapter 29 Debug Support This chapter describes the Revision A enhanced hardware debug support in the MCF5282. 29.1 Overview The debug module is shown in Figure 29-1. High-speed local bus ColdFire CPU Core Debug Module Control BKPT Trace Port PST[3:0], DDATA[3:0] CLKOUT Communication Port DSCLK, DSI, DSO Figure 29-1.
Signal Description systems can access saved data because the hardware supports concurrent operation of the processor and BDM-initiated commands. See Section 29.6, “Real-Time Debug Support.” NOTE Enabling Flash security will disable BDM communications. 29.2 Signal Description Table 29-1 describes debug module signals. All ColdFire debug signals are unidirectional and related to a rising edge of the processor’s clock signal. The standard 26-pin debug connector is shown in Section 29.
Real-Time Trace Support 29.3 Real-Time Trace Support Real-time trace, which defines the dynamic execution path, is a fundamental debug function. The ColdFire solution is to include a parallel output port providing encoded processor status and data to an external development system. This port is partitioned into two 4-bit nibbles: one nibble allows the processor to transmit processor status, (PST), and the other allows operand data to be displayed (debug data, DDATA).
Real-Time Trace Support Table 29-2. Processor Status Encoding (continued) PST[3:0] Hex Binary 0x7 0111 0x8– 0xB Definition Begin execution of return from exception (RTE) instruction. 1000–1 Indicates the number of bytes to be displayed on the DDATA port on subsequent processor clock cycles. The 011 value is driven onto the PST port one CLKOUT cycle before the data is displayed on DDATA. 0x8 Begin 1-byte transfer on DDATA. 0x9 Begin 2-byte transfer on DDATA. 0xA Begin 3-byte transfer on DDATA.
Programming Model Another example of a variant branch instruction would be a JMP (A0) instruction. Figure 29-3 shows the PST and DDATA outputs that indicate a JMP (A0) execution (assuming the CSR was programmed to display the lower 2 bytes of an address). CLKOUT PST 0x5 0x9 default default default default DDATA 0x0 0x0 A[3:0] A[7:4] A[11:8] A[15:12] Figure 29-3. Example JMP Instruction Output on PST/DDATA PST 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address.
Programming Model 31 31 31 31 31 31 15 7 15 0 AATR Address attribute trigger register ABLR ABHR Address low breakpoint register Address high breakpoint register CSR Configuration/status register DBR DBMR Data breakpoint register Data breakpoint mask register PBR PBMR PC breakpoint register PC breakpoint mask register TDR Trigger definition register 0 15 0 15 0 15 0 15 0 Note: Each debug register is accessed as a 32-bit register; shaded fields above are not used (don’t care).
Programming Model Table 29-3. BDM/Breakpoint Registers DRc[4–0] 0x00 Register Name Configuration/status register 0x01–0x05 Abbreviation Initial State Page CSR 0x00010_0000 p. 29-10 — — — Reserved 0x06 Address attribute trigger register AATR 0x0000_0005 p. 29-8 0x07 Trigger definition register TDR 0x0000_0000 p. 29-14 0x08 Program counter breakpoint register PBR — p. 29-13 0x09 Program counter breakpoint mask register PBMR — p.
Programming Model 29.4.2 Address Attribute Trigger Register (AATR) The AATR, shown in Figure 29-5, defines address attributes and a mask to be matched in the trigger. The register value is compared with address attribute signals from the processor’s local high-speed bus, as defined by the setting of the trigger definition register (TDR). 15 Field RM 14 13 SZM 12 11 TTM Reset 10 8 7 TMM 6 R 5 SZ 4 3 2 0 TT TM 0000_0000_0000_0101 R/W Write only.
Programming Model Table 29-5. AATR Field Descriptions (continued) Bits Name 2–0 TM Description Transfer modifier. Compared with the local bus transfer modifier signals, which give supplemental information for each transfer type.
Programming Model Table 29-6 describes ABLR fields. Table 29-6. ABLR Field Description Bits Name 31–0 Address Description Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range. Breakpoints for specific addresses are programmed into ABLR. Table 29-7 describes ABHR fields. Table 29-7. ABHR Field Description Bits Name 31–0 Address Description High address. Holds the 32-bit address marking the upper bound of the address breakpoint range. 29.4.
Programming Model Table 29-8 describes CSR fields. Table 29-8. CSR Field Descriptions Bit 31–28 Name Description BSTAT Breakpoint status. Provides read-only status information concerning hardware breakpoints. BSTAT is cleared by a TDR write or by a CSR read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and the level-2 breakpoint is disabled.
Programming Model Table 29-8. CSR Field Descriptions (continued) Bit Name 7 — 6 NPL 5 IPI 4 SSM 3–0 — Description Reserved, should be cleared. Non-pipelined mode. Determines whether the core operates in pipelined or mode or not. 0 Pipelined mode 1 Nonpipelined mode. The processor effectively executes one instruction at a time with no overlap. This adds at least 5 cycles to the execution time of each instruction. Given an average execution latency of 1.
Programming Model Table 29-9 describes DBR fields. Table 29-9. DBR Field Descriptions Bits Name Description 31–0 Data Data breakpoint value. Contains the value to be compared with the data value from the processor’s local bus as a breakpoint trigger. Table 29-10 describes DBMR fields. Table 29-10. DBMR Field Descriptions Bits Name 31–0 Mask Description Data breakpoint mask. The 32-bit mask for the data breakpoint trigger.
Programming Model 31 0 Field Program Counter Reset — R/W Write. PC breakpoint register is accessible in supervisor mode using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands using values shown in Section 29.5.3.3, “Command Set Descriptions.” DRc[4–0] 0x08 Figure 29-9. Program Counter Breakpoint Register (PBR) Table 29-12 describes PBR fields. Table 29-12. PBR Field Descriptions Bits Name 31–0 Address Description PC breakpoint address.
Programming Model NOTE: The debug module has no hardware interlocks, so to prevent spurious breakpoint triggers while the breakpoint registers are being loaded, disable TDR (by clearing TDR[29,13])before defining triggers. A write to TDR clears the CSR trigger status bits, CSR[BSTAT].
Background Debug Mode (BDM) Table 29-14. TDR Field Descriptions (continued) Bits Name 28–22/ 12–6 EDx Description Setting an EDx bit enables the corresponding data breakpoint condition based on the size and placement on the processor’s local data bus. Clearing all EDx bits disables data breakpoints. 28/12 EDLW Data longword. Entire processor’s local data bus. 27/11 EDWL Lower data word. 26/10 EDWU Upper data word. 25/9 EDLL Lower lower data byte. Low-order byte of the low-order word.
Background Debug Mode (BDM) 1. A catastrophic fault-on-fault condition automatically halts the processor. 2. A hardware breakpoint can be configured to generate a pending halt condition similar to the assertion of BKPT. This type of halt is always first made pending in the processor. Next, the processor samples for pending halt and interrupt conditions once per instruction. When a pending condition is asserted, the processor halts execution at the next sample point. See Section 29.6.
Background Debug Mode (BDM) 29.5.2 BDM Serial Interface When the CPU is halted and PST reflects the halt status, the development system can send unrestricted commands to the debug module. The debug module implements a synchronous protocol using two inputs (DSCLK and DSI) and one output (DSO), where DSO is specified as a delay relative to the rising edge of the processor clock. See Table 29-1. The development system serves as the serial communication channel master and must generate DSCLK.
Background Debug Mode (BDM) NOTE: A not-ready response can be ignored except during a memory-referencing cycle. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. 29.5.2.1 Receive Packet Format The basic receive packet, Figure 29-13, consists of 16 data bits and 1 status bit . 16 15 0 S Data Field [15:0] Figure 29-13. Receive BDM Packet Table 29-15 describes receive BDM packet fields. Table 29-15.
Background Debug Mode (BDM) 29.5.3 BDM Command Set Table 29-17 summarizes the BDM command set. Subsequent paragraphs contain detailed descriptions of each command. Issuing a BDM command when the processor is accessing debug module registers using the WDEBUG instruction causes undefined behavior. Table 29-17. BDM Command Summary Command (Hex) CPU State 1 Section Read the selected address or data register and return the results through the serial interface. Halted 29.5.3.3.
Background Debug Mode (BDM) 29.5.3.1 ColdFire BDM Command Format All ColdFire Family BDM commands include a 16-bit operation word followed by an optional set of one or more extension words, as shown in Figure 29-15. 15 10 Operation 9 8 0 R/W 7 6 5 4 3 Op Size 0 0 A/D 2 0 Register Extension Word(s) Figure 29-15. BDM Command Format Table 29-18 describes BDM fields. Table 29-18.
Background Debug Mode (BDM) 29.5.3.2 Command Sequence Diagrams The command sequence diagram in Figure 29-16 shows serial bus traffic for commands. Each bubble represents a 17-bit bus transfer. The top half of each bubble indicates the data the development system sends to the debug module; the bottom half indicates the debug module’s response to the previous development system commands. Command and result transactions overlap to minimize latency.
Background Debug Mode (BDM) • • At the completion of cycle 3, the debug module initiates a memory read operation. Any serial transfers that begin during a memory access return a not-ready response. Results are returned in the two serial transfer cycles after the memory access completes. For any command performing a byte-sized memory read operation, the upper 8 bits of the response data are undefined and the referenced data is returned in the lower 8 bits.
Background Debug Mode (BDM) 29.5.3.3.2 Write A/D Register (WAREG/WDREG) The operand longword data is written to the specified address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted. Command Format: 15 12 11 0x2 8 7 0x0 4 0x8 3 A/D 2 0 Register D[31:16] D[15:0] Figure 29-19.
Background Debug Mode (BDM) Command/Result Formats: 15 Byte 12 Command 11 8 0x1 7 0x9 4 3 0x0 0 0x0 A[31:16] A[15:0] Result Word X Command X X X X X 0x1 X X 0x9 D[7:0] 0x4 0x0 0x8 0x0 A[31:16] A[15:0] Result D[15:0] Longword Command 0x1 0x9 A[31:16] A[15:0] Result D[31:16] D[15:0] Figure 29-21.
Background Debug Mode (BDM) 29.5.3.3.4 Write Memory Location (WRITE) Write data to the memory location specified by the longword address. The address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned.
Background Debug Mode (BDM) Command Sequence: WRITE (B/W) ??? MS ADDR ’NOT READY’ LS ADDR ’NOT READY’ DATA ’NOT READY’ WRITE MEMORY LOCATION XXX ’NOT READY’ NEXT CMD ’CMD COMPLETE’ XXX BERR NEXT CMD ’NOT READY’ WRITE (LONG) ??? MS ADDR ’NOT READY’ LS ADDR ’NOT READY’ MS DATA ’NOT READY’ LS DATA ’NOT READY’ WRITE MEMORY LOCATION XXX ’NOT READY’ NEXT CMD ’CMD COMPLETE’ XXX BERR NEXT CMD ’NOT READY’ Figure 29-24.
Background Debug Mode (BDM) NOTE: DUMP does not check for a valid address; it is a valid command only when preceded by NOP, READ, or another DUMP command. Otherwise, an illegal command response is returned. NOP can be used for intercommand padding without corrupting the address pointer. The size field is examined each time a DUMP command is processed, allowing the operand size to be dynamically altered.
Background Debug Mode (BDM) Command Sequence: READ MEMORY LOCATION DUMP (B/W) ??? XXX ’NOT READY’ NEXT CMD RESULT XXX ’ILLEGAL’ NEXT CMD ’NOT READY’ READ MEMORY LOCATION DUMP (LONG) ??? XXX ’ILLEGAL’ XXX BERR NEXT CMD ’NOT READY’ XXX ’NOT READY’ NEXT CMD MS RESULT NEXT CMD LS RESULT XXX BERR NEXT CMD ’NOT READY’ NEXT CMD ’NOT READY’ Figure 29-26. DUMP Command Sequence Operand Data: None Result Data: Requested data is returned as either a word or longword.
Background Debug Mode (BDM) The size field is examined each time a FILL command is processed, allowing the operand size to be altered dynamically. Command Formats: 15 12 Byte 11 8 0x1 X X Word 7 4 0xC X X X X 0x1 3 0 0x0 X 0x0 X D[7:0] 0xC 0x4 0x0 0x8 0x0 D[15:0] Longword 0x1 0xC D[31:16] D[15:0] Figure 29-27.
Background Debug Mode (BDM) 29.5.3.3.7 Resume Execution (GO) The pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC and at the current privilege level. If any register (such as the PC or SR) is altered by a BDM command while the processor is halted, the updated value is used when prefetching resumes. If a GO command is issued and the CPU is not halted, the command is ignored.
Background Debug Mode (BDM) 29.5.3.3.9 Read Control Register (RCREG) Reads the selected control register and returns the 32-bit result. Accesses to the processor/memory control registers are always 32 bits wide, regardless of register width. The second and third words of the command form a 32-bit address, which the debug module uses to generate a special bus cycle to access the specified control register. The 12-bit Rc field is the same as that used by the MOVEC instruction.
Background Debug Mode (BDM) Command Sequence: RCREG ??? MS ADDR ’NOT READY’ MS ADDR ’NOT READY’ READ CONTROL REGISTER XXX ’NOT READY’ NEXT CMD MS RESULT NEXT CMD LS RESULT XXX BERR NEXT CMD ’NOT READY’ Figure 29-34. RCREG Command Sequence Operand Data: The only operand is the 32-bit Rc control register select field. Result Data: Control register contents are returned as a longword, most-significant word first.
Background Debug Mode (BDM) As an example, any BDM read of an accumulator register (ACCn) must be preceded by two commands accessing the MAC status register.
Background Debug Mode (BDM) Command Sequence: WCREG ??? MS ADDR ’NOT READY’ MS ADDR ’NOT READY’ MS DATA ’NOT READY’ LS DATA ’NOT READY’ WRITE CONTROL REGISTER XXX ’NOT READY’ NEXT CMD ’CMD COMPLETE’ XXX BERR NEXT CMD ’NOT READY’ Figure 29-36. WCREG Command Sequence Operand Data: This instruction requires two longword operands. The first selects the register to which the operand data is to be written; the second contains the data. Result Data: Successful write operations return 0xFFFF.
Background Debug Mode (BDM) Table 29-20. Definition of DRc Encoding—Read DRc[4:0] Debug Register Definition Mnemonic Initial State Page 0x00 Configuration/Status CSR 0x0 p. 29-10 0x01–0x1F Reserved — — — Command Sequence: RDMREG ??? XXX MS RESULT NEXT CMD LS RESULT XXX ’ILLEGAL’ NEXT CMD ’NOT READY’ Figure 29-38. RDMREG Command Sequence Operand Data: None Result Data: The contents of the selected debug register are returned as a longword value.
Real-Time Debug Support Operand Data: Longword data is written into the specified debug register. The data is supplied most-significant word first. Result Data: Command complete status (0xFFFF) is returned when register write is complete. 29.6 Real-Time Debug Support The ColdFire Family provides support debugging real-time applications. For these types of embedded systems, the processor must continue to operate during debug.
Real-Time Debug Support recognized on the processor’s local bus, but are made pending to the processor and sampled like other interrupt conditions. As a result, these interrupts are imprecise. In systems that tolerate the processor being halted, a BDM-entry can be used. With TDR[TRC] = 01, a breakpoint trigger causes the core to halt (PST = 0xF). If the processor core cannot be halted, the debug interrupt can be used.
Real-Time Debug Support • Setting CSR[TRC] forces the processor into emulation mode when trace exception processing begins. While operating in emulation mode, the processor exhibits the following properties: • • All interrupts are ignored, including level-7 interrupts. If CSR[MAP] = 1, all caching of memory and the SRAM module are disabled. All memory accesses are forced into a specially mapped address space signaled by TT = 0x2, TM = 0x5 or 0x6.
Processor Status, DDATA Definition 29.7 Processor Status, DDATA Definition This section specifies the ColdFire processor and debug module’s generation of the processor status (PST) and debug data (DDATA) output on an instruction basis. In general, the PST/DDATA output for an instruction is defined as follows: PST = 0x1, {PST = [0x89B], DDATA= operand} where the {...} definition is optional operand information defined by the setting of the CSR.
Processor Status, DDATA Definition Table 29-22. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax bclr #imm,x PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination} bclr Dy,x PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination} bra.
Processor Status, DDATA Definition Table 29-22. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax move.w {Dy,#imm},CCR movem.l #list,x PST = 0x1, {PST = 0xB, DD = destination},... 2 movem.l y,#list PST = 0x1, {PST = 0xB, DD = source},... 2 moveq #imm,Dx PST = 0x1 muls.l y,Dx PST = 0x1, {PST = 0xB, DD = source operand} muls.w y,Dx PST = 0x1, {PST = 0x9, DD = source operand} mulu.
Processor Status, DDATA Definition Table 29-22. PST/DDATA Specification for User-Mode Instructions (continued) Instruction Operand Syntax PST/DDATA wddata.b y PST = 0x4, {PST = 0x8, DD = source operand wddata.l y PST = 0x4, {PST = 0xB, DD = source operand wddata.w y PST = 0x4, {PST = 0x9, DD = source operand 1 For JMP and JSR instructions, the optional target instruction address is displayed only for those effective address fields defining variant addressing modes.
Processor Status, DDATA Definition Table 29-23. PST/DDATA Specification for MAC Instructions (continued) Instruction Operand Syntax PST/DDATA move.l Accy,Rx PST = 0x1 move.l MACSR,CCR PST = 0x1 move.l MACSR,Rx PST = 0x1 move.l MASK,Rx PST = 0x1 move.l Accext01,Rx PST = 0x1 move.l Accext23,Rx PST = 0x1 msac.l Ry,Rx,Accx PST = 0x1 msac.l Ry,Rx,,Rw,Accx msac.w Ry,Rx,Accx msac.
Motorola-Recommended BDM Pinout 29.8 Motorola-Recommended BDM Pinout The ColdFire BDM connector, Figure 29-41, is a 26-pin Berg connector arranged 2 x 13.
Motorola-Recommended BDM Pinout 29-46 MCF5282 User’s Manual MOTOROLA
Chapter 30 Chip Configuration Module (CCM) The chip configuration module (CCM) controls the chip configuration and mode of operation for the MCF5282. 30.1 Features The CCM performs these operations.
Block Diagram 30.2.1 Master Mode In master mode, the central processor unit (CPU) can access external memories and peripherals. The external bus consists of a 32-bit data bus and 24 address lines. The available bus control signals include R/W, TS, TIP, TSIZ[1:0], TA, TEA, OE, and BS[3:0]. Up to seven chip selects can be programmed to select and control external devices and to provide bus cycle termination.
Signal Descriptions 30.4 Signal Descriptions Table 30-1 provides an overview of the CCM signals. Table 30-1. Signal Properties Name Function Reset State RCON Reset configuration select CLKMOD[1:0] Clock mode select — D[26:24, 21, 19:16] Reset configuration override pins — Internal weak pull-up device 30.4.
Memory Map and Registers Some control register bits are implemented as write-once bits. These bits are always readable, but once the bit has been written, additional writes have no effect, except during debug and test operations. Some write-once bits can be read and written while in debug mode. When debug mode is exited, the chip configuration module resumes operation based on the current register values.
Memory Map and Registers 30.5.3 Register Descriptions The following subsection describes the CCM registers. 30.5.3.1 Chip Configuration Register (CCR) 15 14 11 Field LOAD 10 — 8 MODE Reset 7 — 6 5 SZEN PSTEN 4 3 — BME 2 0 BMT See Note R/W R/W Read Only Address R/W IPSBAR + 0x11_0004 Note: The reset value of the LOAD and MODE fields is determined during reset configuration. The SZEN is set for master mode and cleared for all other configurations.
Memory Map and Registers Table 30-4. CCR Field Descriptions (continued) Bits Name 3 BME Bus monitor enable. This read/write bit enables the bus monitor to operate during external bus cycles. 0 Bus monitor disabled for external bus cycles. 1 Bus monitor enabled for external bus cycles. Table 30-2 shows the read/write accessibility of this write-once bit. 2–0 BMT Bus monitor timing. This field selects the timeout period (in system clocks) for the bus monitor.
Memory Map and Registers Table 30-5. RCON Field Descriptions (continued) Bits Name Description 6 RPLLREF 5 RLOAD Pad driver load. Reflects the default pad driver strength configuration. 0 Partial drive strength 1 Full drive strength (This is the value used for the MCF5282.) 4–3 BOOTPS Boot port size. Reflects the default selection for the boot port size if the boot device is configured to be external. Table 30-7 shows the different port configurations for BOOTPS.
Functional Description 30.5.3.3 Chip Identification Register (CIR) 15 8 Field 7 0 PIN PRN Reset 0010_0000_0000_0000 R/W R Address IPSBAR + 0x11_000a Figure 30-4. Chip Identification Register (CIR) Table 30-8. CIR Field Description Bits Name Description 15–8 PIN Part identification number. Contains a unique identification number for the device. 7–0 PRN Part revision number. This number is increased by one for each new full-layer mask set of this part.
Functional Description Table 30-9.
Functional Description Table 30-10.
Functional Description Table 30-11. Chip Configuration Mode Selection 1 Chip Configuration Mode 1 CCR Register MODE Field MODE2 MODE1 MODE0 Master mode D26 driven high D17 driven high D16 driven high Single-chip mode D26 driven high D17 driven high D16 driven low Reserved D26 driven high D17 driven low D16 driven high Reserved D26 driven low D17 don’t care D16 don’t care Modifying the default configurations is possible only if the external RCON pin is asserted low.
Reset Table 30-13. Clock Mode Selection 1 Synthesizer Status Register (SYNSR) Clock Mode PLLSEL Bit PLLREF Bit PLLMOD External clock mode; PLL disabled 0 0 0 1:1 PLL mode 0 0 1 Normal PLL mode; external clock reference 1 0 1 Normal PLL mode; crystal oscillator reference 1 1 1 1Modifying the default configurations is possible only if the external RCON pin is asserted low. 30.6.
Chapter 31 IEEE 1149.1 Test Access Port (JTAG) The Joint Test Action Group, or JTAG, is a dedicated user-accessible test logic, that complies with the IEEE 1149.1 standard for boundary-scan testability, to help with system diagnostic and manufacturing testing. This architecture provides access to all data and chip control pins from the board-edge connector through the standard four-pin test access port (TAP) and the JTAG reset pin, TRST. Figure 31-1 shows the block diagram of the JTAG module.
Features TAP CONTROLLER 1-BIT BYPASS REGISTER TDI/DSI 147 0 148-BIT BOUNDARY SCAN REGISTER 31 0 32-BIT IDCODE REGISTER 1 6 0 7-BIT JTAG_CFM_CLKDIV REGISTER 2 TDO/DSO 0 0 3-BIT TEST_CTRL REGISTER 4-BIT TAP INSTRUCTION DECODER 3 0 4-BIT TAP INSTRUCTION REGISTER JTAG_EN TCLK TMS/BKPT TRST/DSCLK Disable DSCLK Force BKPT = 1 DSI = 0 1 0 JTAG Module to Debug Module DSO DSI BKPT DSCLK Figure 31-1. JTAG Block Diagram 31.
Modes of Operation 31.2 Modes of Operation The JTAG_EN pin can select between the following modes of operation: • • JTAG mode BDM - background debug mode (For more information, refer to Section 29.5, “Background Debug Mode (BDM)).” 31.3 External Signal Description The JTAG module has five input and one output external signals, as described in Table 31-1. 31.3.1 Detailed Signal Description Table 31-1.
External Signal Description Table 31-3. Signal State to the Disable Module JTAG_EN = 0 JTAG_EN = 1 Disabling JTAG TRST = 0 TMS = 1 — Disabling BDM — Disable DSCLK DSI = 0 BKPT = 1 NOTE The JTAG_EN does not support dynamic switching between JTAG and BDM modes. 31.3.1.2 TCLK — Test Clock Input The TCLK pin is a dedicated JTAG clock input to synchronize the test logic. Pulses on TCLK shift data and instructions into the TDI pin on the rising edge and out of the TDO pin on the falling edge.
Memory Map/Register Definition 31.3.1.6 TDO/DSO — Test Data Output / Development Serial Output The TDO pin is the LSB-first data output. Data is clocked out of TDO on the falling edge of TCLK. TDO is tri-stateable and is actively driven in the shift-IR and shift-DR controller states. The DSO pin provides serial output data in BDM mode. 31.4 Memory Map/Register Definition 31.4.1 Memory Map The JTAG module registers are not memory mapped and are only accessible through the TDO/DSO pin. 31.4.
Memory Map/Register Definition Table 31-4. IDCODE Register Field Descriptions Bits Name 31–28 PRN 27–22 DC Design center. 21–12 PIN Part identification number. Indicate the device number. 11–1 0 Description Part revision number. Indicate the revision number of the project. JEDEC Joint electron device engineering council ID bits. Indicate the reduced JEDEC ID for Motorola. ID IDCODE register ID.
Functional Description 31.5 Functional Description 31.5.1 JTAG Module The JTAG module consists of a TAP controller state machine, which is responsible for generating all control signals that execute the JTAG instructions and read/write data registers. 31.5.2 TAP Controller The TAP controller is a state machine that changes state based on the sequence of logical values on the TMS pin. Figure 31-3 shows the machine’s states.
Functional Description 1 TEST-LOGIC-RESET 0 0 RUN-TEST/IDLE 1 SELECT DR-SCAN SELECT IR-SCAN 1 1 CAPTURE-DR 1 CAPTURE-IR 0 0 0 SHIFT-DR 1 EXIT1-DR 1 EXIT1-IR 1 1 0 0 0 PAUSE-DR 0 PAUSE-IR 1 1 EXIT2-DR EXIT2-IR 0 1 1 UPDATE-DR 1 0 SHIFT-IR 1 0 1 0 0 UPDATE-IR 0 1 0 Figure 31-3. TAP Controller State Machine Flow 31.5.3 JTAG Instructions Table 31-5 describes public and private instructions. Table 31-5.
Functional Description Table 31-5.
Functional Description contains the $2 opcode. The sampled data is accessible by shifting it through the boundary scan register to the TDO output by using the shift-DR state. Both the data capture and the shift operation are transparent to system operation. NOTE External synchronization is required to achieve meaningful results because there is no internal synchronization between TCLK and the system clock. • PRELOAD - initialize the boundary scan register update cells before selecting EXTEST or CLAMP.
Initialization/Application Information contents of the user’s secured code stored in flash gets erased before security is disabled on the MCU on the next reset or power-up sequence. The LOCKOUT_RECOVERY instruction selects a 7-bit shift register for connection as a shift path between the TDI pin and the TDO pin.
Initialization/Application Information Using the EXTEST instruction requires a circuit-board test environment that avoids device-destructive configurations in which MCU output drivers are enabled into actively driven networks. Low-power stop mode considerations: • • • The TAP controller must be in the test-logic-reset state to either enter or remain in the low-power stop mode. Leaving the test-logic-reset state negates the ability to achieve low-power, but does not otherwise affect device functionality.
Chapter 32 Mechanical Data This chapter contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF5282. MOTOROLA Chapter 32.
Pinout 32.1 Pinout Figure 32-1 is a pinout for the MCF5282.
Pinout Table 32-1.
Pinout Table 32-1.
Pinout Table 32-1.
Pinout Table 32-1.
Ordering Information X D Y M LASER MARK FOR PIN A1 IDENTIFICATION IN THIS AREA 5 K A 0.30 Z A2 A1 Z E 256X 4 0.15 Z DETAIL K ROTATED 90°CLOCKWISE M 0.20 15X e S 16151413121110 15X e METALIZED MARK FOR PIN A1 IDENTIFICATION IN THIS AREA 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T S 256X b NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z.
Ordering Information 32-8 MCF5282 User’s Manual MOTOROLA
Chapter 33 Electrical Characteristics This chapter contains electrical specification tables and reference timing diagrams for the MCF5282 microcontroller unit. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of MCF5282. The electrical specifications are preliminary and are from previous designs or design simulations.
Maximum Ratings Table 33-1. Absolute Maximum Ratings1, 2 (Continued) Rating Symbol Value Unit Instantaneous Maximum Current Single pin limit (applies to all pins) 3, 4, 5 ID 25 mA Operating Temperature Range (Packaged) TA – 40 to 85 °C Storage Temperature Range Tstg – 65 to 150 °C Tj 105 oC HBM 2000 V Maximum operating junction temperature ESD Target for Human Body 1 2 3 4 5 6 33-2 Model6 Functional operating conditions are given in DC Electrical Specifications.
Thermal Characteristics 33.2 Thermal Characteristics Table 33-2 lists thermal resistance values. Table 33-2.
DC Electrical Specifications P D = K ÷ ( T J + 273°C ) (2) Solving equations 1 and 2 for K gives: K = PD × (TA + 273 × C) + QJMA × PD 2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. 33.3 DC Electrical Specifications Table 33-3.
DC Electrical Specifications Table 33-3. DC Electrical Specifications1 (Continued) (VSS = VSSPLL= VSSF = VSSA= 0 VDC) Characteristic Operating Supply Current 4 Master Mode • 66 MHz • 80 MHz Single Chip Mode WAIT DOZE STOP Symbol Min Max — — — — — — 200 240 150 15 10 1000 — — — — 4 2 1 10 mA mA mA µA — — — 10 7 20 µA mA µA — — — — 30 64 20 10 mA mA mA µA — — 5.0 10.0 mA µµAµ IDD Clock Synthesizer Supply Current Normal Operation 8.
Phase Lock Loop Electrical Specifications 33.4 Phase Lock Loop Electrical Specifications Table 33-4. PLL Electrical Specifications (VDD and VDDPLL = 2.7 to 3.6 V, VSS = VSSPLL = 0 V) Characteristic PLL Reference Frequency Range Crystal reference External reference 1:1 Mode Symbol Min Max fref_crystal fref_ext fref_1:1 2 2 33.33 10.0 10.
QADC Electrical Characteristics 8 Assuming a reference is available at power up, lock time is measured from the time VDD and VDDPLL are valid to RSTO negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time must be added to the PLL lock time to determine the total start-up time. 9 PLL is operating in 1:1 PLL mode. 10 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys.
QADC Electrical Characteristics Table 33-6. QADC Electrical Specifications (Operating) 1 (Continued) (VDDH and VDDA = 5.0 Vdc ± 0.5V, VDD = 2.7-3.6V, VSS and VSSA = 0 Vdc, FQCLK = 2.0 MHz, TA within operating temperature range) Parameter Symbol Min Max Unit VINDC VSSA–0.3 VDDA + 0.3 V Input High Voltage, PQA and PQB VIH 0.7 (VDDA) VDDA + 0.3 V Input Low Voltage, PQA and PQB VIL VSSA – 0.3 0.4(VDDA) V VHYS 0.5 — V VDDH-0.8 — — — — 5.0 10.
Flash Memory Characteristics Table 33-7. QADC Conversion Specifications (Operating) (VDDH and VDDA = 5.0 Vdc ± 0.5V, VDD= 2.7-3.6V, VSS and VSSA= 0 Vdc, VRH – VRL = 5 Vdc ± 0.5V, TA within operating temperature range, fsys = 16 MHz) Num 1 2 Parameter QADC Clock (QCLK) Frequency1 Conversion Cycles 3 Conversion Time FQCLK = 2.0 MHz1 Min = CCW/IST =%00 Max = CCW/IST =%11 4 Stop Mode Recovery Time 2 5 Resolution 6 Absolute (total unadjusted) error 3, 4, 5 FQCLK = 2.
External Interface Timing Characteristics Table 33-9. SGFM Flash Module Life Characteristics (VDDF = 2.7 to 3.6 V) Parameter Maximum number of guaranteed program/erase cycles1 before failure Data retention at average operating temperature of 85°C 1 2 Symbol Value Unit P/E 10,0002 Cycles Retention 10 Years A program/erase cycle is defined as switching the bits from 1 → 0 → 1. Reprogramming of a Flash array block prior to erase is not required. 33.
Processor Bus Output Timing Specifications Timings listed in Table 33-10 are shown in Figure 33-1. * The timings are also valid for inputs sampled on the negative clock edge. 1.5V CLKOUT(66.67 MHz) TSETUP Input Setup And Hold Invalid THOLD 1.5V Valid 1.5V Invalid trise = 1.5 ns Vh = VIH Input Rise Time Vl = VIL tfall = 1.5 ns Vh = VIH Input Fall Time CLKOUT Vl = VIL B4 B5 Inputs Figure 33-1. General Input Timing Requirements 33.
Processor Bus Output Timing Specifications Table 33-11.
Processor Bus Output Timing Specifications S0 S1 S2 S3 S4 S5 S0 S1 S2 S3 S4 S5 CLKOUT B7a CSn A[23:0] SIZ[1:0] TS B6a B6a B7a B8 B8 B8 B9 B9 B9 B8 TIP B9 B8 B6c B0 B7 OE R/W (H) B6b B6b B7 B7 BS[3:0] D[31:0] B9 B8 B11 B4 B5 B12 B13 TA (H) TEA (H) Figure 33-2. Read/Write (Internally Terminated) Timing Figure 33-3 shows a bus cycle terminated by TA showing timings listed in Table 33-11. MOTOROLA Chapter 33.
Processor Bus Output Timing Specifications S0 S1 S2 S3 S4 S5 S0 S1 CLKOUT CSn A[23:0] B6a B7a B8 B9 SIZ[1:0] B8 TS B9 B8 B9 TIP B6c OE B7 R/W (H) BS[3:0] B6b B7 B5 B4 D[31:0] B2a TA TEA (H) B1a Figure 33-3. Read Bus Cycle Terminated by TA Figure 33-4 shows a bus cycle terminated by TEA; it displays the timings listed in Table 33-11.
Processor Bus Output Timing Specifications S0 S1 S2 S3 S4 S5 S0 S1 CLKOUT CSn A[23:0] B6a B7a B8 B9 SIZ[1:0] B8 B9 TS B8 TIP OE B9 B6c B7 R/W (H) BS[3:0] B6b B7 D[31:0] TA (H) TEA B1a B2a Figure 33-4. Read Bus Cycle Terminated by TEA MOTOROLA Chapter 33.
Processor Bus Output Timing Specifications Figure 33-5 shows an SDRAM read cycle. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 CLKOUT D3 D1 Row A[23:0] Column D4 SRAS D2 SCAS 1 D4 DRAMW D5 D[31:0] D6 SDRAM_CS[1:0] D4 BS[3:0] ACTV NOP 1 DACR[CASL] READ NOP PRE =2 Figure 33-5. SDRAM Read Cycle Table 33-12.
General Purpose I/O Timing Figure 33-6 shows an SDRAM write cycle. 0 1 2 3 4 5 6 7 8 9 10 11 12 CLKOUT D3 D1 Row A[23:0] Column SRAS D2 SCAS1 D4 DRAMW D7 D[31:0] D8 SDRAM_CS[1:0] D2 D4 D4 BS[3:0] D4 ACTV 1 NOP WRITE NOP PALL DACR[CASL] = 2 Figure 33-6. SDRAM Write Cycle 33.9 General Purpose I/O Timing Table 33-13. GPIO Timing1, 2 (VDD = 2.7 to 3.
Reset and Configuration Override Timing Table 33-13. GPIO Timing1, 2 (Continued) (VDD = 2.7 to 3.6 V, VSS = 0 V, VDDH = 5 V) NUM Characteristic Symbol Min Max Unit G1a G2a CLKOUT High to PQA/PQB Output Valid tCHPAOV — 12 ns CLKOUT High to PQA/PQB Output Invalid tCHPAOI 2 — ns PQA/PQB Input Valid to CLKOUT Low tPAVCH 10 — ns CLKOUT Low to PQA/PQB Input Invalid tCHPAI 2 — ns G3a G4a 1 2 GPIO pins include: Ports A-I, INT, SPI, SCI1/2 (including SCI functions), FlexCAN and Timer.
I2C Input/Output Timing Specifications Table 33-14. Reset and Configuration Override Timing (Continued) (VDD = 2.7 to 3.6 V, VSS = 0 V)1 NUM 1 2 Characteristic Symbol Min Max Unit tROVCV 0 — ns R5 RSTO valid to Config.
Fast Ethernet AC Timing Specifications Table 33-16 lists specifications for the I2C output timing parameters shown in Figure 33-9. Table 33-16. I2C Output Timing Specifications between SCL and SDA Num 1 I1 Characteristic Min Max Units Start condition hold time 6 — Bus clocks I2 1 Clock low period 10 — Bus clocks I3 2 SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) — — µS I4 1 Data hold time 7 — Bus clocks I5 3 SCL/SDA fall time (VIH = 2.4 V to VIL = 0.
Fast Ethernet AC Timing Specifications 33.12.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and ERXCLK) The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the ERXCLK frequency. Table 33-17 lists MII receive channel timings. Table 33-17.
Fast Ethernet AC Timing Specifications Table 33-18 lists MII transmit channel timings. Table 33-18. MII Transmit Signal Timing Characteristic1 Num 1 Min Max Unit M5 ETXCLK to ETXD[3:0], ETXEN, ETXER invalid 5 — ns M6 ETXCLK to ETXD[3:0], ETXEN, ETXER valid — 25 ns M7 ETXCLK pulse width high 35% 65% ETXCLK period M8 ETXCLK pulse width low 35% 65% ETXCLK period ETXCLK, ETXD0, and ETXEN have the same timing in 10 Mbit 7-wire interface mode.
Fast Ethernet AC Timing Specifications 33.12.4 MII Serial Management Channel Timing (EMDIO and EMDC) The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. Table 33-20 lists MII serial management channel timings. Table 33-20.
DMA Timer Module AC Timing Specifications 33.13 DMA Timer Module AC Timing Specifications Table 33-21 lists timer module AC timings. Table 33-21. Timer Module AC Timing Specifications Characteristic 1 Name Min Max Unit T1 DTIN0 / DTIN1 / DTIN2 / DTIN3 cycle time 3 — tCYC T2 DTIN0 / DTIN1 / DTIN2 / DTIN3 pulse width 1 — tCYC 1 All timing references to CLKOUT are given to its rising edge when bit 3 of the SDRAM control register is 0. 33.
JTAG and Boundary Scan Timing 33.15 JTAG and Boundary Scan Timing Table 33-23. JTAG and Boundary Scan Timing Characteristics1 Num 1 Symbol Min Max Unit 1 TCLK Frequency of Operation fJCYC DC 1/4 fsys 2 TCLK Cycle Period tJCYC 4 — tCYC 3 TCLK Clock Pulse Width tJCW 25.0 — ns 4 TCLK Rise and Fall Times tJCRF 0.0 3.0 ns 5 Boundary Scan Input Data Setup Time to TCLK Rise tBSDST 5.0 — ns 6 Boundary Scan Input Data Hold Time after TCLK Rise tBSDHT 25.
JTAG and Boundary Scan Timing TCLK VIL VIH 5 Data Inputs 6 Input Data Valid 7 Data Outputs Output Data Valid 8 Data Outputs 7 Data Outputs Output Data Valid Figure 33-16. Boundary Scan (JTAG) Timing TCLK VIL VIH 9 TDI TMS BKPT 10 Input Data Valid 11 TDO Output Data Valid 12 TDO 11 TDO Output Data Valid Figure 33-17. Test Access Port Timing TCLK 14 TRST 13 Figure 33-18.
Debug AC Timing Specifications CLKOUT VIL VIH 15 BKPT (Input) B1b 16 B2b Input Data Valid 17 Figure 33-19. BKPT Timing 33.16 Debug AC Timing Specifications Table 33-24 lists specifications for the debug AC timing parameters shown in Figure 33-21. Table 33-24.
Debug AC Timing Specifications Figure 33-20 shows real-time trace timing for the values in Table 33-24. CLKOUT D1 D2 PST[3:0] DDATA[3:0] Figure 33-20. Real-Time Trace AC Timing Figure 33-21 shows BDM serial port AC timing for the values in Table 33-24. CLKOUT D5 DSCLK D3 DSI Current Next D4 DSO Past Current Figure 33-21.
Appendix A Register Memory Map Table A-1 summarizes the address, name, and byte assignment for registers within the MCF5282 CPU space. Table A-2 lists an overview of the memory map for the on-chip modules, and Table A-3 is a detailed memory map including all of the registers for on-chip modules. Table A-1.
Table A-2.
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A-22 MCF5282 User’s Manual MOTOROLA
INDEX A A/D converter bias, 27-37 block diagram, 27-35 channel decode, 27-36 comparator, 27-37 cycle times, 27-35 multiplexer, 27-36 operation, 27-34 sample buffer, 27-36 state machine, 27-37 successive approximation register (SAR), 27-37 Access error on operand reads, 2-13 on operand writes, 2-14 Acknowledge error (ACKERR), 25-29 Address error exception, 2-14 Address variant, 29-4 Analog inputs, 27-73 Analog power signals, 27-63 Analog reference signals, 27-63 Analog supply filtering, 27-67 grounding, 27-6
INDEX operands, misaligned, 13-14 SACU, 8-14 Bus off interrupt (BOFFINT), 25-30 BUSY, 25-12 BYPASS instruction, 31-11 BYTEREV instruction, 2-30 C Cache block diagram, 4-3 coherency, 4-4 data, 4-1 features, 4-1 fill buffer, 4-2, 4-5 instruction, 4-1 invalidation, 4-4, 4-4 memory map, 4-7 memory reference attributes, 4-4 miss fetch algorithm, 4-5 programming model, 4-7 registers access control 1–0 (ACRn), 2-8, 4-11 control (CACR), 2-8, 4-4, 4-7 reset, 4-5, 4-5 SRAM interaction, 4-3 Channel flags, 20-22 Chip
INDEX writes, 6-17 registers clock divider (CFMCLKD), 6-10 setting, 6-18 command (CFMCMD), 6-16 configuration (CFMCR), 6-9 data access (CFMDACC), 6-14 FLASHBAR, 2-8, 6-5 protection (CFMPROT), 6-12 security (CFMSEC), 6-10 supervisor access (CFMSACC), 6-13 user status (CFMUSTAT), 6-15 reset, 6-24 security back door access, 6-24 erase verify check, 6-24 Collision handling, 17-17 Core hardware configuration, 2-17 low-power modes, 7-7 pipelines, 2-1 programming model, 2-8 supervisor, 2-5 user, 2-2 registers addr
INDEX E Electrical characteristics bus external output timing specifications, 33-11 processor input timing specifications, 33-10 ColdFire Flash module module life characteristics, 33-10 program and erase characteristics, 33-9 DC specifications, 33-4 debug AC timing specifications, 33-27, 33-27 DMA timer AC timing specifications, 33-24 FEC AC timing specifications, 33-20 GPIO timing, 33-17 I2C input timing between SCL and SDA, 33-19 I2C input/output timing specifications, 33-19 I2C output timing between SCL
INDEX (IAUR/IALR), 17-38 descriptor individual upper/lower address (IAUR/IALR), 17-37 FIFO receive bound (FRBR), 17-41 FIFO receive start (FRSR), 17-42 FIFO transmit FIFO watermark (TFWR), 17-40 interrupt event (EIR), 17-23 interrupt mask (EIMR), 17-26 MIB control (MIBC), 17-32 MII management frame (MMFR), 17-29 MII speed control (MSCR), 17-31 opcode/pause duration (OPD), 17-37 physical address low/high (PALR, PAUR), 17-35 receive buffer size (EMRBR), 17-44 receive control (RCR), 17-33 receive descriptor ac
INDEX memory map, 26-6 operation, 26-3 low-power modes, 7-10 overview, 26-1, 26-3 registers port AS pin assignment (PASPAR), 26-19 port B/C/D pin assignment (PBCDPAR), 26-14 port clear output data (CLRn), 26-12 port data direction (DDRn), 26-9 port E pin assignment (PEPAR), 26-15 port EH/EL pin assignment (PEHLPAR), 26-20 port F pin assignment (PFPAR), 26-17 port J pin assignment (PJPAR), 26-18 port output data (PORTn), 26-8 port pin data/set data (PORTnP/SETn), 26-11 port QS pin assignment (PQSPAR), 26-21
INDEX control (I2CR), 24-8 data I/O (I2DR), 24-10 frequency divider (I2FDR), 24-7 status (I2SR), 24-9 software response, 24-11 START generation, 24-11 STOP generation, 24-12 system configuration, 24-3 timing diagrams input/output timing, 33-20 IDCODE instruction, 31-9 Identifier (ID) bits, 25-7 IDLE bit, 25-29 Illegal instruction exception, 2-14 Information processing time (IPT), 25-14 Input capture, 20-17 Instructions additions, 2-9 enhancements BITREV, 2-29 BYTEREV, 2-30 FF1, 2-31 STRLDSR, 2-32 execution
INDEX L Listen-only mode, 25-13 Local loop-back, 23-25 LOCKOUT_RECOVERY instruction, 31-10 Loopback, internal and external, 17-17 Lowest buffer transmitted first (LBUF), 25-24 Low-power modes doze, 7-6 peripheral behavior chip configuration module, 7-11 chip select module, 7-8 clock module, 7-11 ColdFire Flash module, 7-7, 7-15 core, 7-7 debug, 7-16 DMA controller, 7-8 DMA timers, 7-9 EPORT, 7-12 Ethernet, 7-10 FlexCAN, 7-13 general purpose timers, 7-13 GPIO, 7-10 I2C, 7-9 interrupt controller, 7-10 JTAG, 7
INDEX loss-of-clock alternate clock selection, 9-16 detection, 9-16 reset, 9-16 stop mode, 9-17 loss-of-lock conditions, 9-15 reset, 9-15 multiplication factor divider (MFD), 9-13 operation, 9-12 1-1 mode, 9-2 normal mode, 9-1 phase and frequency detector (PFD), 9-12 voltage control output (VCO), 9-13 Porting code, 2-16 Power management features, 7-1 low-power modes, 7-5 doze, 7-6 peripheral behavior chip configuration module, 7-11 chip select module, 7-8 clock module, 7-11 ColdFire Flash module, 7-7, 7-15
INDEX electrical characteristics absolute maximum ratings, 33-7 operating conversion specifications, 33-9 operating electrical specifications, 33-7 external multiplexing, 27-31 operation, 27-32 options, 27-34 features, 27-1 interrupts operation, 27-75 sources, 27-76 leakage, 27-75 memory map, 27-7 operation continuous-scan, 27-54 externally gated, 27-56 externally triggered, 27-56 periodic timer, 27-57 software-initiated, 27-55 debug mode, 27-3 disabled, 27-50 low-power modes, 7-12 reserved, 27-50 single-sc
INDEX FLASHBAR, 2-8, 6-5 protection (CFMPROT), 6-12 security (CFMSEC), 6-10 supervisor access (CFMSACC), 6-13 user status (CFMUSTAT), 6-15 core address (An), 2-3 condition code (CCR), 2-4, 2-4 data (Dn), 2-3 stack pointer (A7), 2-3, 2-7 status register (SR), 2-6 vector base (VBR), 2-8 debug address attribute trigger (AATR), 29-8 address breakpoint (ABLR, ABHR), 29-9 configuration/status (CSR), 29-10 data breakpoint/mask (DBR, DBMR), 29-12 program counter breakpoint/mask (PBR/PBMR), 29-13 trigger definition
INDEX port J pin assignment (PJPAR), 26-18 port output data (PORTn), 26-8 port pin data/set data (PORTnP/SETn), 26-11 port QS pin assignment (PQSPAR), 26-21 port SD pin assignment (PSDPAR), 26-19 port TC pin assignment (PTCPAR), 26-22 port TD pin assignment (PTDPAR), 26-23 port UA pin assignment (PUAPAR), 26-24 I2C address (I2ADR), 24-6 control (I2CR), 24-8 data I/O (I2DR), 24-10 frequency divider (I2FDR), 24-7 status (I2SR), 24-9 interrupt controller interrupt acknowledge level and priority (IACKLPRn), 10-
INDEX overview, 28-1 registers control (RCR), 28-3 status (RSR), 28-4 requests internal, 28-10 synchronous, 28-10 sources of reset, 28-6 external reset, 28-7 LDV reset, 28-7 loss-of-clock reset, 28-7 loss-of-lock reset, 28-7 power-on reset, 28-6 software reset, 28-7 watchdog timer reset, 28-7 status flags, 28-11 timing diagrams RSTI and configuration override, 33-19 Reset exception, 2-16 RTE instruction, 2-16 Run mode, 7-6 Rx/Tx frames, 25-6 S SACU features, 8-14 overview, 8-14 SAMPLE/PRELOAD instructions,
INDEX clock module CLKMOD1–0, 9-5 clock output (CLKOUT), 9-5, 14-22 EXTAL, 9-4, 14-22 RSTOUTl, 9-5 XTAL, 9-5, 14-22 debug breakpoint (BKPT), 29-2 breakpoint/test mode select (BKPT/TMS), 14-31 CLKOUT, 29-2 debug data (DDATA3–0), 14-32, 29-2 development serial clock (DSCLK), 29-2 development serial clock/test reset (DSCLK/TRST), 14-30 development serial input (DSI), 29-2 development serial input/test data (DSI/TDI), 14-31 development serial output (DSO), 29-2 development serial output/test data (DSO/TDO), 14-
INDEX bank select (SDRAM_CS1–0), 14-21 clock enable (SCKE), 14-21 column address strobe (SCAS), 14-21 row address strobe (SRAS), 14-21 summary, 15-4 write enable (DRAMW), 14-21 single-chip mode, 14-17 TEST, 14-32 UART modules clear-to-send (UCTS1–0), 14-27 receive serial data input (URXD2–0), 14-27 request-to-send (URTS1–0), 14-27 transmit serial data output (UTXD2–0), 14-26 SRAM cache, interaction, 4-3 features, 5-1 initialization, 5-3 operation low-power modes, 7-7 overview, 5-1 power management, 5-4 prog
INDEX automatic echo, 23-25 local loop-back, 23-25 remote loop-back, 23-26 low-power modes, 7-8 multidrop mode, 23-26 receiver, 23-22 transmitter, 23-20 overview, 23-1 programming core interrupts, 23-29 DMA service, 23-29 registers auxiliary control (UACRn), 23-13 baud rate generator (UBG1n/UBG2n), 23-14 input port (UIPn), 23-15 interrupt status/mask (UISRn/UIMRn), 23-13 mode 2–1 (UMRnn), 23-4–23-6 output port command (UOP1n/UOP0n), 23-15 receive buffers (URBn), 23-11 status (USRn), 23-7 transmit buffers (U
