Datasheet

16
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
Figure 5-2. Data Memory Map
5.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The internal data SRAM
access is performed in two clk
CPU
cycles as described in Figure 5-3.
Figure 5-3. On-chip Data SRAM Access Cycles
5.3 EEPROM Data Memory
The ATtiny25/45/85 contains 128/256/512 bytes of data EEPROM memory. It is organized as a separate data
space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000
write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the
EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For details see
“Serial Downloading” on page 151.
5.3.1 EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access times for the EEPROM are given in Table 5-1 on page 21. A self-timing function, however, lets
the user software detect when the next byte can be written. If the user code contains instructions that write the
EEPROM, some precautions must be taken. In heavily filtered power supplies, V
CC
is likely to rise or fall slowly on
Power-up/down. This causes the device for some period of time to run at a voltage lower than specified as mini-
mum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19 for details on how to avoid
problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to “Atomic
Byte Programming” on page 17 and “Split Byte Programming” on page 17 for details on this.
32 Registers
64 I/O Registers
Internal SRAM
(128/256/512 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x0DF/0x015F/0x025F
0x0060
Data Memory
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction