Datasheet

109
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
The 4-bit counter can be both read and written via the data bus, and it can generate an overflow interrupt. Both the
USI Data Register and the counter are clocked simultaneously by the same clock source. This allows the counter
to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note
that when an external clock source is selected the counter counts both clock edges. This means the counter regis-
ters the number of clock edges and not the number of data bits. The clock can be selected from three different
sources: The USCK pin, Timer/Counter0 Compare Match or from software.
The two-wire clock control unit can be configured to generate an interrupt when a start condition has been detected
on the two-wire bus. It can also be set to generate wait states by holding the clock pin low after a start condition is
detected, or after the counter overflows.
15.3 Functional Descriptions
15.3.1 Three-wire Mode
The USI three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the
slave select (SS) pin functionality. However, this feature can be implemented in software, if required. Pin names
used in this mode are DI, DO, and USCK.
Figure 15-2. Three-wire Mode Operation, Simplified Diagram
Figure 15-2 shows two USI units operating in three-wire mode, one as Master and one as Slave. The two USI Data
Registers are interconnected in such way that after eight USCK clocks, the data in each register has been inter-
changed. The same clock also increments the USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or
USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master
device software by toggling the USCK pin via the PORTB register or by writing a one to bit USITC bit in USICR.
SLAVE
MASTER
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DO
DI
USCK
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DO
DI
USCK
PORTxn