Datasheet

106
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
the rising edge of OC1x and OC1x can have different dead time periods. The dead time is adjusted as the number
of prescaled dead time generator clock cycles.
Figure 14-3. The Complementary Output Pair
14.1 Register Description
14.1.1 DTPS1 – Timer/Counter1 Dead Time Prescaler Register 1
The dead time prescaler register, DTPS1 is a 2-bit read/write register.
• Bits 1:0 – DTPS1[1:0]: Dead Time Prescaler
The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the Timer/Counter1 clock (PCK
or CK) by 1, 2, 4 or 8 providing a large range of dead times that can be generated. The Dead Time prescaler is
controlled by two bits DTPS1[1:0] from the Dead Time Prescaler register. These bits define the division factor of
the Dead Time prescaler. The division factors are given in table 46.
OC1x
x = A or B
t
non-overlap / rising edge
t
non-overlap / falling edge
OC1x
PWM1x
Bit 76543210
0x23
DTPS11 DTPS10 DTPS1
Read/Write R R R R R R R/W R/W
Initial value 0 0 0 0 0 0 0 0
Table 14-1. Division factors of the Dead Time prescaler
DTPS11 DTPS10 Prescaler divides the T/C1 clock by
0 0 1x (no division)
012x
104x
118x