Atmel 8-bit AVR Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny25/V / ATtiny45/V / ATtiny85/V Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-volatile Program and Data Memories – 2/4/8K Bytes of In-System Programmable Program Memory Flash • Endurance: 10,000 Write/Erase Cycles – 128/25
1. Pin Configurations Figure 1-1.
Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in “Alternate Functions of Port B” on page 60. On ATtiny25, the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged in ATtiny15 Compatibility Mode for supporting the backward compatibility with ATtiny15. 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled.
2. Overview The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1.
The ATtiny25/45/85 provides the following features: 2/4/8K bytes of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes.
3. About 3.1 Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.
4. AVR CPU Core 4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 4-1.
ands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory.
4.4.1 SREG – AVR Status Register The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 0x3F I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
4.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
Figure 4-3. The X-, Y-, and Z-registers 15 X-register XH XL 7 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.
Figure 4-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-5.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.
A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.
5. AVR Memories This section describes the different memories in the ATtiny25/45/85. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny25/45/85 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 5.1 In-System Re-programmable Flash Program Memory The ATtiny25/45/85 contains 2/4/8K bytes On-chip In-System Reprogrammable Flash memory for program storage.
Figure 5-2. Data Memory Map Data Memory 32 Registers 64 I/O Registers 0x0000 - 0x001F 0x0020 - 0x005F 0x0060 Internal SRAM (128/256/512 x 8) 0x0DF/0x015F/0x025F 5.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 5-3. Figure 5-3.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. 5.3.2 Atomic Byte Programming Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the user must write the address into the EEAR Register and data into EEDR Register.
The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details.
5.5.3 EEDR – EEPROM Data Register Bit 7 6 5 4 3 2 1 0 EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0x1D EEDR • Bits 7:0 – EEDR[7:0]: EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 5.
• Bit 1 – EEPE: EEPROM Program Enable The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM. When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.
6. System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 34. The clock systems are detailed below. Figure 6-1.
6.1.4 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 6.1.5 Internal PLL for Fast Peripheral Clock Generation - clkPCK The internal PLL in ATtiny25/45/85 generates a clock frequency that is 8x multiplied from a source input. By default, the PLL uses the output of the internal, 8.0 MHz RC oscillator as source.
Figure 6-3. PCK Clocking System in ATtiny15 Compatibility Mode. OSCCAL PLLE PLL 8x 1/2 25.6 MHz PCK 3.2 MHz LOCK DETECTOR 6.4 MHz OSCILLATOR 1/4 1.6 MHz PLOCK SYSTEM CLOCK Note that low speed mode is not implemented in ATtiny15 compatibility mode. 6.2 Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 6-1.
6.2.1 External Clock To drive the device from an external clock source, CLKI should be driven as shown in Figure 6-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “00”. Figure 6-4. External Clock Drive Configuration EXTERNAL CLOCK SIGNAL CLKI GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-3. Table 6-3.
Table 6-5. 6.2.3 Start-up Times for the High Frequency PLL Clock SUT[1:0] Start-up Time from Power Down Additional Delay from Power-On Reset (VCC = 5.0V) Recommended usage 01 14CK + 16K (16384) CK + 4 ms 4 ms Fast rising power 10 14CK + 1K (1024) CK + 64 ms 4 ms Slowly rising power 11 14CK + 16K (16384) CK + 64 ms 4 ms Slowly rising power Calibrated Internal Oscillator By default, the Internal RC Oscillator provides an approximate 8.0 MHz clock.
When the calibrated 8 MHz internal oscillator is selected as clock source the start-up times are determined by the SUT Fuses as shown in Table 6-7 below. Table 6-7. SUT[1:0] Start-up Times for Internal Calibrated RC Oscillator Clock Start-up Time from Power-down Additional Delay from Reset (VCC = 5.0V) Recommended Usage 00 6 CK 01 6 CK 14CK + 4 ms Fast rising power 6 CK 14CK + 64 ms Slowly rising power (2) 10 11 Note: 14CK (1) BOD enabled Reserved 1.
Note: 6.2.5 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to ensure programming mode can be entered. Low-Frequency Crystal Oscillator To use a 32.768 kHz watch crystal as the clock source for the device, the Low-frequency Crystal Oscillator must be selected by setting CKSEL fuses to ‘0110’. The crystal should be connected as shown in Figure 6-5. To find suitable load capacitance for a 32.768 kHz crysal, please consult the manufacturer’s datasheet.
ment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 6-12 below. For ceramic resonators, the capacitor values given by the manufacturer should be used. Table 6-12. Crystal Oscillator Operating Modes CKSEL[3:1] Frequency Range (MHz) Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) 100(1) 0.4 - 0.9 – 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 12 - 22 Notes: 1.
6.3 System Clock Prescaler The ATtiny25/45/85 system clock can be divided by setting the “CLKPR – Clock Prescale Register” on page 32. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 6-15 on page 33. 6.3.
To ensure stable operation of the MCU the calibration value should be changed in small. A variation in frequency of more than 2% from one cycle to the next can lead to unpredicatble behavior. Changes in OSCCAL should not exceed 0x20 for each calibration. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency Table 6-14. 6.5.
chosen if the selcted clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 6-15.
7. Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.
7.1.2 ADC Noise Reduction Mode When the SM[1:0] bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the Watchdog to continue operating (if enabled). This sleep mode halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run. This improves the noise environment for the ADC, enabling higher resolution measurements.
7.2.1 Limitations BOD disable functionality has been implemented in the following devices, only: • ATtiny25, revision E, and newer • ATtiny45, revision D, and newer • ATtiny85, revision C, and newer Revisions are marked on the device package and can be located as follows: • Bottom side of packages 8P3 and 8S2 • Top side of package 20M1 7.
7.4.4 Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately.
write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. • Bits 4:3 – SM[1:0]: Sleep Mode Select Bits 1 and 0 These bits select between the three available sleep modes as shown in Table 7-2. Table 7-2. Sleep Mode Select SM1 SM0 Sleep Mode 0 0 Idle 0 1 ADC Noise Reduction 1 0 Power-down 1 1 Reserved • Bit 2 – BODSE: BOD Sleep Enable BOD disable functionality is available in some devices, only.
8. System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 8-1 shows the reset logic.
8.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in “System and Reset Characteristics” on page 165. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on.
Figure 8-4. External Reset During Operation CC 8.2.3 Brown-out Detection ATtiny25/45/85 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
Figure 8-6. Watchdog Reset During Operation CC CK 8.3 Internal Voltage Reference ATtiny25/45/85 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 8.3.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in “System and Reset Characteristics” on page 165.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON as shown in Table 8-1 Refer to “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 43 for details. Table 8-1.
8.4.2 Code Example The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
• Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. This bit must also be set when changing the prescaler bits. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 43.
Table 8-3. Watchdog Timer Prescale Select (Continued) WDP3 WDP2 WDP1 WDP0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Note: Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V Reserved(1) 1. If selected, one of the valid settings below 0b1010 will be used.
9. Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny25/45/85. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. 9.1 Interrupt Vectors in ATtiny25/45/85 The interrupt vectors of ATtiny25/45/85 are described in Table 9-1below. Table 9-1. Reset and Interrupt Vectors Vector No.
A typical and general setup for interrupt vector addresses in ATtiny25/45/85 is shown in the program example below. Assembly Code Example .
the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 23. If the low level on the interrupt pin is removed before the device has woken up then program execution will not be diverted to the interrupt service routine but continue from the instruction following the SLEEP command. 9.2.
9.3 Register Description 9.3.1 MCUCR – MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control.
9.3.3 GIFR – General Interrupt Flag Register Bit 7 6 5 4 3 2 1 0x3A – INTF0 PCIF – – – – 0 – Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 GIFR • Bits 7, 4:0 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one).
10. I/O Ports 10.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Figure 10-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx WPx RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 10.2.1 PULLUP DISABLE SLEEP CONTROL I/O CLOCK WDx: RDx: WRx: RRx: RPx: WPx: WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.
difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tristate ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b10) as an intermediate step. Table 10-1 summarizes the control signals for the pin value. Table 10-1. 10.2.
Figure 10-4. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS 0xFF out PORTx, r16 nop in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4.
10.2.5 Digital Input Enable and Sleep Modes As shown in Figure 10-2, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins.
Figure 10-5.
Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 10-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 10-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
10.3.1 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 10-3. Table 10-3.
• Port B, Bit 4 – XTAL2/CLKO/ADC2/OC1B/PCINT4 • XTAL2: Chip Clock Oscillator pin 2. Used as clock pin for all chip clock sources except internal calibrateble RC Oscillator and external clock. When used as a clock pin, the pin can not be used as an I/O pin. When using internal calibratable RC Oscillator or External clock as a Chip clock sources, PB4 serves as an ordinary I/O pin. • CLKO: The devided system clock can be output on the pin PB4.
• OC1A: Output Compare Match output: The PB1 pin can serve as an external output for the Timer/Counter1 Compare Match B when configured as an output (DDB1 set). The OC1A pin is also the output pin for the PWM mode timer function. • DO: Three-wire mode Universal Serial Interface Data output. Three-wire mode Data output overrides PORTB1 value and it is driven to the port when data direction bit DDB1 is set (one). PORTB1 still enables the pull-up, if the direction is input and PORTB1 is set (one).
Table 10-4.
10.4 10.4.1 Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0 0x35 MCUCR • Bit 6 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
11. 8-bit Timer/Counter0 with PWM 11.1 Features • • • • • • • 11.2 Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support.
interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0).
11.3.3 External Clock Source An external clock source applied to the T0 pin can be used as timer/counter clock (clkT0). The T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 11-2 shows a functional equivalent block diagram of the T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O).
Figure 11-3. Timer/Counter0 Prescaler clk I/O Clear PSR10 T0 Synchronization clkT0 The synchronization logic on the input pins (T0) in Figure 11-3 is shown in Figure 11-2 on page 67. 11.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 11-4 shows a block diagram of the counter and its surroundings. Figure 11-4. Counter Unit Block Diagram TOVn (Int.Req.
be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC0A.
The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly. 11.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0x) bit.
Figure 11-6. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCn Waveform Generator D Q 1 OCnx DATA BUS D 0 OCn Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x[1:0] bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
For detailed timing information refer to Figure 11-10, Figure 11-11, Figure 11-12 and Figure 11-13 in “Timer/Counter Timing Diagrams” on page 76. 11.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM0[2:0] = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8bit value (TOP = 0xFF) and then restarts from the bottom (0x00).
The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 11.7.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM0[2:0] = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM.
form is generated by setting (or clearing) the OC0x Register at the Compare Match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = -----------------N 256 The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
Figure 11-9. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCn (COMnx[1:0] = 2) OCn (COMnx[1:0] = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
• The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 11.8 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 11-10 contains timing data for basic Timer/Counter operation.
Figure 11-13 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP. Figure 11-13. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP OCRnx BOTTOM BOTTOM + 1 TOP OCFnx 11.9 11.9.
When OC0A/OC0B is connected to the I/O pin, the function of the COM0A[1:0]/COM0B[1:0] bits depend on the WGM0[2:0] bit setting. Table 11-2 shows the COM0x[1:0] bit functionality when the WGM0[2:0] bits are set to a normal or CTC mode (non-PWM). Table 11-2. Compare Output Mode, non-PWM Mode COM0A1 COM0B1 COM0A0 COM0B0 0 0 Normal port operation, OC0A/OC0B disconnected.
• Bits 1:0 – WGM0[1:0]: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 11-5. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 71). Table 11-5.
The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the “TCCR0A – Timer/Counter Control Register A” on page 77. • Bits 2:0 – CS0[2:0]: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 11-6.
11.9.6 OCR0B – Output Compare Register B Bit 7 6 5 0x28 4 3 2 1 0 OCR0B[7:0] OCR0B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0B pin. 11.9.
• Bit 3 – OCF0B: Output Compare Flag 0 B The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
12. 8-bit Timer/Counter1 The Timer/Counter1 is a general purpose 8-bit Timer/Counter module that has a separate prescaling selection from the separate prescaler. 12.1 Timer/Counter1 Prescaler Figure 12-1 shows the Timer/Counter1 prescaler that supports two clocking modes, a synchronous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base.
Figure 12-2. Timer/Counter 1 Synchronization Register Block Diagram. 8-BIT DATABUS IO-registers Input synchronization registers OCR1A OCR1A_SI OCR1B OCR1B_SI OCR1C OCR1C_SI TCCR1 TCCR1_SI GTCCR GTCCR_SI TCNT1 TCNT1_SI Timer/Counter1 Output synchronization registers TCNT1 TCNT_SO OCF1A OCF1A_SO TCNT1 OCF1B OCF1B_SO OCF1A OCF1A_SI OCF1B OCF1B_SI TOV1 TOV1_SI TOV1 TOV1_SO PCKE CK S A S PCK A SYNC MODE 1/2 CK Delay 1 CK Delay 1 CK Delay 1/2 CK Delay ASYNC MODE 1..
Figure 12-3. Timer/Counter1 Block Diagram T/C1 OVER- T/C1 COMPARE T/C1 COMPARE FLOW IRQ MATCH A IRQ MATCH B IRQ OC1A (PB1) OC1B (PB4) OC1A (PB0) DEAD TIME GENERATOR TOV0 PSR1 FOC1B FOC1A COM1B0 PWM1B GLOBAL T/C CONTROL REGISTER (GTCCR) COM1B1 CS10 CS12 CS11 CS13 COM1A0 COM1A1 CTC1 TOV1 T/C CONTROL REGISTER 1 (TCCR1) PWM1A OCF1B TOV1 OCF1A OCF1A TIMER INT. FLAG REGISTER (TIFR) OCF1B TOIE1 TOIE0 OCIE1A OCIE1B DEAD TIME GENERATOR TIMER INT.
12.2.1 Timer/Counter1 Initialization for Asynchronous Mode To set Timer/Counter1 in asynchronous mode first enable PLL and then wait 100 µs for PLL to stabilize. Next, poll the PLOCK bit until it is set and then set the PCKE bit. 12.2.
Figure 12-5. Effects of Unsynchronized OCR Latching Compare Value changes Counter Value Compare Value PWM Output OC1x Synchronized OC1x Latch Compare Value changes Counter Value Compare Value PWM Output OC1x Unsynchronized OC1x Latch Glitch During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A or OCR1B.
Table 12-3. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode PWM Frequency Clock Selection CS1[3:0] OCR1C RESOLUTION 20 kHz PCK/16 0101 199 7.6 30 kHz PCK/16 0101 132 7.1 40 kHz PCK/8 0100 199 7.6 50 kHz PCK/8 0100 159 7.3 60 kHz PCK/8 0100 132 7.1 70 kHz PCK/4 0011 228 7.8 80 kHz PCK/4 0011 199 7.6 90 kHz PCK/4 0011 177 7.5 100 kHz PCK/4 0011 159 7.3 110 kHz PCK/4 0011 144 7.2 120 kHz PCK/4 0011 132 7.1 130 kHz PCK/2 0010 245 7.
12.3 12.3.1 Register Description TCCR1 – Timer/Counter1 Control Register Bit 7 6 5 4 3 2 1 0 CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 0x30 TCCR1 • Bit 7 – CTC1 : Clear Timer/Counter on Compare Match When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.
Table 12-5. Timer/Counter1 Prescale Select (Continued) Asynchronous Clocking Mode Synchronous Clocking Mode 1 PCK/64 CK/64 0 0 PCK/128 CK/128 0 0 1 PCK/256 CK/256 1 0 1 0 PCK/512 CK/512 1 0 1 1 PCK/1024 CK/1024 1 1 0 0 PCK/2048 CK/2048 1 1 0 1 PCK/4096 CK/4096 1 1 1 0 PCK/8192 CK/8192 1 1 1 1 PCK/16384 CK/16384 CS13 CS12 CS11 CS10 0 1 1 1 0 1 The Stop condition provides a Timer Enable/Disable function. 12.3.
occurred, but no interrupt is generated. The FOC1B bit always reads as zero. FOC1B is not in use if PWM1B bit is set. • Bit 2 – FOC1A: Force Output Compare Match 1A Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written in the same cycle as FOC1A, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value.
to the OCR1B value. A software write that sets TCNT1 and OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag OCF1B after a synchronization delay following the compare event. 12.3.6 OCR1C – Timer/Counter1 Output Compare RegisterC Bit 7 6 5 4 3 2 1 0 0x2D MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 1 1 1 1 1 1 1 1 OCR1C The output compare register C is an 8-bit read/write register.
12.3.8 TIFR – Timer/Counter Interrupt Flag Register Bit 7 6 5 4 3 2 1 0x38 – OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 0 – Read/Write R R/W R/W R/W R/W R/W R/W R Initial value 0 0 0 0 0 0 0 0 TIFR • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. • Bit 6 – OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A Output Compare Register 1A.
12.3.9 PLLCSR – PLL Control and Status Register Bit 7 6 5 4 3 2 1 0 0x27 LSM - - - - PCKE PLLE PLOCK Read/Write R/W R R R R R/W R/W R Initial value 0 0 0 0 0 0 0/1 0 PLLCSR • Bit 7 – LSM: Low Speed Mode The high speed mode is enabled as default and the fast peripheral clock is 64 MHz, but the low speed mode can be set by writing the LSM bit to one. Then the fast peripheral clock is scaled down to 32 MHz. The low speed mode must be set, if the supply voltage is below 2.
13. 8-bit Timer/Counter1 in ATtiny15 Mode The ATtiny15 compatibility mode is selected by writing the code “0011” to the CKSEL fuses (if any other code is written, the Timer/Counter1 is working in normal mode). When selected the ATtiny15 compatibility mode provides an ATtiny15 backward compatible prescaler and Timer/Counter. Furthermore, the clocking system has same clock frequencies as in ATtiny15. 13.1 Timer/Counter1 Prescaler Figure 13-1 shows an ATtiny15 compatible prescaler.
Figure 13-2. Timer/Counter 1 Synchronization Register Block Diagram. 8-BIT DATABUS IO-registers Input synchronization registers OCR1A OCR1A_SI OCR1C OCR1C_SI TCCR1 TCCR1_SI GTCCR GTCCR_SI TCNT1 TCNT1_SI Timer/Counter1 Output synchronization registers TCNT1 TCNT_SO TCNT1 OCF1A OCF1A_SO OCF1A OCF1A_SI TOV1 TOV1_SI TOV1 TOV1_SO PCKE CK S A S PCK A SYNC MODE 1..2 PCK Delay 1 PCK Delay ~1 CK Delay No Delay ASYNC MODE 1..
Figure 13-3. Timer/Counter1 Block Diagram PSR1 GLOBAL T/C CONTROL REGISTER 2 (GTCCR) FOC1A CS10 CS12 CS11 CS13 COM1A1 COM1A0 T/C CONTROL REGISTER 1 (TCCR1) CTC1 PWM1A TOV1 TOV0 OCF1A TIMER INT. FLAG REGISTER (TIFR) OCF1A TIMER INT.
When the counter value match the content of OCR1A, the OC1A and output is set or cleared according to the COM1A1/COM1A0 bits in the Timer/Counter1 Control Register A - TCCR1, as shown in Table 13-1. Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output compare register OCR1C, and starting from $00 up again. A compare match with OCR1C will set an overflow interrupt flag (TOV1) after a synchronization delay following the compare event. Table 13-1.
Table 13-2. PWM Outputs OCR1A = $00 or OCR1C COM1A1 COM1A0 OCR1A Output OC1A 1 0 OCR1C H 1 1 $00 H 1 1 OCR1C L In PWM mode, the Timer Overflow Flag - TOV1 is set when the TCNT1 counts to the OCR1C value and the TCNT1 is reset to $00. The Timer Overflow Interrupt1 is executed when TOV1 is set provided that Timer Overflow Interrupt and global interrupts are enabled. This also applies to the Timer Output Compare flags and interrupts.
Table 13-3. 13.3 13.3.1 Timer/Counter1 Clock Prescale Select in the Asynchronous Mode (Continued) PWM Frequency Clock Selection CS1[3:0] OCR1C RESOLUTION 160 kHz PCK/2 0010 199 7.6 170 kHz PCK/2 0010 187 7.6 180 kHz PCK/2 0010 177 7.5 190 kHz PCK/2 0010 167 7.4 200 kHz PCK/2 0010 159 7.3 250 kHz PCK 0001 255 8.0 300 kHz PCK 0001 212 7.7 350 kHz PCK 0001 182 7.5 400 kHz PCK 0001 159 7.3 450 kHz PCK 0001 141 7.1 500 kHz PCK 0001 127 7.
• Bits 3:0 – CS1[3:0]: Clock Select Bits 3, 2, 1, and 0 The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. Table 13-5.
13.3.3 TCNT1 – Timer/Counter1 Bit 7 6 5 4 3 2 1 0 0x2F MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 TCNT1 This 8-bit register contains the value of Timer/Counter1. Timer/Counter1 is realized as an up counter with read and write access. Due to synchronization of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by one CPU clock cycle in synchronous mode and at most two CPU clock cycles for asynchronous mode. 13.3.
• Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.
• Bit 0 – PLOCK: PLL Lock Detector When the PLOCK bit is set, the PLL is locked to the reference clock. The PLOCK bit should be ignored during initial PLL lock-in sequence when PLL frequency overshoots and undershoots, before reaching steady state. The steady state is obtained within 100 µs. After PLL lock-in it is recommended to check the PLOCK bit before enabling PCK for Timer/Counter1.
14. Dead Time Generator The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be connected to Timer/Counter1 and it is used to insert dead times (non-overlapping times) for the Timer/Counter1 complementary output pairs (OC1A-OC1A and OC1B-OC1B).
the rising edge of OC1x and OC1x can have different dead time periods. The dead time is adjusted as the number of prescaled dead time generator clock cycles. Figure 14-3. The Complementary Output Pair PWM1x OC1x OC1x x = A or B t non-overlap / rising edge 14.1 14.1.
14.1.2 DT1A – Timer/Counter1 Dead Time A Bit 7 6 5 4 3 2 1 0 DT1AH3 DT1AH2 DT1AH1 DT1AH0 DT1AL3 DT1AL2 DT1AL1 DT1AL0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 0x25 DT1A The dead time value register A is an 8-bit read/write register. The dead time delay of is adjusted by the dead time value register, DT1A. The register consists of two fields, DT1AH[3:0] and DT1AL[3:0], one for each complementary output.
15. USI – Universal Serial Interface Features • • • • • • Overview The Universal Serial Interface (USI), provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load.
The 4-bit counter can be both read and written via the data bus, and it can generate an overflow interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges.
Figure 15-3. Three-Wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The three-wire mode timing is shown in Figure 15-3 At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRB. The value stored in register r16 prior to the function is called is transferred to the slave device, and when the transfer is completed the data received from the slave is stored back into the register r16. The second and third instructions clear the USI Counter Overflow Flag and the USI counter value.
sbrs r16, USIOIF rjmp SlaveSPITransfer_loop in r16,USIDR ret The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRB. The value stored in register r16 prior to the function is called is transferred to the master device, and when the transfer is completed the data received from the master is stored back into the register r16.
Since the clock also increments the counter, a counter overflow can be used to indicate that the transfer is completed. The clock is generated by the master by toggling the USCK pin via the PORTB register. The data direction is not given by the physical layer. A protocol, like the one used by the TWI-bus, must be implemented to control the data flow. Figure 15-5.
Figure 15-6. Start Condition Detector, Logic Diagram USISIF D Q D Q CLR CLR SDA CLOCK HOLD SCL Write( USISIF) The start condition detector is working asynchronously and can therefore wake up the processor from power-down sleep mode. However, the protocol used might have restrictions on the SCL hold time. Therefore, when using this feature the oscillator start-up time (set by CKSEL fuses, see “Clock Systems and their Distribution” on page 23) must also be taken into consideration.
15.5 15.5.1 Register Descriptions USIDR – USI Data Register Bit 7 6 5 4 3 2 1 0 0x0F MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 USIDR The USI Data Register can be accessed directly but a copy of the data can also be found in the USI Buffer Register. Depending on the USICS[1:0] bits of the USI Control Register a (left) shift operation may be performed.
If USISIE bit in USICR and the Global Interrupt Enable Flag are set, an interrupt will be generated when this flag is set. The flag will only be cleared by writing a logical one to the USISIF bit. Clearing this bit will release the start detection hold of USCL in two-wire mode. A start condition interrupt will wakeup the processor from all sleep modes. • Bit 6 – USIOIF: Counter Overflow Interrupt Flag This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0).
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable Setting this bit to one enables the counter overflow interrupt. If there is a pending interrupt and USIOIE and the Global Interrupt Enable Flag are set to one the interrupt will be executed immediately. Refer to the USIOIF bit description on page 116 for further details. • Bits 5:4 – USIWM[1:0]: Wire Mode These bits set the type of wire mode to be used, as shown in Table 15-1 below. Table 15-1.
Table 15-2 shows the relationship between the USICS[1:0] and USICLK setting and clock source used for the USI Data Register and the 4-bit counter. Table 15-2.
16. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 16-1.
16.2 16.2.1 Register Description ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 0x03 BIN ACME IPR – – ADTS2 ADTS1 ADTS0 Read/Write R/W R/W R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 6 – ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator.
• Bits 1:0 – ACIS[1:0]: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 16-2. Table 16-2. ACIS1/ACIS0 Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge.
17. Analog to Digital Converter 17.1 Features • • • • • • • • • • • • • • • • • 17.2 10-bit Resolution 1 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 65 - 260 µs Conversion Time Up to 15 kSPS at Maximum Resolution Four Multiplexed Single Ended Input Channels Two differential input channels with selectable gain Temperature sensor input channel Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 1.1V / 2.
Figure 17-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] REFS[2:0] ADC[9:0] ADPS1 TRIGGER SELECT MUX DECODER VCC PRESCALER INTERNAL 1.1V/2.56V REFERENCE GAIN SELECTION CHANNEL SELECTION START AREF CONVERSION LOGIC TEMPERATURE SENSOR SAMPLE & HOLD COMPARATOR 10-BIT DAC ADC4 ADC3 ADC2 0 ADC DATA REGISTER (ADCH/ADCL) ADPS0 ADPS2 ADIF ADSC ADEN ADLAR MUX1 MUX0 MUX2 BIN IPR 15 ADC CTRL.
If ADC0 or ADC2 is selected as both the positive and negative input to the differential gain amplifier (ADC0-ADC0 or ADC2-ADC2), the remaining offset in the gain stage and conversion circuitry can be measured directly as the result of the conversion. This figure can be subtracted from subsequent conversions with the same gain setting to reduce offset error to below 1 LSW.
Figure 17-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. Prescaling and Conversion Timing Figure 17-3.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry, as shown in Figure 17-4 below. Figure 17-4.
Figure 17-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion 1 Cycle Number 2 3 4 5 6 7 8 9 Next Conversion 10 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Prescaler Reset Prescaler Reset Conversion Complete MUX and REFS Update In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. Figure 17-7.
17.6 Changing Channel or Reference Selection The MUX[3:0] and REFS[2:0] bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and voltage reference selection only takes place at a safe point during the conversion. The channel and voltage reference selection is continuously updated until a conversion is started.
conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed. Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption. 17.
is used for reading the internal temperature sensor, as described in Section 17.12 on page 133. A good system design with properly placed, external bypass capacitors does reduce the need for using ADC Noise Reduction Mode 17.10 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
Figure 17-10. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 17-11.
Figure 17-12. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code.
V POS – V NEG 1024 ADC = -------------------------------------------------------- GAIN V REF where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin, and VREF the selected voltage reference (see Table 17-3 on page 134 and Table 17-4 on page 135). The voltage on the positive pin must always be larger than the voltage on the negative pin or otherwise the voltage difference is saturated to zero.
where ADCH and ADCL are the ADC data registers, k is the fixed slope coefficient and TOS is the temperature sensor offset. Typically, k is very close to 1.0 and in single-point calibration the coefficient may be omitted. Where higher accuracy is required the slope coefficient should be evaluated based on measurements at two temperatures. 17.13 Register Description 17.13.
enables the temperature sensor. Refer to Table 17-4 for details. If these bits are changed during a conversion, the change will not go into effect until this conversion is complete (ADIF in ADCSRA is set). Table 17-4.
17.13.2 ADCSRA – ADC Control and Status Register A Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0x06 ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
17.13.3 ADCL and ADCH – The ADC Data Register 17.13.3.1 ADLAR = 0 Bit 15 14 13 12 11 10 9 8 0x05 – – – – – – ADC9 ADC8 ADCH 0x04 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL Read/Write Initial Value 17.13.3.
• Bits 4:3 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag.
18. debugWIRE On-chip Debug System 18.1 Features • • • • • • • • • • 18.
When designing a system where debugWIRE will be used, the following must be observed: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 k. However, the pull-up resistor is optional. • Connecting the RESET pin directly to VCC will not work. • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 18.4 Software Break Points debugWIRE supports Program memory Break Points by the AVR Break instruction.
19. Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The SPM instruction is disabled by default but it can be enabled by programming the SELFPRGEN fuse (to “0”). The Program memory is updated in a page by page fashion.
19.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. Note: 19.4 The CPU is halted during the Page Write operation. Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands.
19.6 Reading Lock, Fuse and Signature Data from Software It is possible to read fuse and lock bits from firmware. In addition, firmware can also read data from the device signature imprint table (see page 149). Note: 19.6.1 Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one.
To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and repeat the previous procedure. If successful, the contents of the destination register are as follows. Bit 7 6 5 4 3 2 1 0 Rd FEB7 FEB6 FEB5 FEB4 FEB3 FEB2 FEB1 FEB0 Refer to Table 20-3 on page 148 for detailed description and mapping of the Fuse Extended Byte. 19.6.
not, an external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 2. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash from unintentional writes. 19.
• Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.
20. Memory Programming This section describes the different methods for Programming the ATtiny25/45/85 memories. 20.1 Program And Data Memory Lock Bits ATtiny25/45/85 provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in Table 20-2. Lock bits can be erased to “1” with the Chip Erase command, only. Program memory can be read out via the debugWIRE interface when the DWEN fuse is programmed, even if the Lock Bits are set.
20.2 Fuse Bytes ATtiny25/45/85 has three fuse bytes, as described in Table 20-3, Table 20-4, and Table 20-5. Note that fuses are read as logical zero, “0”, when programmed. Table 20-3. Fuse Extended Byte Fuse High Byte SELFPRGEN Notes: (1) Bit No Description Default Value 7 - 1 (unprogrammed) 6 - 1 (unprogrammed) 5 - 1 (unprogrammed) 4 - 1 (unprogrammed) 3 - 1 (unprogrammed) 2 - 1 (unprogrammed) 1 - 1 (unprogrammed) 0 Self-programming enabled 1 (unprogrammed) 1.
Table 20-5.
20.3.1 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and high-voltage programming mode, even when the device is locked. Signature bytes can also be read by the device firmware. See section “Reading Lock, Fuse and Signature Data from Software” on page 143. The three signature bytes reside in a separate address space called the device signature imprint table.
20.5 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). See below. Figure 20-1. Serial Programming and Verify(1) +1.8 - 5.5V VCC MOSI MISO SCK RESET GND Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the CLKI pin.
To program and verify the ATtiny25/45/85 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 20-12): 1. Power-up sequence: apply power between VCC and GND while RESET and SCK are set to “0” – In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse after SCK has been set to '0'. The duration of the pulse must be at least tRST plus two CPU clock cycles.
20.5.2 Serial Programming Instruction set Table 20-11. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 4.0 ms tWD_ERASE 9.0 ms tWD_FUSE 4.5 ms Table 20-12 on page 153 and Figure 20-2 on page 154 describes the Instruction set. Table 20-12.
2. a = address 3. Bits are programmed ‘0’, unprogrammed ‘1’. 4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) . 5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use a word address. This address may be random within the page range. 7. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers.
20.6 High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the ATtiny25/45/85. Figure 20-3. High-voltage Serial Programming +11.5 - 12.5V SCI +4.5 - 5.5V PB5 (RESET) VCC PB3 PB2 SDO PB1 SII PB0 SDI GND Table 20-13.
20.7.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in High-voltage Serial Programming mode: 1. Set Prog_enable pins listed in Table 20-14 to “000”, RESET pin and VCC to 0V. 2. Apply 4.5 - 5.5V between VCC and GND. Ensure that VCC reaches at least 1.8V within the next 20 µs. 3. Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET. 4.
1. Load command “Chip Erase” (see Table 20-16). 2. Wait after Instr. 3 until SDO goes high for the “Chip Erase” cycle to finish. 3. Load Command “No Operation”. 20.7.4 Programming the Flash The Flash is organized in pages, see Table 20-12 on page 153. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: 1.
20.7.5 Programming the EEPROM The EEPROM is organized in pages, see Table 21-11 on page 170. When programming the EEPROM, the data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM Data memory is as follows (refer to Table 20-16): 1. Load Command “Write EEPROM”. 2. Load EEPROM Page Buffer. 3. Program EEPROM Page. Wait after Instr. 2 until SDO goes high for the “Page Programming” cycle to finish. 4.
Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued) Instruction Format Instruction Instr.1/5 Instr.2/6 Instr.3 Instr.4 Wait after Instr 3 until SDO goes high. Repeat Instr. 2 - 3 for each loaded Flash Page until the entire Flash or all data is programmed. Repeat Instr. 1 for a new 256 byte page.
Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued) Instruction Format Instruction Instr.1/5 Instr.2/6 Instr.3 Instr.
21. Electrical Characteristics 21.1 Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied.
Table 21-1. DC Characteristics. TA = -40C to +85C (Continued) Symbol Parameter Condition Rpu I/O Pin Pull-up Resistor VCC = 5.5V, input low Power Supply Current (7) ICC Power-down mode (8) Notes: Min. Typ.(1) 20 Max. Units 50 k Active 1 MHz, VCC = 2V 0.3 0.55 mA Active 4 MHz, VCC = 3V 1.5 2.5 mA Active 8 MHz, VCC = 5V 5 8 mA Idle 1 MHz, VCC = 2V 0.1 0.2 mA Idle 4 MHz, VCC = 3V 0.35 0.6 mA Idle 8 MHz, VCC = 5V 1.
21.3 Speed Figure 21-1. Maximum Frequency vs. VCC 10 MHz Safe Operating Area 4 MHz 1.8V 2.7V 5.5V Figure 21-2. Maximum Frequency vs. VCC 20 MHz 10 MHz Safe Operating Area 2.7V 4.5V 5.
21.4 Clock Characteristics 21.4.1 Calibrated Internal RC Oscillator Accuracy It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Please note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics can be found in Figure 22-40 on page 193 and Figure 22-41 on page 193. Table 21-2.
21.5 System and Reset Characteristics Table 21-4. Reset, Brown-out and Internal Voltage Characteristics Parameter Condition Min(1) VRST RESET Pin Threshold Voltage VCC = 3V 0.2 VCC tRST Minimum pulse width on RESET Pin VCC = 3V Symbol VHYST Typ(1) Max(1) Units 0.9 VCC V 2.5 µs Brown-out Detector Hysteresis 50 mV tBOD Min Pulse Width on Brown-out Reset 2 µs VBG Bandgap reference voltage VCC = 5.
• ATtiny45, revision G, and newer • ATtiny85, revision C, and newer Table 21-6. Symbol Characteristics of Enhanced Power-On Reset. TA = -40C to +85C Parameter Min(1) Typ(1) Max(1) Units 1.1 1.4 1.6 V 1.3 1.6 V (2) VPOR Release threshold of power-on reset VPOA Activation threshold of power-on reset (3) 0.6 SRON Power-On Slope Rate 0.01 Note: V/ms 1. Values are guidelines, only 2. Threshold where device is released from reset when voltage is rising 3.
21.7 ADC Characteristics Table 21-8. Symbol ADC Characteristics, Single Ended Channels. TA = -40C to +85C Parameter Condition Min Typ Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset errors) VINT VREF = 4V, VCC = 4V, ADC clock = 1 MHz 3 LSB VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 1.5 LSB VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode 2.
Table 21-9. Symbol ADC Characteristics, Differential Channels (Unipolar Mode). TA = -40C to +85C Parameter Condition Min Typ Max Units Gain = 1x 10 Bits Gain = 20x 10 Bits Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 10.0 LSB Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 20.
Table 21-10. ADC Characteristics, Differential Channels (Bipolar Mode). TA = -40C to +85C Symbol Parameter Condition Min Typ Max Units Gain = 1x 10 Bits Gain = 20x 10 Bits Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 8.0 LSB Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 8.
21.8 Serial Programming Characteristics Figure 21-4. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Figure 21-5. Serial Programming Timing MOSI tSHOX tOVSH SCK tSLSH tSHSL MISO tSLIV Table 21-11. Serial Programming Characteristics, TA = -40C to +85C, VCC = 1.8 - 5.5V (Unless Otherwise Noted) Symbol Parameter 1/tCLCL Oscillator Frequency (VCC = 1.8 - 5.5V) tCLCL Oscillator Period (VCC = 1.8 - 5.
21.9 High-voltage Serial Programming Characteristics Figure 21-6. High-voltage Serial Programming Timing SDI (PB0), SII (PB1) tIVSH SCI (PB3) tSLSH tSHIX tSHSL SDO (PB2) tSHOV Table 21-12. High-voltage Serial Programming Characteristics TA = 25C ± 10%, VCC = 5.
22. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled.
Figure 22-2. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 14 5.5 V 12 5.0 V ICC (mA) 10 4.5 V 8 4.0V 6 3.3V 4 2.7V 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 22-3. Active Supply Current vs. VCC (Internal RC oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs.
Figure 22-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 1,6 25 ˚C 85 ˚C -40 ˚C 1,4 ICC (mA) 1,2 1 0,8 0,6 0,4 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs.
Idle Supply Current Figure 22-6. Idle Supply Current vs. low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 0,25 5.5 V 5.0 V 0,2 4.5 V ICC (mA) 4.0 V 0,15 3.3 V 2.7 V 0,1 1.8 V 0,05 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 22-7. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 4 ICC (mA) 22.2 3,5 5.5 V 3 5.0 V 2,5 4.5 V 2 4.0V 1,5 3.3V 1 2.7V 0,5 1.
Figure 22-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)I IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 1,8 85 ˚C 1,6 25 ˚C 1,4 -40 ˚C ICC (mA) 1,2 1 0,8 0,6 0,4 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-9. Idle Supply Current vs. VCC (Internal RC Oscilllator, 1 MHz) IDLE SUPPLY CURRENT vs.
Figure 22-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 128 kHz 0,1 0,09 -40 ˚C 25 ˚C 0,08 85 ˚C ICC (mA) 0,07 0,06 0,05 0,04 0,03 0,02 0,01 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 22.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode.
22.3.1 Example Calculate the expected current consumption in idle mode with USI, TIMER0, and ADC enabled at VCC = 2.0V and f = 1 MHz. From Table 22-2 on page 177, third column, we see that we need to add 10% for the USI, 25% for the ADC, and 10% for the TIMER0 module. Reading from Figure 22-9, we find that the idle current consumption is ~0,18 mA at VCC = 2.0V and f = 1 MHz.
Figure 22-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 14 12 10 ICC (uA) -40 ˚C 8 25 ˚C 85 ˚C 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pin Pull-up Figure 22-13. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 1.8V 60 50 40 IOP (uA) 22.
Figure 22-14. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7V 80 70 60 IOP (uA) 50 40 30 20 25 ˚C 85 ˚C 10 -40 ˚C 0 0 0,5 1 1,5 2 2,5 3 VOP (V) Figure 22-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs.
Figure 22-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 1.8V 40 35 IRESET(uA) 30 25 20 15 10 25 ˚C -40 ˚C 85 ˚C 5 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VRESET (V) Figure 22-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC =2.
Figure 22-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 5V 120 100 IRESET(uA) 80 60 40 25 ˚C -40 ˚C 85 ˚C 20 0 0 1 2 3 4 5 6 VRESET(V) Pin Driver Strength Figure 22-19. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 1,2 1 85 0,8 VOL (V) 22.
Figure 22-20. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 0,6 85 0,5 25 VOL (V) 0,4 -40 0,3 0,2 0,1 0 0 5 10 15 20 25 IOL (mA) Figure 22-21. I/O Pin Output Voltage vs. Source Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs.
Figure 22-22. I/O Pin Output Voltage vs. Source Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5,1 5 VOH (V) 4,9 4,8 4,7 4,6 -40 25 4,5 85 4,4 0 5 10 15 20 25 IOH (mA) Figure 22-23. Reset Pin Output Voltage vs. Sink Current (VCC = 3V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 1.5 85 °C VOL (V) 1 0 °C -45 °C 0.5 0 0 0.5 1 1.5 2 2.
Figure 22-24. Reset Pin Output Voltage vs. Sink Current (VCC = 5V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 1 0.8 VOL (V) 0.6 85 °C 0.4 0 °C -45 °C 0.2 0 0 0.5 1 1.5 2 2.5 3 IOL (mA) Figure 22-25. Reset Pin Output Voltage vs. Source Current (VCC = 3V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 3V 3.5 3 VOH (V) 2.5 2 1.5 -45 °C 25 °C 85 °C 1 0.5 0 0 0.5 1 1.
Figure 22-26. Reset Pin Output Voltage vs. Source Current (VCC = 5V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5 4.5 VOH (V) 4 3.5 3 -45 °C 25 °C 85 °C 2.5 0 0.5 1 1.5 2 IOH (mA) Pin Threshold and Hysteresis Figure 22-27. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 3 -40 ˚C 85 ˚C 25 ˚C 2,5 Threshold (V) 22.
Figure 22-28. I/O Pin Input Threshold Voltage vs. VCC (VIL, IO Pin Read as ‘0’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 3 85 ˚C 25 ˚C 2,5 Threshold (V) -40 ˚C 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-29. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs.
Figure 22-30. Reset Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 85 °C 2,5 25 °C -40 °C Threshold (V) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-31. Reset Input Threshold Voltage vs. VCC (VIL, IO Pin Read as ‘0’) RESET INPUT THRESHOLD VOLTAGE vs.
Figure 22-32. Reset Pin Input Hysteresis vs. VCC RESET PIN INPUT HYSTERESIS vs. VCC 0,5 0,45 0,4 Input Hysteresis (V) 0,35 0,3 0,25 0,2 0,15 0,1 -40 °C 25 °C 0,05 85 °C 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) BOD Threshold Figure 22-33. BOD Threshold vs. Temperature (BOD Level is 4.3V) BOD THRESHOLDS vs. TEMPERATURE 4,4 Rising VCC 4,38 4,36 Threshold (V) 22.
Figure 22-34. BOD Threshold vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE 2,8 Rising VCC 2,78 Threshold (V) 2,76 2,74 2,72 Falling VCC 2,7 2,68 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) Figure 22-35. BOD Threshold vs. Temperature (BOD Level is 1.8V) BOD THRESHOLDS vs.
Figure 22-36. Bandgap Voltage vs. Supply Voltage BANDGAP VOLTAGE vs. VCC 1,2 1,18 1,16 Bandgap Voltage (V) 1,14 1,12 1,1 85 °C 25 °C 1,08 1,06 1,04 -40 °C 1,02 1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 Vcc (V) Figure 22-37. Bandgap Voltage vs. Temperature BANDGAP VOLTAGE vs. Temperature 1,2 1,18 1,16 Bandgap Voltage (V) 1,14 1.
Internal Oscillator Speed Figure 22-38. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. VCC 0,128 0,126 0,124 FRC (MHz) -40 ˚C 0,122 25 ˚C 0,12 0,118 0,116 0,114 85 ˚C 0,112 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-39. Watchdog Oscillator Frequency vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 0,12 0,118 0,116 FRC (MHz) 22.9 0,114 1.8 V 0,112 2.7 V 3.3 V 0,11 4.0 V 5.
Figure 22-40. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. VCC 8,2 85 ˚C 8,1 FRC (MHz) 8 25 ˚C 7,9 7,8 -40 ˚C 7,7 7,6 7,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-41. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8,15 3.0 V 8,1 8,05 5.
Figure 22-42. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 18 85 ˚C 25 ˚C 16 14 -40 ˚C FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL (X1) Figure 22-43. Calibrated 1.6 MHz RC Oscillator Frequency vs. VCC CALIBRATED 1.6 MHz RC OSCILLATOR FREQUENCY vs.
Figure 22-44. Calibrated 1.6 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 1.6MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1,64 3.0 V 1,62 5.0 V FRC (MHz) 1,6 1,58 1,56 1,54 1,52 1,5 -60 -40 -20 0 20 40 60 80 100 Temperature Figure 22-45. Calibrated 1.6 MHz RC Oscillator Frequency vs. OSCCAL Value CALIBRATED 1.6 MHz RC OSCILLATOR FREQUENCY vs.
22.10 Current Consumption of Peripheral Units Figure 22-46. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 30 85 °C 25 25 °C -40 °C ICC (uA) 20 15 10 5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-47. ADC Current vs. VCC (AREF = AVCC) ADC CURRENT vs.
Figure 22-48. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 50 45 85 °C 40 25 °C -40 °C ICC (uA) 35 30 25 20 15 10 5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-49. Programming Current vs. VCC PROGRAMMING CURRENT vs.
22.11 Current Consumption in Reset and Reset Pulsewidth Figure 22-50. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. VCC 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP ICC (mA) 0,16 0,14 5.5 V 0,12 5.0 V 4.5 V 0,1 4.0 V 0,08 3.3 V 0,06 2.7 V 0,04 1.8 V 0,02 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 22-51. Reset Supply Current vs.
Figure 22-52. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs.
23.
should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags.
24.
Mnemonics Operands Description Operation Flags #Clocks SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..
25. Ordering Information 25.
25.2 ATtiny45 Speed (MHz) (1) 10 1.8 – 5.5 20 Notes: Supply Voltage (V) 2.7 – 5.
25.3 ATtiny85 Speed (MHz) (1) 10 1.8 – 5.5 20 Notes: Supply Voltage (V) 2.7 – 5.5 Temperature Range Industrial (-40C to +85C) (4) Industrial (-40C to +85C) (4) Package (2) Ordering Code (3) 8P3 ATtiny85V-10PU 8S2 ATtiny85V-10SU ATtiny85V-10SUR ATtiny85V-10SH ATtiny85V-10SHR 20M1 ATtiny85V-10MU ATtiny85V-10MUR 8P3 ATtiny85-20PU 8S2 ATtiny85-20SU ATtiny85-20SUR ATtiny85-20SH ATtiny85-20SHR 20M1 ATtiny85-20MU ATtiny85-20MUR 1. For speed vs. supply voltage, see section 21.
26. Packaging Information 26.1 8P3 E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A SYMBOL MIN NOM A b2 b3 b 4 PLCS Side View L 0.210 NOTE 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 0.100 BSC eA 0.300 BSC 0.115 3 3 e L Notes: MAX 0.130 4 0.150 2 1.
26.2 8S2 C 1 E E1 L N θ TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D SIDE VIEW MAX NOM NOTE 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 θ 0° 8° e Notes: 1. 2. 3. 4. MIN A 1.27 BSC 2 3 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included.
26.3 S8S1 1 E1 E N Top View e b A A1 D Side View C L End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX E 5.79 6.20 E1 3.81 3.99 A 1.35 1.75 A1 0.1 0.25 D 4.80 4.98 C 0.17 0.25 b 0.31 0.51 L 0.4 1.27 e NOTE 1.27 BSC 0o 8o Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc. 7/28/03 R 2325 Orchard Parkway San Jose, CA 95131 TITLE S8S1, 8-lead, 0.
26.4 8X C 1 E1 End View E L Top View e Ø b COMMON DIMENSIONS (Unit of Measure = mm) A A1 MAX 1.05 1.10 1.20 A1 0.05 0.10 0.15 b 0.25 – 0.30 C – 0.127 – D 2.90 3.05 3.10 E1 4.30 4.40 4.50 E 6.20 6.40 6.60 A D Side View MIN NOM SYMBOL e NOTE 0.65 TYP L 0.50 0.60 0.70 Ø 0o – 8o Note: These drawings are for general information only. Refer to JEDEC Drawing MO-153AC. 4/14/05 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8X, 8-lead, 4.
26.5 20M1 D 1 Pin 1 ID 2 SIDE VIEW E 3 TOP VIEW A2 D2 A1 A 0.08 1 2 Pin #1 Notch (0.20 R) 3 COMMON DIMENSIONS (Unit of Measure = mm) E2 b L e BOTTOM VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 b 0.18 D D2 E2 L 0.23 0.30 4.00 BSC 2.45 2.60 2.75 4.00 BSC 2.45 e Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. NOTE 0.20 REF E Note: C 2.60 2.75 0.50 BSC 0.35 0.40 0.
27. Errata 27.1 Errata ATtiny25 The revision letter in this section refers to the revision of the ATtiny25 device. 27.1.1 Rev D – F No known errata. 27.1.2 Rev B – C • EEPROM read may fail at low supply voltage / low clock frequency 1. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data.
27.2.3 Rev B – C • • • • PLL not locking EEPROM read from application code does not work in Lock Bit Mode 3 EEPROM read may fail at low supply voltage / low clock frequency Timer Counter 1 PWM output generation on OC1B- XOC1B does not work correctly 1. PLL not locking When at frequencies below 6.0 MHz, the PLL will not lock Problem fix / Workaround When using the PLL, run at 6.0 MHz or higher. 2.
– When using external clock, avoid setting the clock pin as Output. – Do not read the EEPROM if power down power consumption is important. – Use VCC lower than 4.5 Volts. 2. DebugWIRE looses communication when single stepping into interrupts When receiving an interrupt during single stepping, debugwire will loose communication. Problem fix / Workaround – When singlestepping, disable interrupts. – When debugging interrupts, use breakpoints within the interrupt routine, and run into the interrupt. 3.
27.3 Errata ATtiny85 The revision letter in this section refers to the revision of the ATtiny85 device. 27.3.1 Rev B – C No known errata. 27.3.2 Rev A • EEPROM read may fail at low supply voltage / low clock frequency 1. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data. Problem Fix/Workaround Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V.
28. Datasheet Revision History 28.1 Rev. 2586Q-08/13 1. 28.2 Rev. 2586P-06/13 1. 28.3 “Bit 3 – FOC1B: Force Output Compare Match 1B” description in “GTCCR – General Timer/Counter1 Control Register” on page 90 updated: PB3 in “compare match output pin PB3 (OC1B)” corrected to PB4. Updated description of “EEARH – EEPROM Address Register” and “EEARL – EEPROM Address Register” on page 20. Rev. 2586O-02/13 Updated ordering codes on page 204, page 205, and page 206. 28.4 Rev. 2586N-04/11 1.
2. Updated: – “Features” on page 1, removed Preliminary from ATtiny25 – Section 8.4.2 “Code Example” on page 44 – “PCMSK – Pin Change Mask Register” on page 52, Bit Descriptions – “TCCR1 – Timer/Counter1 Control Register” on page 89 and “GTCCR – General Timer/Counter1 Control Register” on page 90, COM bit descriptions clarified – Section 20.3.2 “Calibration Bytes” on page 150, frequencies (8 MHz, 6.
5. Updated Figure: – “Reset Logic” on page 39 6. Updated Tables: – “Start-up Times for Internal Calibrated RC Oscillator Clock” on page 28 – “Start-up Times for Internal Calibrated RC Oscillator Clock (in ATtiny15 Mode)” on page 28 – “Start-up Times for the 128 kHz Internal Oscillator” on page 28 – “Compare Mode Select in PWM Mode” on page 86 – “Compare Mode Select in PWM Mode” on page 98 – “DC Characteristics.
8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. Updated Table 6-1 on page 25, Table 6-13 on page 30 and Table 6-6 on page 27. Updated “Calibrated Internal Oscillator” on page 27. Updated Table 6-5 on page 26. Updated “OSCCAL – Oscillator Calibration Register” on page 31. Updated “CLKPR – Clock Prescale Register” on page 32. Updated “Power-down Mode” on page 35. Updated “Bit 0” in “PRR – Power Reduction Register” on page 38.
28.9 Rev. 2586I-09/06 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. All Characterization data moved to “Electrical Characteristics” on page 161. All Register Descriptions are gathered up in seperate sections in the end of each chapter. Updated Table 11-3 on page 78, Table 11-5 on page 79, Table 11-6 on page 80 and Table 20-4 on page 148. Updated “Calibrated Internal Oscillator” on page 27. Updated Note in Table 7-1 on page 34. Updated “System Control and Reset” on page 39.
28.13 Rev. 2586E-03/06 1. 2. 3. 4. 5. Updated Features in “Analog to Digital Converter” on page 122. Updated Operation in “Analog to Digital Converter” on page 122. Updated Table 17-2 on page 133. Updated Table 17-3 on page 134. Updated “Errata” on page 212. 28.14 Rev. 2586D-02/06 1. 2. 3. 4. 5. 6. 7. 8. 9.
ATtiny25/45/85 [DATASHEET] 2586Q–AVR–08/2013 222
ATtiny25/45/85 [DATASHEET] 2586Q–AVR–08/2013 223
ATtiny25/45/85 [DATASHEET] 2586Q–AVR–08/2013 224
ATtiny25/45/85 [DATASHEET] 2586Q–AVR–08/2013 225
ATtiny25/45/85 [DATASHEET] 2586Q–AVR–08/2013 226
Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1 2 Overview ................................................................................................... 4 2.1 3 4 5 6 7 Pin Descriptions .................................................................................................2 Block Diagram ...
8 9 7.2 Software BOD Disable .....................................................................................35 7.3 Power Reduction Register ...............................................................................36 7.4 Minimizing Power Consumption ......................................................................36 7.5 Register Description ........................................................................................37 System Control and Reset ...........................
13.2 Counter and Compare Units ............................................................................95 13.3 Register Description ......................................................................................100 14 Dead Time Generator ........................................................................... 105 14.1 Register Description ......................................................................................106 15 USI – Universal Serial Interface .........................
19.1 Performing Page Erase by SPM ....................................................................141 19.2 Filling the Temporary Buffer (Page Loading) .................................................141 19.3 Performing a Page Write ...............................................................................142 19.4 Addressing the Flash During Self-Programming ...........................................142 19.5 EEPROM Write Prevents Writing to SPMCSR .........................................
22.9 Internal Oscillator Speed ...............................................................................192 22.10 Current Consumption of Peripheral Units ......................................................196 22.11 Current Consumption in Reset and Reset Pulsewidth ...................................198 23 Register Summary ................................................................................ 200 24 Instruction Set Summary .............................................................
28.16 Rev. 2586B-05/05 ..........................................................................................221 28.17 Rev. 2586A-02/05 ..........................................................................................221 Table of Contents .......................................................................................
ATtiny25/45/85 [DATASHEET] 2586Q–AVR–08/2013 vii
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