Datasheet

ManualsBrandsMicrochip ManualsAVR MicrocontrollersAVR RISC Microcontroller Flash 32KB

8-bit AVR Microcontrollers

ATmega324PA

DATASHEET SUMMARY

Introduction

The Atmel

picoPower

ATmega324PA is a low-power CMOS 8-bit

microcontroller based on the AVR

enhanced RISC architecture. By

executing powerful instructions in a single clock cycle, the ATmega324PA

achieves throughputs close to 1MIPS per MHz. This empowers system

designer to optimize the device for power consumption versus processing

speed.

Feature

High Performance, Low Power Atmel

AVR

8-Bit Microcontroller Family

• Advanced RISC Architecture

– 131 Powerful Instructions

– Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20MHz

– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory Segments

– 32KBytes of In-System Self-Programmable Flash Program

Memory

– 1KBytes EEPROM

– 2KBytes Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data Retention: 20 Years at 85°C/100 Years at 25°C

(1)

– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program

• True Read-While-Write Operation

– Programming Lock for Software Security

• Atmel QTouch

Library Support

– Capacitive Touch Buttons, Sliders and Wheels

– QTouch and QMatrix acquisition

– Up to 64 Sense Channels

Atmel-42715C-ATmega324PA_Datasheet_Summary-10/2016

Summary of content (22 pages)

PAGE 1
8-bit AVR Microcontrollers ATmega324PA DATASHEET SUMMARY Introduction ® ® The Atmel picoPower ATmega324PA is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega324PA achieves throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed.
PAGE 2
• • JTAG (IEEE std. 1149.
PAGE 3
Data Retention on page 16 Atmel ATmega324PA [DATASHEET] Atmel-42715C-ATmega324PA_Datasheet_Summary-10/2016 3
PAGE 4
Table of Contents Introduction......................................................................................................................1 Feature............................................................................................................................ 1 1. Description.................................................................................................................5 2. Configuration Summary...........................................................................
PAGE 5
1. Description The Atmel® ATmega324PA is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega324PA achieves throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed. The Atmel AVR® core combines a rich instruction set with 32 general purpose working registers.
PAGE 6
2. Configuration Summary The table below compares the device series of feature and pin compatible devices, providing a seamless migration path. Table 2-1.
PAGE 7
3. Ordering Information Speed [MHz](3) Power Supply [V] 20 1.8 - 5.5 20 1.8 - 5.
PAGE 8
4. Block Diagram Figure 4-1. Block Diagram SRAM TCK TMS TDI TDO JTAG CPU OCD Clock generation TOSC1 32.
PAGE 9
5. Pin Configurations 5.1. Pinout 5.1.1.
PAGE 10
PB1 (T1/CLKO/PCINT9) PB0 (XCK0/T0/PCINT8) GND VCC PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3) 41 40 39 38 37 36 35 34 Crystal/Osc PB2 (AIN0/INT2/PCINT10) Analog 42 Digital PB3 (AIN1/OC0A/PCINT11) Programming/debug 43 Ground PB4 (SS/OC0B/PCINT12) Power 44 TQFN and QFN GND XTAL2 7 27 AVCC XTAL1 8 26 PC7 (TOSC2/PCINT23) (PCINT24/RXD0) PD0 9 25 PC6 (TOSC1/PCINT22) (PCINT25/TXD0) PD1 10 24 PC5 (TDI/PCINT21) (PCINT26/RXD1/INT0) PD2 11 23
PAGE 11
DRQFN Top view Bottom view B6 A7 B7 A8 A12 B10 B8 A10 B9 A11 B10 A12 B7 A9 B6 A8 A9 B5 A6 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 A10 B8 B4 A5 A18 B15 A17 B14 A16 B13 A15 B12 A14 B11 A13 A11 B9 B3 A4 A24 B20 B2 A3 A23 B19 A2 A22 B18 A18 B15 A17 B14 A16 B13 A15 B12 A14 B11 A13 B1 A21 B17 A20 B16 A19 A19 B16 A20 B17 A21 B18 A22 B19 A23 B20 A24 A1 A7 5.1.3. Table 5-1.
PAGE 12
5.1.4. VFBGA 7 6 02 C VC PB 00 PB AR EF 01 06 PA PB C 06 PC 07 PC 04 PC 03 PC PB PC 05 02 PC 01 PC 05 PB C VC 07 00 7 2 PD AL XT 07 05 PD 01 PD 00 06 PD PD C VC 04 PD 0 PA C AV 03 PB 04 PB PD PC 03 1 AL XT 02 PD Programming/debug 5.2. Pin Descriptions 5.2.1. VCC Digital supply voltage. 5.2.2. GND Ground. 5.2.3. Port A (PA[7:0]) This port serves as analog inputs to the Analog-to-digital Converter.
PAGE 13
5.2.4. Port B (PB[7:0]) This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running.
PAGE 14
6. I/O Multiplexing Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the PORT I/O pins. Table 6-1.
PAGE 15
32-pin 40-pin TQFP/ QFN/ PDIP Pin MLF Pin # # DRQFN Pin# VFBGA Pin# PAD 34 37 A19 B6 PA[3] PCINT3 ADC3 35 38 B16 A6 PA[2] PCINT2 ADC2 36 39 A20 C5 PA[1] PCINT1 ADC1 37 40 B17 B5 PA[0] PCINT0 ADC0 38 - A21 G3 VCC SDA1 39 - B18 A7 GND SCL1 40 1 A22 B4 PB[0] PCINT8 41 2 B19 C4 PB[1] PCINT9 42 3 A23 A3 PB[2] 43 4 B20 B3 PB[3] PCINT11 PCINT12 44 5 A24 A2 PB[4] - - - D4 GND - - - D7 GND - - - G1 GND - - - G4 GND - - - G7
PAGE 16
7. General Information 7.1. Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. 7.2. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C. 7.3. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device.
PAGE 17
8. Packaging Information 8.1. 40-pin PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). SYMBOL MIN NOM MAX A – – 4.826 A1 0.381 – – D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.
PAGE 18
8.2. 44-pin TQFP P IN 1 IDENTIFIER P IN 1 B e E1 E A1 A2 D1 D C 0°~7° L A COMMON DIMENS IONS (Unit of Me a s ure = mm) Note s : 1. This pa cka ge conforms to J EDEC re fe re nce MS -026, Va ria tion ACB. 2. Dime ns ions D1 a nd E1 do not include mold protrus ion. Allowa ble protrus ion is 0.25mm pe r s ide . Dime ns ions D1 a nd E1 a re ma ximum pla s tic body s ize dime ns ions including mold mis ma tch. 3. Le a d copla na rity is 0.10mm ma ximum. S YMBOL MIN NOM MAX A – – 1.
PAGE 19
8.3. 44-pin VQFN D Marked Pin# 1 I D E SE ATING PLANE A1 TOP VIEW A3 A K L Pin #1 Co rne r D2 1 2 3 Option A SIDE VIEW Pin #1 Triangl e COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 SYMBOL E2 Option B K Option C b e Pin #1 Cham fe r (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW A3 0.20 REF b 0.18 0.23 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.40 e Note : JEDEC Standard MO-220, Fig .
PAGE 20
8.4. 44-pin QFN C Pin 1 ID D SIDE VIEW y A1 E A TOP VIEW eT/2 A19 eR A24 B20 B16 A1 A18 COMMON DIMENSIONS (Unit of Measure = mm) B1 B15 b R0.20 0.40 D2 eT SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.18 0.23 0.30 C B5 B11 A6 A13 B10 B6 A12 A7 L L E2 BOTTOM VIEW Note: 1. The terminal #1 ID is a Laser-marked Feature. L NOTE 0.20 REF D 4.90 5.00 5.10 D2 2.55 2.60 2.65 E 4.90 5.00 5.10 E2 2.55 2.60 2.65 eT – 0.70 – eR – 0.
PAGE 21
8.5. 49-pin VFBGA E A1 BALL ID 0.10 D A1 TOP VIEW A A2 SIDEVIEW E1 G e F E D D1 COMMON DIMENSIONS (Unit of Measure = mm) C B SYMBOL A A 1 A1 BALL CORNER 2 3 4 5 b 6 7 e 49 - Ø0.35 ±0.05 BOTTOM VIEW MIN NOM MAX – – 1.00 A1 0.20 – – A2 0.65 – – D 4.90 5.00 5.10 D1 E4.90 3.90 BSC 5.00 5.10 E1 b NOTE 3.90 BSC 0.30 0.35 e 0.40 0.65 BSC 3/14/08 TITLE 49C2, 49-ball (7 x 7 array), 0.65mm pitch, Package Drawing Contact: packagedrawings@atmel.com 5.0 x 5.0 x 1.
PAGE 22
Atmel Corporation © 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com 2016 Atmel Corporation. / Rev.: Atmel-42715C-ATmega324PA_Datasheet_Summary-10/2016 ® ® ® Atmel , Atmel logo and combinations thereof, Enabling Unlimited Possibilities , AVR , and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others.