Datasheet

© 2009 Microchip Technology Inc. DS39689F-page 259
PIC18F2221/2321/4221/4321 FAMILY
24.0 SPECIAL FEATURES OF THE
CPU
PIC18F2221/2321/4221/4321 family devices include
several features intended to maximize reliability and
minimize cost through elimination of external
components. These are:
• Oscillator Selection
• Resets:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• ID Locations
• In-Circuit Serial Programming
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 3.0
“Oscillator Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, PIC18F2221/2321/4221/
4321 family devices have a Watchdog Timer, which is
either permanently enabled via the Configuration bits
or software controlled (if configured as disabled).
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immediately on start-up, while the primary clock source
completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
24.1 Configuration Bits
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh), which
can only be accessed using table reads and table writes.
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,
a TBLWT instruction with the TBLPTR pointing to the
Configuration register sets up the address and the data
for the Configuration register write. Setting the WR bit
starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 7.5 “Writing
to Flash Program Memory”.
TABLE 24-1: CONFIGURATION BITS AND DEVICE IDs
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default/
Unprogrammed
Value
300001h CONFIG1H IESO FCMEN
— — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111
300002h CONFIG2L
— — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111
300003h CONFIG2H
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN ---1 1111
300005h CONFIG3H MCLRE
— — — — LPT1OSC PBADEN CCP2MX 1--- -011
300006h CONFIG4L DEBUG
XINST BBSIZ1 BBSIZ0 rLVP—STVREN1000 01-1
300008h CONFIG5L
— — — — — —CP1CP0---- --11
300009h CONFIG5H CPD CPB
— — — — — — 11-- ----
30000Ah CONFIG6L
— — — — — —WRT1WRT0---- --11
30000Bh CONFIG6H WRTD WRTB WRTC
— — — — — 111- ----
30000Ch CONFIG7L
— — — — — — EBTR1 EBTR0 ---- --11
30000Dh CONFIG7H
—EBTRB— — — — — — -1-- ----
3FFFFEh DEVID1
(1)
DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx
(2)
3FFFFFh DEVID2
(1)
DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 1100
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, maintain as ‘0’.
Shaded cells are unimplemented, read as ‘0’.
Note 1: Unimplemented in PIC18F2221/4221 devices; maintain these bits set.
2: See Register 24-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.