Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TLLGA 48 (5.5x5.5) 32-Bit 50 MHz I/O number 36

Features

• High-performance, Low-power 32-bit Atmel

AVR

Microcontroller

– Compact Single-cycle RISC Instruction Set Including DSP Instructions

– Read-modify-write Instructions and Atomic Bit Manipulation

– Performance

• Up to 64DMIPS Running at 50MHz from Flash (1 Flash Wait State)

• Up to 36DMIPS Running at 25MHz from Flash (0 Flash Wait State)

– Memory Protection Unit (MPU)

• Secure Access Unit (SAU) providing User-defined Peripheral Protection

• picoPower

Technology for Ultra-low Power Consumption

• Multi-hierarchy Bus System

– High-performance Data Transfers on Separate Buses for Increased Performance

– 12 Peripheral DMA Channels improve Speed for Peripheral Communication

• Internal High-speed Flash

– 256Kbytes, 128Kbytes, and 64Kbytes Versions

– Single-cycle Access up to 25MHz

– FlashVault Technology Allows Pre-programmed Secure Library Support for End

User Applications

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 100,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User-defined Configuration Area

• Internal High-speed SRAM, Single-cycle Access at Full Speed

– 32Kbytes (256Kbytes and 128Kbytes Flash) and 16Kbytes (64Kbytes Flash)

• Interrupt Controller (INTC)

– Autovectored Low-latency Interrupt Service with Programmable Priority

• External Interrupt Controller (EIC)

• Peripheral Event System for Direct Peripheral to Peripheral Communication

• System Functions

– Power and Clock Manager

– SleepWalking Power Saving Control

– Internal System RC Oscillator (RCSYS)

– 32 KHz Oscillator

– Multipurpose Oscillator, Phase Locked Loop (PLL), and Digital Frequency Locked

Loop (DFLL)

• Windowed Watchdog Timer (WDT)

• Asynchronous Timer (AST) with Real-time Clock Capability

– Counter or Calendar Mode Supported

• Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency

• Universal Serial Bus (USBC)

– Full Speed and Low Speed USB Device Support

– Multi-packet Ping-pong Mode

• Six 16-bit Timer/Counter (TC) Channels

– External Clock Inputs, PWM, Capture, and Various Counting Capabilities

• 36 PWM Channels (PWMA)

– 12-bit PWM with a Source Clock up to 150MHz

• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– Independent Baudrate Generator, Support for SPI

– Support for Hardware Handshaking

32142DS–06/2013

32-bit Atmel

AVR

Microcontroller

ATUC256L3U

ATUC128L3U

ATUC64L3U

ATUC256L4U

ATUC128L4U

ATUC64L4U

Summary

Summary of content (45 pages)

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Features • High-performance, Low-power 32-bit Atmel® AVR® Microcontroller • • • • • • • • • • • • • • • – Compact Single-cycle RISC Instruction Set Including DSP Instructions – Read-modify-write Instructions and Atomic Bit Manipulation – Performance • Up to 64DMIPS Running at 50MHz from Flash (1 Flash Wait State) • Up to 36DMIPS Running at 25MHz from Flash (0 Flash Wait State) – Memory Protection Unit (MPU) • Secure Access Unit (SAU) providing User-defined Peripheral Protection picoPower® Technology f
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ATUC64/128/256L3/4U • One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals – Up to 15 SPI Slaves can be Addressed • Two Master and Two Slave Two-wire Interfaces (TWI), 400kbit/s I2C-compatible • One 8-channel Analog-to-digital Converter (ADC) with up to 12 Bits Resolution – Internal Temperature Sensor • Eight Analog Comparators (AC) with Optional Window Detection • Capacitive Touch (CAT) Module • • • • • • • – Hardware-assisted Atmel® AVR® QTouch® and Atmel® AVR® QMatrix Touch A
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ATUC64/128/256L3/4U 1. Description The Atmel® AVR® ATUC64/128/256L3/4U is a complete system-on-chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a highperformance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and high performance.
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ATUC64/128/256L3/4U The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing it to a known reference clock. The Full-speed USB 2.0 device interface (USBC) supports several USB classes at the same time, thanks to the rich end-point configuration. The device includes six identical 16-bit Timer/Counter (TC) channels.
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ATUC64/128/256L3/4U 2. Overview Block Diagram Figure 2-1. Block Diagram EVTO_N TCK TDO TDI TMS DATAOUT JTAG INTERFACE DATA INTERFACE M M S AVR32UC CPU NEXUS CLASS 2+ OCD aWire RESET_N INSTR INTERFACE MEMORY INTERFACE MCKO MDO[5..0] MSEO[1..
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ATUC64/128/256L3/4U 2.2 Configuration Summary Table 2-1.
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ATUC64/128/256L3/4U 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Section . ATUC64/128/256L4U TQFP48/QFN48 Pinout 36 35 34 33 32 31 30 29 28 27 26 25 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 Figure 3-1.
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ATUC64/128/256L3/4U ATUC64/128/256L4U TLLGA48 Pinout 37 36 35 34 33 32 31 30 29 28 27 26 25 PA15 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 Figure 3-2.
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ATUC64/128/256L3/4U PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB22 PB21 PB09 PA04 VDDIO GND PA11 PA13 PA20 ATUC64/128/256L3U TQFP64/QFN64 Pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Figure 3-3.
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ATUC64/128/256L3/4U Peripheral Multiplexing on I/O lines 3.1.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1.
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ATUC64/128/256L3/4U Table 3-1.
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ATUC64/128/256L3/4U Table 3-1. 3.
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ATUC64/128/256L3/4U 3.2.2 Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed function has priority in case multiple functions are enabled on the same pin. Table 3-2. 3.2.
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ATUC64/128/256L3/4U Table 3-4. 3.2.5 Nexus OCD AUX Port Connections Pin AXS=1 AXS=0 EVTO_N PA04 PA04 MCKO PA06 PB01 MSEO[1] PA07 PB11 MSEO[0] PA11 PB12 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more information about this. Table 3-5. 3.2.
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ATUC64/128/256L3/4U 3.3 Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-7.
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ATUC64/128/256L3/4U Table 3-7.
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ATUC64/128/256L3/4U Table 3-7.
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ATUC64/128/256L3/4U Table 3-8. Signal Description List, Continued Signal Name Function MSEO1 - MSEO0 Trace Frame Control EVTI_N Event In EVTO_N Event Out Type Active Level Comments Output Input Low Output Low General Purpose I/O pin PA22 - PA00 Parallel I/O Controller I/O Port 0 I/O PB27 - PB00 Parallel I/O Controller I/O Port 1 I/O Note: 1. See Section 6. on page 40 3.4 I/O Line Considerations 3.4.1 JTAG Pins The JTAG is enabled if TCK is low while the RESET_N pin is released.
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ATUC64/128/256L3/4U 3.4.5 TWI Pins PA05/PA07/PA17 When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the same characteristics as other GPIO pins. After reset a TWI function is selected on these pins instead of the GPIO. Please refer to the GPIO Module Configuration chapter for details. 3.4.
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ATUC64/128/256L3/4U 3.4.10 ADC Input Pins These pins are regular I/O pins powered from the VDDIO. However, when these pins are used for ADC inputs, the voltage applied to the pin must not exceed 1.98V. Internal circuitry ensures that the pin cannot be used as an analog input pin when the I/O drives to VDD. When the pins are not used for ADC inputs, the pins may be driven to the full I/O voltage range.
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ATUC64/128/256L3/4U 4. Mechanical Characteristics 4.1 4.1.1 Thermal Considerations Thermal Data Table 4-1 summarizes the thermal resistance data depending on the package. Table 4-1. 4.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ JA Junction-to-ambient thermal resistance Still Air TQFP48 54.4 JC Junction-to-case thermal resistance TQFP48 15.7 JA Junction-to-ambient thermal resistance QFN48 26.0 JC Junction-to-case thermal resistance QFN48 1.
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ATUC64/128/256L3/4U 4.2 Package Drawings Figure 4-1. TQFP-48 Package Drawing Table 4-2. Device and Package Maximum Weight 140 Table 4-3. mg Package Characteristics Moisture Sensitivity Level Table 4-4.
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ATUC64/128/256L3/4U Figure 4-2. Note: QFN-48 Package Drawing The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 4-5. Device and Package Maximum Weight 140 Table 4-6. mg Package Characteristics Moisture Sensitivity Level Table 4-7.
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ATUC64/128/256L3/4U Figure 4-3. TLLGA-48 Package Drawing Table 4-8. Device and Package Maximum Weight 39.3 Table 4-9. mg Package Characteristics Moisture Sensitivity Level Table 4-10.
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ATUC64/128/256L3/4U Figure 4-4. TQFP-64 Package Drawing Table 4-11. Device and Package Maximum Weight 300 Table 4-12. mg Package Characteristics Moisture Sensitivity Level Table 4-13.
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ATUC64/128/256L3/4U Figure 4-5. Note: QFN-64 Package Drawing The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 4-14. Device and Package Maximum Weight 200 Table 4-15. mg Package Characteristics Moisture Sensitivity Level Table 4-16.
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ATUC64/128/256L3/4U 4.3 Soldering Profile Table 4-17 gives the recommended soldering profile from J-STD-20. Table 4-17.
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ATUC64/128/256L3/4U 5. Ordering Information Table 5-1.
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ATUC64/128/256L3/4U Table 5-1.
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ATUC64/128/256L3/4U 6. Errata 6.1 6.1.1 Rev. C SCIF 1. The RC32K output on PA20 is not always permanently disabled The RC32K output on PA20 may sometimes re-appear. Fix/Workaround Before using RC32K for other purposes, the following procedure has to be followed in order to properly disable it: - Run the CPU on RCSYS - Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT - Enable RC32K by writing a one to SCIF.RC32KCR.
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ATUC64/128/256L3/4U 4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. 5.
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ATUC64/128/256L3/4U eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency. This results in premature loss of charge from the sense capacitors and thus increased variability of the acquired count values. Fix/Workaround Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11, 13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register. 2.
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ATUC64/128/256L3/4U - Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as zero. 2. PLLCOUNT value larger than zero can cause PLLEN glitch Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN signal during asynchronous wake up. Fix/Workaround The lock-masking mechanism for the PLL should not be used. The PLLCOUNT field of the PLL Control Register should always be written to zero. 3.
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ATUC64/128/256L3/4U 4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. 5.
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ATUC64/128/256L3/4U Disable the Ready interrupt in the interrupt handler when receiving the interrupt. When an operation that triggers the Busy/Ready bit is started, wait until the ready bit is low in the Status Register before enabling the interrupt. 6.2.6 TC 1. Channel chaining skips first pulse for upper channel When chaining two channels using the Block Mode Register, the first pulse of the clock between the channels is skipped.
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ATUC64/128/256L3/4U Issue a dummy read to address 0x100000000 before MEMORY_SPEED_REQUEST command and use this formula instead: issuing the 7f aw f sab = ---------------CV – 3 6.2.9 Flash 1. Corrupted data in flash may happen after flash page write operations After a flash page write operation from an external in situ programmer, reading (data read or code fetch) in flash may fail. This may lead to an exception or to others errors derived from this corrupted read access.
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ATUC64/128/256L3/4U The flash programming time is now: Table 6-1. Flash Characteristics Symbol Parameter TFPP Page programming time TFPE Page erase time TFFP Fuse programming time TFEA Full chip erase time (EA) TFCE JTAG chip erase time (CHIP_ERASE) Conditions Min Typ Max Unit 7.5 7.5 fCLK_HSB= 50MHz 1 ms 9 fCLK_HSB= 115kHz 250 Fix/Workaround None. 4. Power Manager 5.
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ATUC64/128/256L3/4U Under certain circumstances, the lock signal from the Phase Locked Loop (PLL) oscillator may not go back to zero after the PLL oscillator has been disabled. This can cause the propagation of clock signals with the wrong frequency to parts of the system that use the PLL clock. Fix/Workaround PLL must be turned off before entering STOP, DEEPSTOP or STATIC sleep modes. If PLL has been turned off, a delay of 30us must be observed after the PLL has been enabled again before the SCIF.
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ATUC64/128/256L3/4U 6.3.5 GPIO 1. Clearing Interrupt flags can mask other interrupts When clearing interrupt flags in a GPIO port, interrupts on other pins of that port, happening in the same clock cycle will not be registered. Fix/Workaround Read the PVR register of the port before and after clearing the interrupt to see if any pin change has happened while clearing the interrupt. If any change occurred in the PVR between the reads, they must be treated as an interrupt. 6.3.6 SPI 1.
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ATUC64/128/256L3/4U 6.3.7 TWI 1. TWIS may not wake the device from sleep mode If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condition, the CPU may not wake upon a TWIS address match. The request is NACKed. Fix/Workaround When using the TWI address match to wake the device from sleep, do not switch to sleep modes deeper than Frozen.
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ATUC64/128/256L3/4U Fix/Workaround Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle for the upper channel. After the dummy cycle has been generated, indicated by the SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real values. 6.3.10 ADCIFB 1. ADCIFB DMA transfer does not work with divided PBA clock DMA requests from the ADCIFB will not be performed when the PBA clock is slower than the HSB clock.
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ATUC64/128/256L3/4U 6.3.12 aWire 1. aWire MEMORY_SPEED_REQUEST command does not return correct CV The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to the formula in the aWire Debug Interface chapter. Fix/Workaround Issue a dummy read to address 0x100000000 before issuing the MEMORY_SPEED_REQUEST command and use this formula instead: 7f aw f sab = ---------------CV – 3 6.3.13 Flash 1.
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ATUC64/128/256L3/4U 7. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 7.1 7.2 7.3 Rev. D – 06/2013 1. Updated the datasheet with a new ATmel blue logo and the last page. 2. Added Flash errata. Rev. C – 01/2012 1. Description: DFLL frequency is 20 to 150MHz, not 40 to 150MHz. 2. Block Diagram: GCLK_IN is input, not output.
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ATUC64/128/256L3/4U Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 4 2.1 Block Diagram ...................................................................................................5 2.
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Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Roa D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.