Datasheet

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MAX174/MX574A/MX674A
Industry-Standard, Complete 12-Bit ADCs
Note 6: Timing specifications guaranteed by design. All input control signals specified with t
R
= t
F
= 5ns (10% to 90% of +5V) and
timed from a voltage level of +1.6V. See loading circuits in Figures 1 and 2.
TIMING CHARACTERISTICS—MAX174/MX574A/MX674A
(V
L
= +5V, V
CC
= +15V or +12V, V
EE
= -15V or -12V.)
(Note 6)
PARAMETER SYMBOL CONDITIONS
T
A
= +25°C
T
A
= -40°C TO +85°C
T
A
= 0°C TO +70° C
T
A
= -55°C TO +125°C
UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
CONVERT START TIMING—FULL CONTROL MODE
STS Delay from CE t
DSC
C
L
= 50pF 100 200 250 320 ns
CE Pulse Width t
HEC
50 15 50 50 ns
CS to CE Setup
t
SSC
50 50 50 ns
CS Low During CE High
t
HSC
50 50 50 ns
R/C to CE Setup
t
SRC
50 50 50 ns
R/C Low During CE High
t
HRC
50 50 50 ns
A0 to CE Setup t
SAC
0 0 0 ns
A0 Valid During CE High t
HAC
50 50 50 ns
READ TIMING—FULL CONTROL MODE
Access Time (From CE) t
DD
C
L
= 100pF 60 120 150 200 ns
Data Valid After CE Low t
HD
25 40 20 15 ns
Output Float Delay t
HL
75 100 120 ns
CS to CE Setup
t
SSR
50 50 50 ns
R/C to CE Setup
t
SRR
0 0 0 ns
A0 to CE Setup t
SAR
50 50 50 ns
CS Valid After CE Low
t
HSR
0 0 0 ns
R/C High After CE Low
t
HRR
0 0 0 ns
A0 Valid After CE Low t
HAR
0 0 0 ns
STAND-ALONE MODE
Low R/C Pulse Width
t
HRL
50 15 50 50 ns
STS Delay from R/C
t
DS
115 200 250 320 ns
Data Valid After R/C Low
t
HDR
25 40 20 15 ns
STS Delay After Data Valid t
HS
MX574A 300 600 1000 300 1000 300 1000
nsMX674A 30 320 600 30 600 30 600
MAX174 30 140 300 30 300 30 400
High R/C Pulse Width
t
HRH
150 150 200 ns
Data Access Time t
DDR
C
L
= 100pF 60 120 150 200 ns