Instruction Manual

17.3.4 PLL-Based Programmable Oscillator Control Register (PLLF)
Register Description: PLL-Based Programmable Oscillator Control Register
Register Name: PLLF
Register Address: Module 05h, Index 04h
Bits 15 to 11: Reserved.
Read returns 0.
Bits 10 and 9: PLL Reference Clock Divide Control (PLLC[1:0]). Selects reference clock-divide ratio.
00 selects 1024 to support a 16MHz system clock
01 selects 512 to support an 8MHz system clock
10 selects 256 to support a 4MHz system clock
11 selects 128 to support a 2MHz system clock
Bits 8 to 0: PLL Fine Frequency Control (PLLF[8:0]). PLL output clock frequency is (768 + PLLF) x (SYSCLK)/1024, where SYSCLK
is the system clock frequency and PLLF represents a value from 0 to 511. PLLF defaults to 256 upon reset.
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MAXQ7667 User’s Guide
r = read, w = write
Note: PLLF is cleared to 0100h on all forms of reset.
Bit #
15 14 13 12 11 10 98
Name — — — — — PLLC1 PLLC0 PLLF8
Reset 0 0 0 0 0 0 0 1
Access r r r r r rw r w rw
Bit #
76543210
Name PLLF7 PLLF6 PLLF5 PLLF4 PLLF3 PLLF2 PLLF1 PLLF0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw