Instruction Manual

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MAXQ7667 User’s Guide
9.1.2 Master Mode
The master mode selection enables the MAXQ7667 to control transfer cycles on the SPI bus. An SPI master device drives the SCLK
and the SS pins on the SPI bus. Transfers are initiated when firmware writes a character to the SPIB. The CHR bit selects between 8-
bit or 16-bit transfer cycles. Data is shifted out serially, with MSB first on the MOSI pin using the SCLK as the shift clock. The SPI bus is
a full-duplex bus, so as data is shifted out of the MOSI pin, new data is returned from the slave device into the master shift register on
the MISO pin. When the transfer cycle begins, the STBY flag is set and the SS pin is asserted, followed by clearing of the SPIC bit by
the user. At the completion of the transfer the SPIC flag is set and STBY flag clears. If auxiliary digital I/O pins are used as additional
SS lines, these must be asserted under software control immediately preceding the SPIB register data write. The SPI port flags can be
monitored by a polling routine or by interrupts. The SPI port baud rate is determined by the master clock setting, as programmed in the
SPICK register. The MAXQ7667 can run up to one-half the system clock rate.
The following steps should be taken to initialize and set up the SPI port for master mode operation.
1) If SPI port is enabled:
a. Wait until STBY clears.
b. Disable SPI port.
2) If interrupts are used:
a. Disable interrupts in the SPICF (ESPII, bit 7).
b. Clear flags SPICK, ROVR, WCOL, MODF.
3) Set SPI port baud rate in the SPICK register (from 1/2 to 1/512th of SYSCLK).
4) Set SPI clocking mode, character length, and enable interrupts in the SPICF register.
5) Set SPI master mode, which automatically configures the SPI port as follows: MISO (port 1.5 as input), MOSI (port 1.4 as output),
and SCLK (port 1.6 as output). Mode-fault enable can be enabled here, if desired.
6) Enable the SPI port in the SPICN.
Once the port is configured as an SPI bus master, do the following to initiate a transfer cycle:
1) Assert the SS pin low. (Any GPIO can be used in place of the SS pin.)
2) Write a character to the SPIB. STBY is set (1).
3) A series of SCLKs shifts the contents of the SPIB to the selected slave device, while the contents of the slave device are shifted in
through the LSB of the master shift register. The number of serial shift clocks required is set by the CHR bit, enabling either 8-bit
or 16-bit transfer cycles.
4) Once the transfer is complete:
a. The serial register loads the completed incoming data into the read buffer.
b. The SPIC flag sets, marking the end of the transfer cycle and notifying the µC that the read buffer has valid data.
c. If interrupts are enabled, an interrupt to the µC is issued.
5) Data should be read from the SPIB, and the SPIC flag can be cleared in the SPICN.
6) Additional data transfer is possible by repeating steps 2 to 5.
7) Once done, deassert the SS pin high.