Owner's manual

Bit 3: Operand Count Select (OPCS). This bit defines how many operands must be loaded to trigger a multiply or multiply-accumu-

late/subtract operation (except when SQU = 1 since this implicitly specifies a single operand). When this bit is cleared to logic 0, both

operands (MA and MB) must be written to trigger the operation. When this bit is set to 1, the specified operation is triggered once either

operand is written.

0 = Both operands (MA and MB) must be written to trigger the multiplier operation.

1 = Loading one operand (MA or MB) triggers the multiplier operation.

Bit 2: Multiply Negate (MSUB). Configuring this bit to logic 1 enables negation of the product for signed multiply operations and sub-

traction of the product from the accumulator (MC2:MC0) when MMAC = 1. When MSUB is configured to logic 0, the product of multi-

ply operations will not be negated and accumulation is selected when MMAC = 1.

Bit 1: Multiply-Accumulate Enable (MMAC). This bit enables the accumulate or subtract operation (as per MSUB) for the hardware

multiplier. When this bit is cleared to logic 0, the multiplier will perform only multiply operations. When this bit is set to logic 1, the mul-

tiplier will perform a multiply-accumulate or multiply-subtract operation based upon the MSUB bit.

0 = Accumulate/subtract operation disabled.

1 = Accumulate/subtract operation enabled.

Bit 0: Signed-Unsigned Select (SUS). This bit determines the data type of the operands. When this bit is cleared to logic 0, the

operands are treated as two’s complement values and the multiplier performs a signed operation. When this bit is set to logic 1, the

operands are treated as absolute magnitudes and the multiplier performs an unsigned operation.

0 = Signed operands.

1 = Unsigned operands.

13.2.2 Multiplier Operand A Register (MA)

Bits 15 to 0: Multiplier Operand A Register Bits 15 to 0 (MA.15 to MA.0). This operand A register is used by the application code

to load 16-bit values for multiplier operations.

MAXQ7665/MAXQ7666 User’s Guide

13-4

Bit #

15 14 13 12 11 10 9 8

Name MA.15 MA.14 MA.13 MA.12 MA.11 MA.10 MA.9 MA.8

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw rw rw rw rw

Bit #

76543210

Name MA.7 MA.6 MA.5 MA.4 MA.3 MA.2 MA.1 MA.0

Reset 0 0 0 0 0 0 0 0

Access rw rw rw rw rw rw rw rw

r = read, w = write

Note: This register is cleared to 0000h on all forms of reset.

Maxim Integrated