Owner's manual

9.3 SPI Operation

The MAXQ7665/MAXQ7666 SPI can be viewed as a synchronous serial I/O port that shifts a data stream of 8 or 16 bits between periph-

eral devices. Data is shifted in and out of the SPI through the programmable shift registers that are formed by serially connecting the

master’s shift register and a slave shift register. The SPI bus is typically implemented with one master device and multiple slave devices.

Each slave device has a unique SS pin that is used to enable transfers to that device. Figure 9-2 shows a typical SPI bus configuration.

During an SPI transfer, data is simultaneously transmitted and received. The serial clock signal (SCLK) synchronizes shifting and sam-

pling of the bit stream on the two serial data pins. For both the master and the slave, data is shifted out of the shift registers on one

edge of SCLK and latched into the shift registers on the opposite SCLK clock edge.

The SPI module operates in one of two modes once enabled by setting the SPI enable bit (SPIEN) in the SPI control register. The mas-

ter mode bit (MSTM) selects the operating mode and the source of the SCLK signal.

9.3.1 SPI Master Operation

The MAXQ7665/MAXQ7666 SPI module is placed in master mode by setting the master mode enable (MSTM) bit in the SPI control

Only an SPI master device can initiate a data transfer. The master is responsible for manually selecting/deselecting the desired slave

devices. This can be done using a general-purpose output pin. Writing a data character to the SPI shift register (SPIB) while in master mode

starts a data transfer. The SPI master immediately shifts out the data serially on the MOSI pin, most significant bit first, while providing the

serial clock on SCLK output. New data is simultaneously received on the MISO pin into the least significant bit of the shift register.

The data transfer format (clock polarity and phase), character length, and baud rate are configurable as described in later sections.

During the transfer, the SPI transfer busy (STBY) flag is set to indicate that a transfer is in progress. At the end of the transfer, the data

contained in the shift register is moved into the receive data buffer, the STBY bit is cleared by hardware, and the SPI transfer complete

flag (SPIC) is set. Setting the SPIC bit generates an interrupt request if SPI interrupt sources are enabled (ESPII = 1). Also, for an inter-

rupt request to be generated global interrupt masks IM1 (in the IMR register) and IGE (in the IC peripheral register) must also be enabled.

MAXQ7665/MAXQ7666 User’s Guide

9-9

Figure 9-2. SPI Bus Configuration

MOSI

SPI SLAVE

MISO

SCLK

MOSI

MISO

SCLK

MISO

SPI MASTER

SCLK

SS1

SS2

Maxim Integrated