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Bit 2: Bit 2 Edge Detect (IE2). This bit is set when a negative edge (IT2 = 1) or a positive edge (IT2 = 0) is detected on the interrupt
2 pin. Setting this bit to 1 generates an interrupt to the CPU if enabled. This bit remains set until cleared by software or a reset. It must
be cleared by software before exiting the interrupt source routine or another interrupt will be generated as long as this bit is set. Note
that this flag register simply indicates whether an edge has been detected at port 0 and is not affected by the state of EIE0.
Bit 1: Bit 1 Edge Detect (IE1). This bit is set when a negative edge (IT1 = 1) or a positive edge (IT1 = 0) is detected on the interrupt
1 pin. Setting this bit to 1 generates an interrupt to the CPU if enabled. This bit remains set until cleared by software or a reset. It must
be cleared by software before exiting the interrupt source routine or another interrupt will be generated as long as this bit is set. Note
that this flag register simply indicates whether an edge has been detected at port 0 and is not affected by the state of EIE0.
Bit 0: Bit 0 Edge Detect (IE0). This bit is set when a negative edge (IT0 = 1) or a positive edge (IT0 = 0) is detected on the interrupt
0 pin. Setting this bit to 1 generates an interrupt to the CPU if enabled. This bit remains set until cleared by software or a reset. It must
be cleared by software before exiting the interrupt source routine or another interrupt will be generated as long as this bit is set. Note
that this flag register simply indicates whether an edge has been detected at port 0 and is not affected by the state of EIE0.
8.2.3 Port 0 Input Register (PI0)
Register Description: Port 0 Input Register
Register Name: PI0
Register Address: Module 00h, Index 08h
Bits 15 to 8: Reserved. Read returns 0, write ignored.
Bits 7 to 0: Port 0 Input Register Bits 7 to 0 (PI0.7 to PI0.0). Port 0 is a Type D I/O port. The PI0 register always reflects the logic
state of its pins when read.
MAXQ7665/MAXQ7666 User’s Guide
8-5
r = read, s = dependent on pin’s state
Note: The reset value for this register is dependent on the logical states of the pins.
Bit #
15 14 13 12 11 10 9 8
Name — — — — — — — —
Reset 0 0 0 0 0 0 0 0
Access r rrrrrrr
Bit #
76543210
Name PI0.7 PI0.6 PI0.5 PI0.4 PI0.3 PI0.2 PI0.1 PI0.0
Reset s s s s s s s s
Access r rrrrrrr
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