Owner's manual

1.2.4.2 Interrupt System Operation
The interrupt handler hardware responds to any interrupt event when it is enabled. An interrupt event occurs when an interrupt flag is
set. All interrupt requests are sampled at the rising edge of the clock and can be serviced by the processor one clock cycle later,
assuming the request does not hit the interrupt exception window. The one-cycle stall between detection and acknowledgement/ser-
vicing is due to the fact that the current instruction may also be accessing the stack. For this reason, the CPU must allow the current
instruction to complete before pushing the stack and vectoring to IV. If an interrupt exception window is generated by the currently exe-
cuting instruction, the following instruction must be executed, so the interrupt service routine will be delayed an additional cycle.
Interrupt operation in the MAXQ7665/MAXQ7666 CPU is essentially a state machine generated long CALL instruction. When the inter-
rupt handler services an interrupt, it temporarily takes control of the CPU to perform the following sequence of actions:
1) The next instruction fetch from program memory is cancelled.
2) The return address is pushed on to the stack.
3) The INS bit is set to 1 to prevent recursive interrupt calls.
4) The instruction pointer is set to the location of the interrupt service routine (contained in the Interrupt Vector register).
5) The CPU begins executing the interrupt service routine.
Once the interrupt service routine completes, it should use the RETI instruction to return to the main program. Execution of RETI
involves the following sequence of actions:
1) The return address is popped off the stack.
2) The INS bit is cleared to 0 to re-enable interrupt handling.
3) The instruction pointer is set to the return address that was popped off the stack.
4) The CPU continues execution of the main program.
Pending interrupt requests will not interrupt an RETI instruction; a new interrupt will be serviced after first being acknowledged in the
execution cycle which follows the RETI instruction and then after the standard one stall cycle of interrupt latency. This means there will
be at least two cycles between back-to-back interrupts.
1.2.4.3 Synchronous vs. Asynchronous Interrupt Sources
Interrupt sources can be classified as either asynchronous or synchronous. All internal interrupts are synchronous interrupts. An internal
interrupt is directly routed to the interrupt handler that can be recognized in one cycle. All external interrupts are asynchronous interrupts
by nature. When the device is not in stop mode, asynchronous interrupt sources are passed through a 3-clock sampling/glitch filter cir-
cuit before being routed to the interrupt handler. The sampling/glitch filter circuit is running on the undivided source clock (i.e., before
PMME, CD1:0-controlled clock divide) such that the number of system clocks required to recognize an asynchronous interrupt request
depends upon the system clock divide ratio:
• if the system clock divide ratio is 1, the interrupt request is recognized after 3 system clock;
• if the system clock divide ratio is 2, the interrupt request is recognized after 2 system clock;
• if the system clock divide ratio is 4 or greater, the interrupt request is recognized after 1 system clock;
An interrupt request with a pulse width less than three undivided clock cycles is not recognized. Note that the granularity of interrupt
source is at module level. Synchronous interrupts and sampled asynchronous interrupts assigned to the same module produce a sin-
gle interrupt to the interrupt handler.
External interrupts, when enabled, can be used as switchback sources from power management mode. There is no latency associat-
ed with the switchback because the circuit is being clocked by an undivided clock source versus the divide-by-256 system clock. For
the same reason, there is no latency for other switchback sources that do not qualify as interrupt sources.
MAXQ7665/MAXQ7666 User’s Guide
1-24
Maxim Integrated