Owner's manual

MAXQ7665/MAXQ7666 User’s Guide
4-4
SECTION 4: CONTROLLER AREA NETWORK (CAN) MODULE
The MAXQ7665/MAXQ7666 smart data-acquisition microcontrollers incorporate a single CAN controller (CAN 0), which provides oper-
ating modes that are fully compliant with the CAN2.0B specification. The CAN unit provides 15 message centers, each with capabili-
ty to use 11-bit standard or 29-bit extended acceptance identifiers. Except where explicitly noted, the MAXQ7665 and MAXQ7666 fea-
tures are identical.
The CAN controller features include the following:
• Full CAN implementation with compliance to CAN2.0A/B protocol standard
• Programmable bit rates from 10kbps to 1Mbps
• 15 Message Centers (14 Tx or Rx, 1 Rx only with FIFO)
• Standard 11-bit or extended 29-bit identification modes
• Support for DeviceNET™, SDS, and higher level CAN protocols
• Remote frame support
• SIESTA low-power mode
• Wakeup on CANRXD edge transition
• Programmable loopback mode
• Support for multiple prioritized interrupt sources: message center interrupts, status interrupts, and error interrupts
• 256 bytes internal dual port memory for information exchange between CAN controller and microcontroller
4.1 Architecture
The microcontroller interface to the CAN controller is broken into two groups of registers. To simplify the software associated with the
operation of the CAN controller, all the global CAN status and controls, as well as the individual message center control/status regis-
ters, are located in the directly accessible peripheral register map. The remaining registers associated with the data identification, iden-
tification masks, format, and data for each message center is located in 256 bytes dual port memory. The access to the dual port data
memory by the CAN controller is direct while the access to the dual port memory by the microcontroller is through the CAN 0 data
pointer (C0DP) and CAN 0 data buffer (C0DB) registers located in the peripheral register map.
The basic functions covered by the CAN controllers begin with the capability to use 11-bit standard or 29-bit extended acceptance
identifiers, as programmed by the microcontroller for each message center. The CAN unit provides 15 message centers, each having
a standard 8-byte data field. The first 14 message centers are programmable in either transmit or receive mode. Message center 15
is designed as a receive-only message center with a FIFO buffer to prevent the inadvertent loss of data when the microcontroller is
busy. This FIFO buffer is utilized when the microcontroller is not allowed time to retrieve the incoming message prior to the acceptance
of a second message into message center 15. Message center 15 also utilizes an independent set of mask registers and identifica-
tion registers, which are only applied once an incoming message has not been accepted by any of the first 14 message centers. A
second filter test is also supported for all message centers (1 to 15) to allow the CAN controller to use two separate 8-bit media masks
and media arbitration fields to verify the contents of the first two bytes of data of each incoming message, before accepting an incom-
ing message. This feature allows the CAN unit to directly support the use of higher CAN protocols, which make use of the first and/or
second byte of data as a part of the acceptance layer for storing incoming messages. Each message center can also be programmed
independently to perform testing of the incoming data with or without the use of the global masks.
Global controls and status registers in the CAN module allow the microcontroller to evaluate error messages, validate new data and
the location of such data, establish the bus timing for the CAN bus, establish the identification mask bits, and verify the source of indi-
vidual messages. Each message center register in dual-port memory is individually equipped with the necessary status and controls
to establish direction, interrupt generation, identification mode (standard or extended), data field size, data status, automatic remote
frame request and acknowledgment, and masked or nonmasked identification acceptance testing.
DeviceNET is a trademark of Open DeviceNet Vendor Association.
Maxim Integrated